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SN54LV02A, SN74LV02A
SCLS390K – APRIL 1998 – REVISED FEBRUARY 2015
SNx4LV02A Quadruple 2-Input Positive-NOR Gates
1 Features
2 Applications
•
•
•
•
•
•
•
•
•
1
•
•
•
•
•
2-V to 5.5-V VCC Operation
Max tpd of 6.5 ns at 5 V
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
> 2.3 V at VCC = 3.3 V, TA = 25°C
Support Mixed-Mode Voltage Operation on All
Ports
Ioff Supports Live insertion, Partial Power Down
Mode, and Back Drive Protection
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model
– 200-V Machine Model
– 1000-V Charged-Device Model
Handset: Smartphone
Network Switch
Health & Fitness / Wearables
PDAs
TV (LCD)
Power Infrastructure
3 Description
The SNx4LV02A devices are quadruple 2-input
positive-NOR gates designed for 2-V to 5.5-V VCC
operation.
The SNx4LV02A devices perform the Boolean
function Y = A + B or Y = A ● B in positive logic.
Device Information(1)
PART NUMBER
PACKAGE
SNx4LV02A
BODY SIZE (NOM)
VQFN (14)
3.50 mm x 3.50 mm
SOIC (14)
8.65 mm × 3.91 mm
SOP (14)
10.30 mm x 5.30 mm
SSOP (14)
6.20 mm x 5.30 mm
TSSOP (14)
5.00 mm x 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
4 Simplified Schematic
A
Y
B
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN54LV02A, SN74LV02A
SCLS390K – APRIL 1998 – REVISED FEBRUARY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
4
4
5
5
6
6
6
6
7
7
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics, VCC = 2.5 V ± 0.2 V ........
Switching Characteristics, VCC = 3.3 V ± 0.3 V ........
Switching Characteristics, VCC = 5 V ± 0.5 V ...........
Noise Characteristics ................................................
Operating Characteristics........................................
Typical Characteristics ............................................
Parameter Measurement Information .................. 8
9
Detailed Description .............................................. 9
9.1
9.2
9.3
9.4
Overview ...................................................................
Functional Block Diagram .........................................
Feature Description...................................................
Device Functional Modes..........................................
9
9
9
9
10 Application and Implementation........................ 10
10.1 Application Information.......................................... 10
10.2 Typical Application ............................................... 10
11 Power Supply Recommendations ..................... 11
12 Layout................................................................... 12
12.1 Layout Guidelines ................................................. 12
12.2 Layout Example .................................................... 12
13 Device and Documentation Support ................. 12
13.1
13.2
13.3
13.4
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
12
12
12
12
14 Mechanical, Packaging, and Orderable
Information ........................................................... 13
5 Revision History
Changes from Revision I (April 2005) to Revision K
•
2
Page
Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table,
Typical Characteristics, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
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SCLS390K – APRIL 1998 – REVISED FEBRUARY 2015
6 Pin Configuration and Functions
(TOP VIEW)
(TOP VIEW)
(TOP VIEW)
NC - No internal Connection
Pin Functions
PIN
NO.
TYPE
NAME
DESCRIPTION
1
1Y
O
1Y output
2
1A
I
1A input
3
1B
I
1B input
4
2Y
O
2Y output
5
2A
I
2A input
6
2B
I
2B input
7
GND
—
8
3A
I
3A input
9
3B
I
3B input
10
3Y
O
3Y output
11
4A
I
4A input
12
4B
I
4B input
13
4Y
O
4Y output
14
VCC
—
VCC
GND
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SCLS390K – APRIL 1998 – REVISED FEBRUARY 2015
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
Supply voltage range
–0.5
7
UNIT
V
(2)
VI
Input voltage range
–0.5
7
V
VO
Voltage range applied to any output in the high-impedance or power-off state (2)
–0.5
7
V
VO
Output voltage range (2) (3)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–20
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
VO = 0 to VCC
±25
mA
±50
mA
150
°C
Continuous current through VCC or GND
Tstg
(1)
(2)
(3)
Storage temperature range
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
This value is limited to 5.5-V maximum.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
4
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
±1500
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins (2)
±2000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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SCLS390K – APRIL 1998 – REVISED FEBRUARY 2015
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
SN54LV02A (2)
VCC
MAX
2
5.5
Supply voltage
VCC = 2 V
VIH
High-level input voltage
SN74LV02A
MIN
Low-level input voltage
MAX
2
5.5
1.5
1.5
VCC = 2.3 V to 2.7 V
VCC × 0.7
VCC × 0.7
VCC = 3 V to 3.6 V
VCC × 0.7
VCC × 0.7
VCC = 4.5 V to 5.5 V
VCC × 0.7
UNIT
V
V
VCC × 0.7
VCC = 2 V
VIL
MIN
0.5
0.5
VCC = 2.3 V to 2.7 V
VCC × 0.3
VCC × 0.3
VCC = 3 V to 3.6 V
VCC × 0.3
VCC × 0.3
VCC = 4.5 V to 5.5 V
VCC × 0.3
VCC × 0.3
V
VI
Input voltage
0
5.5
0
5.5
VO
Output voltage
0
5.5
0
5.5
V
–50
–50
µA
VCC = 2.3 V to 2.7 V
–2
–2
VCC = 3 V to 3.6 V
–6
–6
–12
–12
VCC = 2 V
IOH
High-level output current
VCC = 4.5 V to 5.5 V
VCC = 2 V
IIH
Low-level output current
Δt/Δv
Input transition rise or fall rate
50
50
VCC = 2.3 V to 2.7 V
2
2
VCC = 3 V to 3.6 V
6
6
VCC = 4.5 V to 5.5 V
12
12
VCC = 2.3 V to 2.7 V
200
200
VCC = 3 V to 3.6 V
100
100
20
20
VCC = 4.5 V to 5.5 V
TA
(1)
(2)
Operating free-air temperature
–55
125
–40
V
mA
mA
ns/V
125
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs (SCBA004).
Product Preview.
7.4 Thermal Information
SN74LV02A
THERMAL METRIC (1)
D
DB
DGV
NS
PW
RGY
14 PINS
14 PINS
14 PINS
14 PINS
14 PINS
14 PINS
RθJA
Junction-to-ambient thermal resistance
97.5
109.5
133.3
92.2
125.1
59.0
RθJC(top)
Junction-to-case (top) thermal
resistance
58.7
62.1
55.6
49.8
53.7
72.5
RθJB
Junction-to-board thermal resistance
51.8
56.9
66.3
51.0
66.9
35.0
ψJT
Junction-to-top characterization
parameter
22.6
22.6
7.8
15.7
7.6
3.9
ψJB
Junction-to-board characterization
parameter
51.6
56.3
56.6
50.6
66.3
35.1
–
–
–
–
–
15.4
RθJC(bot)
(1)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).
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SCLS390K – APRIL 1998 – REVISED FEBRUARY 2015
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7.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
MAX
MIN
IOL = –2 mA
2.3 V
2
2
2
IOL = –6 mA
3V
2.48
2.48
2.48
IOL = –12 mA
4.5 V
3.8
3.8
3.8
IOL = 50 µA
2 V to
5.5 V
IOL = 2 mA
2.3 V
0.4
0.4
0.4
IOL = 6 mA
3V
0.44
0.44
0.44
IOL = 12 mA
4.5 V
0.55
0.55
0.55
II
VI = 5.5 V or GND
0 to
5.5 V
±1
±1
±1
µA
ICC
VI = VCC or GND,
5.5
20
20
20
µA
Ioff
VI or VO = 0 to 5.5 V
0
5
5
5
µA
Ci
VI = VCC or GND
IO = 0
VCC –
0.1
UNIT
MAX
2 V to
5.5 V
VOL
VCC –
0.1
–40°C to 125°C
SN74LV02A
IOL = –50 µA
VOH
(1)
–40°C to 85°C
SN74LV02A
SN54LV02A (1)
VCC
VCC –
0.1
0.1
3.3 V
0.1
1.6
0.1
1.6
1.6
V
pF
Product Preview.
7.6 Switching Characteristics, VCC = 2.5 V ± 0.2 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER
tpd
(1)
FROM
(INPUT)
TO
(OUTPUT)
A or B
Y
LOAD
CAPACITANCE
TA = 25°C
MIN
SN54LV02A
–40°C to 85°C
SN74LV02A
–40°C to 125°C
SN74LV02A
UNIT
TYP
MAX
MIN
MAX
MIN
MAX
MIN
MAX
CL = 15 pF
8.3 (1)
12.4 (1)
1 (1)
15 (1)
1
15
1
17.5
CL = 50 pF
11 (1)
16.1 (1)
1
19
1
19
1
21.5
ns
On products compliant to MIL-PRF-38535, this parameter is not production tested.
7.7 Switching Characteristics, VCC = 3.3 V ± 0.3 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER
tpd
(1)
FROM
(INPUT)
TO
(OUTPUT)
A or B
Y
LOAD
CAPACITANCE
TA = 25°C
MIN
–40°C to 85°C
SN74LV02A
SN54LV02A
–40°C to 125°C
SN74LV02A
TYP
MAX
MIN
MAX
MIN
MAX
MIN
MAX
CL = 15 pF
5.6 (1)
7.9 (1)
1 (1)
9.5 (1)
1
9.5
1
11.5
CL = 50 pF
(1)
(1)
1
13
1
13
1
15
7.6
11.4
UNIT
ns
On products compliant to MIL-PRF-38535, this parameter is not production tested.
7.8 Switching Characteristics, VCC = 5 V ± 0.5 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER
tpd
(1)
6
FROM
(INPUT)
TO
(OUTPUT)
A or B
Y
LOAD
CAPACITANCE
TA = 25°C
MIN
SN54LV02A
–40°C to 85°C
SN74LV02A
–40°C to 125°C
SN74LV02A
TYP
MAX
MIN
MAX
MIN
MAX
MIN
CL = 15 pF
3.9 (1)
5.5 (1)
1 (1)
6.5 (1)
1
6.5
1
8
CL = 50 pF
(1)
(1)
1
8.5
1
8.5
1
10
5.3
7.5
UNIT
MAX
ns
On products compliant to MIL-PRF-38535, this parameter is not production tested.
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SCLS390K – APRIL 1998 – REVISED FEBRUARY 2015
7.9 Noise Characteristics (1)
VCC = 3.3 V, CL = 50 pF, TA = 25°C
SN74LV02A
PARAMETER
MIN
TYP
MAX
UNIT
VOL(P)
Quiet output, maximum dynamic VOL
0.2
0.8
V
VOL(V)
Quiet output, minimum dynamic VOL
–0.1
–0.8
V
VOH(V)
Quiet output, minimum dynamic VOH
3.2
VIH(D)
High-level dynamic input voltage
VIL(D)
Low-level dynamic input voltage
(1)
V
2.31
V
0.99
V
Characteristics are for surface-mount packages only.
7.10 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
CL = 50 pF,
f = 10 MHz
VCC
TYP
3.3 V
8.9
5V
3
UNIT
pF
7.11 Typical Characteristics
5
9
TPD in ns
8
4
7
TPD (ns)
TPD (ns)
6
5
4
3
2
3
2
1
1
TPD in ns
0
1
2
3
4
5
VCC (V)
6
0
-100
-50
0
50
Temperature (qC)
D001
Figure 1. TPD vs Temperature
100
150
D002
Figure 2. TPD vs VCC at 25°C
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8 Parameter Measurement Information
Figure 3. Load Circuit and Voltage Waveforms
8
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9 Detailed Description
9.1 Overview
The SN74LV02A devices are quadruple 2-input positive-NOR gates designed for 2-V to 5.5-V VCC operation.
The SN74LV02A devices perform the Boolean function Y = A + B or Y = A ● B in positive logic.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the devices when they are powered down.
9.2 Functional Block Diagram
A
Y
B
Figure 4. Logic Diagram (Positive Logic)
9.3 Feature Description
•
•
•
Wide operating voltage range
– Operates from 2 V to 5.5 V
Allows down voltage translation
– Inputs accept voltages to 5.5 V
Ioff feature allows voltages on the inputs and outputs when VCC is 0 V
9.4 Device Functional Modes
Table 1. Function Table
(Each Gate)
INPUT
B
OUTPUT
Y
H
X
L
X
H
L
L
L
H
A
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SCLS390K – APRIL 1998 – REVISED FEBRUARY 2015
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The SN74LV02A is a Low drive CMOS device that can be used for a multitude of bus interface type applications
where output ringing is a concern. The low drive and slow edge rates will minimize overshoot and undershoot on
the outputs. The inputs can accept voltages to 5.5 V at any valid VCC making it Ideal for down translation.
10.2 Typical Application
5-V Accessory
3.3 V or 5 V Regulated
0.1 µF
5-V
System
Logic
µC or
System
Logic
Figure 5. Typical Application Schematic
10.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create fast
edges into light loads so routing and load conditions should be considered to prevent ringing.
10.2.2 Detailed Design Procedure
1. Recommended Input Conditions
– For specified High and low levels, see VIH and VIL in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
2. Recommend Output Conditions
– Load currents should not exceed 25 mA per output and 50 mA total for the part.
– Outputs should not be pulled above VCC.
10
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Typical Application (continued)
10.2.3 Application Curves
Figure 6. Typical Application Curve
11 Power Supply Recommendations
The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, a 0.1 μf capacitor is recommended and if there are multiple VCC terminals then .01 μf or .022 μf capactior
is recommended for each power terminal. It is ok to parallel multiple bypass capacitors to reject different
frequencies of noise. 0.1 μf and 1 μf capacitors are commonly used in parallel. The bypass capacitor should be
installed as close to the power terminal as possible for best results.
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12 Layout
12.1 Layout Guidelines
When using multiple bit logic devices inputs should not ever float. In many cases, functions or parts of functions
of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only
3 of the 4 buffer gates are used. Such input pins should not be left unconnected because the undefined voltages
at the outside connections result in undefined operational states. Specified below are the rules that must be
observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low
bias to prevent them from floating. The logic level that should be applied to any particular unused input depends
on the function of the device. Generally they will be tied to GND or VCC whichever make more sense or is more
convenient. It is generally OK to float outputs unless the part is a transceiver. If the transceiver has an output
enable pin it will disable the outputs section of the part when asserted. This will not disable the input section of
the I.O’s so they also cannot float when disabled.
12.2 Layout Example
Vcc
Input
Unused Input
Output
Output
Unused Input
Input
Figure 7. Layout Diagram
13 Device and Documentation Support
13.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
SN74LV02A
Click here
Click here
Click here
Click here
Click here
13.2 Trademarks
All trademarks are the property of their respective owners.
13.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12
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SCLS390K – APRIL 1998 – REVISED FEBRUARY 2015
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 1998–2015, Texas Instruments Incorporated
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13
PACKAGE OPTION ADDENDUM
www.ti.com
13-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN74LV02AD
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV02A
SN74LV02ADBR
ACTIVE
SSOP
DB
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV02A
SN74LV02ADBRE4
ACTIVE
SSOP
DB
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV02A
SN74LV02ADGVR
ACTIVE
TVSOP
DGV
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV02A
SN74LV02ADR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV02A
SN74LV02ANSR
ACTIVE
SO
NS
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
74LV02A
SN74LV02APW
ACTIVE
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV02A
SN74LV02APWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV02A
SN74LV02APWRG4
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV02A
SN74LV02APWT
ACTIVE
TSSOP
PW
14
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV02A
SN74LV02ARGYR
ACTIVE
VQFN
RGY
14
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LV02A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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