SN74LV125A
SCES124O – DECEMBER 1997 – REVISED MAY 2022
SN74LV125A Quadruple Bus Buffer Gates With 3-State Outputs
1 Features
2 Applications
•
•
•
•
•
•
•
•
•
•
•
•
•
•
2-V to 5.5-V VCC Operation
Max tpd of 6 ns at 5 V
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
> 2.3 V at VCC = 3.3 V, TA = 25°C
Support Mixed-Mode Voltage Operation on
All Ports
Ioff Supports Partial-Power-Down Mode Operation
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 4000-V Human-Body Model
– 200-V Machine Model
– 2000-V Charged-Device Model
Flow Meters
Solid State Drives (SSDs): Enterprise
Power Over Ethernet (PoE)
Programmable Logic Controllers
Motor Drives and Controls
Electronic Points of Sale
3 Description
The SN74LV125A quadruple bus buffer gate is
designed for 2-V to 5.5-V VCC operation.
Device Information
PART NUMBER(1)
SN74LV125A
(1)
1Y
DGV (TVSOP, 14)
3.60 mm x 4.40 mm
D (SOIC, 14)
8.65 mm × 3.90 mm
NS (SO, 14)
10.20 mm x 5.30 mm
DB (SSOP, 14)
6.20 mm x 5.30 mm
PW (TSSOP, 14)
5.00 mm x 4.40 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
3A
3Y
4OE
2OE
2A
BODY SIZE (NOM)
3OE
1OE
1A
PACKAGE
2Y
4A
4Y
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LV125A
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
Pin Functions.................................................................... 3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................6
6.6 Switching Characteristics, VCC = 2.5 V ± 0.2 V...........6
6.7 Switching Characteristics, VCC = 3.3 V ± 0.3 V...........6
6.8 Switching Characteristics, VCC = 5 V ± 0.5 V..............7
6.9 Noise Characteristics.................................................. 7
6.10 Operating Characteristics......................................... 7
6.11 Typical Characteristics.............................................. 7
7 Parameter Measurement Information............................ 8
8 Detailed Description........................................................9
8.1 Overview..................................................................... 9
8.2 Functional Block Diagram........................................... 9
8.3 Feature Description.....................................................9
8.4 Device Functional Modes............................................9
9 Application and Implementation.................................. 10
9.1 Application Information............................................. 10
9.2 Typical Application.................................................... 10
10 Power Supply Recommendations..............................11
11 Layout........................................................................... 12
11.1 Layout Guidelines................................................... 12
11.2 Layout Example...................................................... 12
12 Device and Documentation Support..........................12
12.1 Related Links.......................................................... 12
12.2 Trademarks............................................................. 12
12.3 Electrostatic Discharge Caution..............................12
12.4 Glossary..................................................................12
13 Mechanical, Packaging, and Orderable
Information.................................................................... 12
4 Revision History
Changes from Revision N (January 2015) to Revision O (May 2022)
Page
• Updated the numbering, formatting, tables, figures, and cross-references throughout the document to reflect
modern data sheet standards............................................................................................................................. 4
Changes from Revision M (December 2014) to Revision N (January 2015)
Page
• Added Tj spec to Absolute Maximum Ratings table........................................................................................... 4
• Added text to Overview section ......................................................................................................................... 9
Changes from Revision L (April 2005) to Revision M (December 2014)
Page
• Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information
table, Typical Characteristics, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section................... 1
• Deleted Ordering Information table.....................................................................................................................1
• Changed MAX operating temperature to 125°C in Recommended Operating Conditions table. ...................... 5
2
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5 Pin Configuration and Functions
2
13
3
12
4
11
5
10
6
9
7
8
VCC
4OE
4A
4Y
3OE
3A
3Y
1A
1Y
2OE
2A
2Y
VCC
14
1
14
2
13 4OE
3
12 4A
4Y
4
11
5
10 3OE
9 3A
6
7
8
3Y
1
GND
1OE
1A
1Y
2OE
2A
2Y
GND
SN74LV125A . . . RGY PACKAGE
(TOP VIEW)
1OE
SN74LV125A . . . D, DB, DGV, N, NS,
OR PW PACKAGE
(TOP VIEW)
Pin Functions
PIN
NO.
NAME
1
1OE
2
3
TYPE(1)
DESCRIPTION
I
Output Enable 1, Active Low
1A
I
1A Input
1Y
O
1Y Output
4
2OE
I
Output Enable 2, Active Low
5
2A
I
2A Input
6
2Y
O
2Y Output
7
GND
—
Ground Pin
8
3Y
O
3Y Output
9
3A
I
3A Input
10
3OE
I
Output Enable 3, Active Low
11
4Y
O
4Y Output
12
4A
I
4A Input
13
4OE
I
Output Enable 4, Active Low
14
VCC
—
(1)
Power Pin
Signal Types: I = Input, O = Output, I/O = Input or Output.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
VCC
MIN(1)
MAX
–0.5
7
V
–0.5
7
V
–0.5
7
V
–0.5
VCC + 0.5
Supply voltage
range(2)
VI
Input voltage
VO
Voltage range applied to any output in the high-impedance or power-off state(2)
range(2) (3)
UNIT
VO
Output voltage
IIK
Input clamp current
VI < 0
–20
mA
V
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
VO = 0 to VCC
±35
mA
Continuous current through VCC or GND
±70
mA
Tj
Junction temperature
150
°C
Tstg
Storage temperature
150
°C
(1)
(2)
(3)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Section 6.3 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
This value is limited to 5.5-V maximum.
6.2 ESD Ratings
MAX
V(ESD)
(1)
(2)
4
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
±4000
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins(2)
±2000
Machine Model (MM)
±200
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
SN74LV125A
VCC
MIN
MAX
2
5.5
Supply voltage
VCC = 2 V
VIH
High-level input voltage
Low-level input voltage
VI
Input voltage
VO
Output voltage
VCC × 0.7
VCC = 3 V to 3.6 V
VCC × 0.7
VCC = 4.5 V to 5.5 V
VCC × 0.7
V
0.5
VCC = 2.3 V to 2.7 V
VCC × 0.3
VCC = 3 V to 3.6 V
VCC × 0.3
VCC = 4.5 V to 5.5 V
High-level output current
5.5
High or low state
0
VCC
3-state
0
5.5
–50
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
∆t/∆v
Input transition rise or fall rate
TA
Operating free-air temperature
–8
50
VCC = 2.3 V to 2.7 V
µA
mA
µA
2
VCC = 3 V to 3.6 V
8
VCC = 4.5 V to 5.5 V
16
VCC = 2.3 V to 2.7 V
200
VCC = 3 V to 3.6 V
100
VCC = 4.5 V to 5.5 V
(1)
V
–16
VCC = 2 V
Low-level output current
V
–2
VCC = 4.5 V to 5.5 V
IOL
V
VCC × 0.3
0
VCC = 2 V
IOH
V
1.5
VCC = 2.3 V to 2.7 V
VCC = 2 V
VIL
UNIT
mA
ns/V
20
–40
125
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs (SCBA004).
6.4 Thermal Information
SN74LV125A
THERMAL
METRIC(1)
D
DB
DGV
N
NS
PW
RGY
UNIT
14 PINS
RθJA
Junction-to-ambient thermal
resistance
92.7
105.0
127.6
89.2
89.6
119.8
55.0
RθJC(top)
Junction-to-case (top) thermal
resistance
54.1
57.5
50.7
47.0
47.2
48.6
67.4
RθJB
Junction-to-board thermal resistance
47.0
52.3
60.5
47.9
48.4
61.5
31.0
ψJT
Junction-to-top characterization
parameter
18.9
19.1
6.1
14.1
14.0
5.7
2.6
ψJB
Junction-to-board characterization
parameter
46.7
51.8
59.8
47.5
48.1
61.0
31.1
RθJC(bot)
Junction-to-case (bottom) thermal
resistance
N/A
N/A
N/A
N/A
N/A
N/A
11.6
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).
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6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA = 25°C
VCC
MIN
–40°C to 85°C
TYP
MAX
MIN
MAX
MAX
UNIT
2 V to
5.5 V
IOH = –2 mA
2.3 V
2
2
2
IOH = –8 mA
3V
2.48
2.48
2.48
IOH = –16 mA
4.5 V
3.8
3.8
3.8
IOL = 50 µA
2 V to
5.5 V
0.1
0.1
0.1
IOL = 2 mA
2.3 V
0.4
0.4
0.4
IOL = 8 mA
3V
0.44
0.44
0.44
IOL = 16 mA
4.5 V
0.55
0.55
0.55
II
VI = 5.5 V or GND
0 to
5.5 V
±1
±1
±1
µA
VOL
IOZ
VO = VCC or GND
ICC
VI = VCC or GND,
Ioff
VI or VO = 0 to 5.5 V
Ci
IO = 0
VI = VCC or GND
VCC – 0.1
MIN
IOH = –50 µA
VOH
VCC – 0.1
–40°C to 125°C
VCC – 0.1
V
V
5.5 V
±5
±5
±5
µA
5.5 V
20
20
20
µA
5
5
5
µA
0
3.3 V
1.6
5V
1.6
pF
6.6 Switching Characteristics, VCC = 2.5 V ± 0.2 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
ten
OE
LOAD
CAPACITANCE
TA = 25°C
MIN
–40°C to 85°C
MAX
MIN
MAX
MIN
MAX
Y
6.8(1)
13(1)
1
15.5
1
17
Y
7(1)
13(1)
1
15.5
1
17
14.7(1)
CL = 15 pF
tdis
OE
Y
5.1(1)
1
17
1
18
tpd
A
Y
8.7
16.5
1
18.5
1
20
ten
OE
Y
8.8
16.5
1
18.5
1
20
tdis
OE
Y
7.3
18.2
1
20.5
1
21.5
CL = 50 pF
tsk(o)
(1)
–40°C to 125°C
TYP
2
2
UNIT
ns
ns
2
On products compliant to MIL-PRF-38535, this parameter is not production tested.
6.7 Switching Characteristics, VCC = 3.3 V ± 0.3 V
over recommended operating free-air temperature range(unless otherwise noted) (see Figure 7-1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
Y
ten
OE
Y
LOAD
CAPACITANCE
CL = 15 pF
TA = 25°C
MIN
MIN
MAX
MIN
4.8(1)
8(1)
1
9.5
1
11
4.8(1)
8(1)
1
9.5
1
10.5
9.7(1)
1
11.5
1
12.5
11.5
1
13
1
14.5
6.2
11.5
1
13
1
14
5.5
13.2
1
15
1
16
tdis
OE
Y
tpd
A
Y
6.1
ten
OE
Y
tdis
OE
Y
tsk(o)
(1)
6
–40°C to 125°C
MAX
4.1(1)
CL = 50 pF
–40°C to 85°C
TYP
1.5
1.5
MAX
UNIT
ns
ns
1.5
On products compliant to MIL-PRF-38535, this parameter is not production tested.
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6.8 Switching Characteristics, VCC = 5 V ± 0.5 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
LOAD
CAPACITANCE
TA = 25°C
MIN
–40°C to 85°C
TYP
MAX
MIN
MAX
MIN
MAX
Y
3.4(1)
5.5(1)
1
6.5
1
7.5
3.4(1)
5.1(1)
ten
OE
Y
1
6
1
7
tdis
OE
Y
3.2(1)
6.8(1)
1
8
1
9
tpd
A
Y
4.3
7.5
1
8.5
1
9.5
ten
OE
Y
4.4
7.1
1
8
1
9
tdis
OE
Y
4
8.8
1
10
1
11
CL = 15 pF
CL = 50 pF
tsk(o)
(1)
–40°C to 125°C
1
1
UNIT
ns
ns
1
On products compliant to MIL-PRF-38535, this parameter is not production tested.
6.9 Noise Characteristics
VCC = 3.3 V, CL = 50 pF, TA = 25°C
SN74LV125A
PARAMETER(1)
MIN
TYP
MAX
UNIT
VOL(P)
Quiet output, maximum dynamic VOL
0.4
0.8
V
VOL(V)
Quiet output, minimum dynamic VOL
–0.3
–0.8
V
VOH(V)
Quiet output, minimum dynamic VOH
3
VIH(D)
High-level dynamic input voltage
VIL(D)
Low-level dynamic input voltage
(1)
V
2.31
V
0.99
V
Characteristics are for surface-mount packages only.
6.10 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
Outputs enabled
CL = 50 pF,
f = 10 MHz
VCC
TYP
3.3 V
15.5
5V
17.6
UNIT
pF
6.11 Typical Characteristics
7
8
6
7
6
TPD (ns)
TPD (ns)
5
4
3
2
5
4
3
2
1
1
TPD in ns
0
-100
TPD in ns
0
-50
0
50
Temperature (qC)
100
150
0
1
D001
Figure 6-1. TPD vs Temperature
2
3
VCC
4
5
6
D002
Figure 6-2. TPD vs VCC at 25°C
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7 Parameter Measurement Information
7.1
RL = 1 kΩ
From Output
Under Test
Test
Point
From Output
Under Test
VCC
Open
S1
TEST
GND
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
CL
(see Note A)
CL
(see Note A)
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
VCC
50% VCC
Timing Input
0V
tw
tsu
VCC
50% VCC
50% VCC
Input
th
VCC
50% VCC
Data Input
50% VCC
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VCC
50% VCC
Input
50% VCC
tPLH
In-Phase
Output
tPHL
VOH
50% VCC
VOL
VOH
50% VCC
VOL
tPLZ
≈VCC
50% VCC
tPZH
VOL + 0.3 V
VOL
tPHZ
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
50% VCC
0V
Output
Waveform 1
S1 at VCC
(see Note B)
tPLH
50% VCC
50% VCC
tPZL
tPHL
50% VCC
Out-of-Phase
Output
0V
VCC
Output
Control
50% VCC
VOH − 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time, with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. t PZL and tPZH are the same as ten.
G. tPHL and tPLH are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 7-1. Load Circuit And Voltage Waveforms
8
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8 Detailed Description
8.1 Overview
The SN74LV125A quadruple bus buffer gate is designed for 2-V to 5.5-V VCC operation.
These devices feature independent line drivers with 3-state outputs. Each output is disabled when the
associated output-enable (OE) input is high.
To ensure the high-impedance state during power up or power down, tie OE to VCC through a pullup resistor; the
minimum value of the resistor is determined by the current-sinking capability of the driver.
8.2 Functional Block Diagram
3OE
1OE
1A
3A
1Y
3Y
4OE
2OE
2A
4A
2Y
4Y
Figure 8-1. Logic Diagram (Positive Logic)
8.3 Feature Description
•
•
•
Wide operating voltage range
– Operates from 2 V to 5.5 V
Allows down-voltage translation
– Inputs accept voltages to 5.5 V
Ioff Feature
– Supports Live Insertion, Partial Power-Down Mode, and Back-Drive Protection
8.4 Device Functional Modes
Table 8-1. Function Table
(Each Buffer)
INPUTS(1)
(1)
(2)
OE
A
OUTPUT(2)
Y
L
H
H
L
L
L
H
X
Z
H = High Voltage Level, L =
Low Voltage Level, X = Don’t
Care
H = Driving High, L = Driving
Low, Z = High Impedance
State
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The SN74LV125A is a low-drive CMOS device that can be used for a multitude of bus interface type applications
where output ringing is a concern. The low drive and slow edge rates minimize overshoot and undershoot on the
outputs. The inputs are 5.5-V tolerant at any valid VCC, making it ideal for translating down to VCC.
9.2 Typical Application
5-V system
Regulated 3.3 V or 5 V
VCC
1OE
1A
4OE
1Y
µC or
System Logic
4A
4Y
µC
System Logic
LEDs
GND
Figure 9-1. Typical Application Schematic
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create
fast edges into light loads, so routing and load conditions should be considered to prevent ringing.
9.2.2 Detailed Design Procedure
1. Recommended Input Conditions
• For rise time and fall time specifications, see Δt/ΔV in the Section 6.3 table.
• For specified High and low levels, see VIH and VIL in the Section 6.3 table.
2. Recommend Output Conditions
• Load currents should not exceed 35 mA per output and 70 mA total for the part.
• Outputs should not be pulled above VCC.
10
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9.2.3 Application Curves
Figure 9-2. Switching Characteristics Comparison
10 Power Supply Recommendations
The power supply can be any voltage between the MIN and MAX supply voltage rating located in the Section 6.3
table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, 0.1 μF is recommended. If there are multiple VCC pins, 0.01 μF or 0.022 μF is recommended for each
power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μF and
1 μF are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as
possible for best results.
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11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states.
Specified in Figure 11-1 are rules that must be observed under all circumstances. All unused inputs of digital
logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should
be applied to any particular unused input depends on the function of the device. Generally they will be tied to
GND or VCC, whichever makes more sense or is more convenient. It is acceptable to float outputs unless the
part is a transceiver. If the transceiver has an output enable pin, it will disable the outputs section of the part
when asserted. This will not disable the input section of the I/Os so they also cannot float when disabled.
11.2 Layout Example
Vcc
Input
Unused Input
Output
Output
Unused Input
Input
Figure 11-1. Layout Diagram
12 Device and Documentation Support
12.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 12-1. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
SN74LV125A
Click here
Click here
Click here
Click here
Click here
12.2 Trademarks
All trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.4 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
12
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: SN74LV125A
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN74LV125AD
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV125A
Samples
SN74LV125ADBR
ACTIVE
SSOP
DB
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV125A
Samples
SN74LV125ADG4
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV125A
Samples
SN74LV125ADGVR
ACTIVE
TVSOP
DGV
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV125A
Samples
SN74LV125ADR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV125A
Samples
SN74LV125AN
ACTIVE
PDIP
N
14
25
RoHS &
Non-Green
NIPDAU
N / A for Pkg Type
-40 to 125
SN74LV125AN
Samples
SN74LV125ANSR
ACTIVE
SO
NS
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
74LV125A
Samples
SN74LV125APW
ACTIVE
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV125A
Samples
SN74LV125APWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV125A
Samples
SN74LV125APWRE4
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV125A
Samples
SN74LV125APWRG4
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV125A
Samples
SN74LV125APWT
ACTIVE
TSSOP
PW
14
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV125A
Samples
SN74LV125ARGYR
ACTIVE
VQFN
RGY
14
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LV125A
Samples
SN74LV125ARGYRG4
ACTIVE
VQFN
RGY
14
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LV125A
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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