SN74LV240APWR

SN74LV240A SCLS384J – SEPTEMBER 1997 – REVISED DECEMBER 2022 SN74LV240A Octal Inverting Buffers/Drivers With 3-State Outputs 1 Features 3 Description • • • These octal buffers/drivers with inverted outputs are designed for 2 V to 5.5 V VCC operation. • • • • VCC operation of 2 V to 5.5 V Max tpd of 6.5 ns at 5 V Typical VOLP (Output Ground Bounce) 2.3 V at VCC = 3.3 V, TA = 25°C Support Mixed-Mode Voltage Operation on All Ports Latch-Up Performance Exceeds 250 mA per JESD 17 Ioff Supports Live Insertion, Partial Power-Down Mode, and Back Drive Protection The ’LV240A devices are designed specifically to improve both the performance and density of 3state memory address drivers, clock drivers, and busoriented receivers and transmitters. These devices are organized as two 4-bit buffers/ line drivers with separate output-enable ( OE) inputs. When OE is low, the device passes inverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. 2 Applications • • • Handset: Smartphone Network Switch Health and Fitness / Wearables Package Information(1) PART NUMBER SN74LV240A (1) PACKAGE BODY SIZE (NOM) TVSOP (14) 3.60 mm × 4.40 mm SOIC (14) 8.65 mm × 3.91 mm SO (14) 10.30 mm × 5.30 mm SSOP (14) 6.20 mm × 5.30 mm TSSOP (14) 5.00 mm × 4.40 mm For all available packages, see the orderable addendum at the end of the data sheet. An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN74LV240A SCLS384J – SEPTEMBER 1997 – REVISED DECEMBER 2022 www.ti.com Logic Diagram (Positive Logic) 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV240A SN74LV240A www.ti.com SCLS384J – SEPTEMBER 1997 – REVISED DECEMBER 2022 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 3 5 Pin Configuration and Functions...................................4 6 Specifications.................................................................. 5 6.1 Absolute Maximum Ratings(1) .................................... 5 6.2 ESD Ratings............................................................... 5 6.3 Recommended Operating Conditions.........................6 6.4 Thermal Information....................................................6 6.5 Electrical Characteristics.............................................7 6.6 Switching Characteristics, VCC = 2.5 V ±0.2 V............8 6.7 Switching Characteristics, VCC = 3.3 V ±0.3 V............8 6.8 Switching Characteristics, VCC = 5 V ±0.5 V...............8 6.9 Noise Characteristics for SN74LV240A...................... 9 6.10 Operating Characteristics......................................... 9 6.11 Typical Characteristics.............................................. 9 7 Parameter Measurement Information.......................... 10 8 Detailed Description...................................................... 11 8.1 Overview................................................................... 11 8.2 Functional Block Diagram......................................... 11 8.3 Feature Description...................................................12 8.4 Device Functional Modes..........................................13 9 Application and Implementation.................................. 14 9.1 Application Information............................................. 14 9.2 Typical Application.................................................... 14 10 Power Supply Recommendations..............................16 11 Layout........................................................................... 16 11.1 Layout Guidelines................................................... 16 11.2 Layout Example...................................................... 16 12 Device and Documentation Support..........................17 12.1 Related Links.......................................................... 17 12.2 Receiving Notification of Documentation Updates..17 12.3 Support Resources................................................. 17 12.4 Trademarks............................................................. 17 12.5 Electrostatic Discharge Caution..............................17 12.6 Glossary..................................................................17 13 Mechanical, Packaging, and Orderable Information.................................................................... 17 4 Revision History Changes from Revision I (February 2015) to Revision J (December 2022) Page • Updated the format for tables, figures, and cross-references throughout the document....................................1 Changes from Revision H (April 2005) to Revision I (Feruary 2015) Page • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................. 1 • Updated operating free-air temperature maximum from 85°C to 125°C for SN74LV240A ................................6 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV240A 3 SN74LV240A www.ti.com SCLS384J – SEPTEMBER 1997 – REVISED DECEMBER 2022 5 Pin Configuration and Functions Figure 5-1. SN74LV240A: DB, DGV, DW, NS, or PW Package Top View Table 5-1. Pin Functions NAME(1) PIN TYPE 1OE 1 I Output enable 1 1A1 2 I 1A1 input 2Y4 3 O 2Y4 output 1A2 4 I 1A2 input 2Y3 5 O 2Y3 output 1A3 6 I 1A3 input 2Y2 7 O 2Y2 output 1A4 8 I 1A4 input 2Y1 9 O 2Y1 output GND 10 — Ground pin 2A1 11 I 2A1 input 1Y4 12 O 1Y4 output 2A2 13 I 2A2 input 1Y3 14 O 1Y3 output 2A3 15 I 2A3 input 1Y2 16 O 1Y2 output 2A4 17 I 2A4 input 1Y1 18 O 1Y1 output 2OE 19 I Output enable 2 VCC 20 — (1) 4 DESCRIPTION Power pin Signal Types: I = Input, O = Output, I/O = Input or Output Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV240A SN74LV240A www.ti.com SCLS384J – SEPTEMBER 1997 – REVISED DECEMBER 2022 6 Specifications 6.1 Absolute Maximum Ratings(1) over operating free-air temperature (unless otherwise noted) VCC MIN MAX Supply voltage –0.5 7 V voltage(2) –0.5 7 V –0.5 7 V –0.5 VCC + 0.5 VI Input VO Voltage applied to any output in the high-impedance or power-off state(2) voltage(2) (3) VO Output IIK Input clamp current VI < 0 IOK Output clamp current VO < 0 IO Continuous output current VO = 0 to VCC –35 UNIT V –20 mA –50 mA 35 mA Continuous current through VCC or GND –70 70 mA Tstg Storage temperature –65 150 °C TJ Junction Temperature 150 °C (1) (2) (3) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. The value is limited to 5.5-V maximum. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000 Machine model (A115-A) ±200 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV240A 5 SN74LV240A www.ti.com SCLS384J – SEPTEMBER 1997 – REVISED DECEMBER 2022 6.3 Recommended Operating Conditions see (1) VCC MIN MAX 2 5.5 Supply voltage VCC = 2 V VIH High-level input voltage Low-level input voltage VI Input voltage VCC = 2.3 to 2.7 V VCC × 0.7 VCC = 3 to 3.6 V VCC × 0.7 VCC = 4.5 to 5.5 V VCC × 0.7 Output voltage VCC = 2.3 to 2.7 V VCC × 0.3 VCC = 3 to 3.6 V VCC × 0.3 High-level output current 5.5 High or low state 0 VCC 3-state 0 5.5 –50 VCC = 2.3 to 2.7 V –2 VCC = 3 to 3.6 V –8 VCC = 4.5 to 5.5 V Low-level output current Δt/Δv Input transition rise or fall rate 50 VCC = 2.3 to 2.7 V 2 VCC = 3 to 3.6 V 8 VCC = 4.5 to 5.5 V 16 VCC = 2.3 to 2.7 V 200 VCC = 3 to 3.6 V 100 VCC = 4.5 to 5.5 V TA (1) V V µA mA –16 VCC = 2 V IOL V VCC × 0.3 0 VCC = 2 V IOH V 0.5 VCC = 4.5 to 5.5 V VO V 1.5 VCC = 2 V VIL UNIT µA mA ns/V 20 Operating free-air temperature –40 125 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, SCBA004. 6.4 Thermal Information DW THERMAL METRIC(1) DGV NS PW 20 PINS RθJA Junction-to-ambient thermal resistance(2) 79.2 94.5 116.2 76.7 102.4 RθJC(top) Junction-to-case (top) thermal resistance 43.7 56.4 31.2 43.2 36.5 RθJB Junction-to-board thermal resistance 47.0 49.7 57.7 44.2 53.6 ψJT Junction-to-top characterization parameter 18.6 18.5 0.9 16.8 2.4 ψJB Junction-to-board characterization parameter 46.5 49.3 57.0 43.8 52.9 (1) (2) 6 DB UNIT °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The package thermal impedance is calculated in accordance with JESD 51-7. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV240A SN74LV240A www.ti.com SCLS384J – SEPTEMBER 1997 – REVISED DECEMBER 2022 6.5 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONS PARAMETER VOH High level output voltage VCC MIN IOH = –50 µA 2 to 5.5 V VCC – 0.1 IOH = –2 mA 2.3 V IOH = –8 mA 3V IOH = –16 mA 4.5 V VOL Low level output voltage TYP MAX UNIT 2 V 2.48 3.8 IOL = 50 µA 2 to 5.5 V 0.1 IOL = 2 mA 2.3 V 0.4 IOL = 8 mA 3V 0.44 IOL = 16 mA 4.5 V 0.55 V II Input leakage current VI = 5.5 V or GND 0 to 5.5 V ±1 µA IOZ Off-State (High-Impedance State) Output Current (of a 3-State Output) VO = VCC or GND 5.5 V ±5 µA ICC Supply current VI = VCC or GND, IO = 0 5.5 V 20 µA Ioff Input/Output Power-Off Leakage Current VI or VO = 0 to 0 5.5 V 5 µA Ci Input Capacitance VI = VCC or GND 3.3 V 2.3 pF Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV240A 7 SN74LV240A www.ti.com SCLS384J – SEPTEMBER 1997 – REVISED DECEMBER 2022 6.6 Switching Characteristics, VCC = 2.5 V ±0.2 V over recommended operating free-air temperature range (unless otherwise noted) (see Section 7) PARAMETER FROM (INPUT) tpd A ten OE tdis TO (OUTPUT) Y LOAD CAPACITANCE TA = 25°C MIN CL = 15 pF OE tpd A ten OE tdis OE Y CL = 50 pF MAX UNIT MAX 6.3(1) 11.6(1) 1(2) 14(2) 8.5(1) 14.6(1) 1(2) 17(2) 9.7(1) 14.1(1) 1(2) 16(2) 8.2 14.4 1 17 10.3 17.8 1 21 14.2 19.2 1 21 tsk(o) (1) (2) (3) MIN TYP ns ns 2(3) 2 On products compliant to MIL-PRF-38535, this parameter is not production tested. This note applies to SN54LV240A only: On products compliant to MIL-PRF-38535, this parameter is not production tested. Value applies for SN74LV240A only 6.7 Switching Characteristics, VCC = 3.3 V ±0.3 V over recommended operating free-air temperature range (unless otherwise noted) (see Section 7) PARAMETER FROM (INPUT) tpd A ten OE tdis OE tpd A ten OE tdis OE TO (OUTPUT) Y LOAD CAPACITANCE TA = 25°C MIN CL = 15 pF Y CL = 50 pF MAX UNIT MAX 4.6(1) 7.5(1) 1(2) 9(2) 6.2(1) 10.6(1) 1(2) 12.5(2) 8.3(1) 12.5(1) 1(2) 13.5(2) 5.9 11 1 12.5 7.5 14.1 1 16 11.8 15 1 17 tsk(o) (1) (2) (3) MIN TYP ns ns 1.5(3) 1.5 On products compliant to MIL-PRF-38535, this parameter is not production tested. This note applies to SN54LV240A only: On products compliant to MIL-PRF-38535, this parameter is not production tested. Value applies for SN74LV240A only 6.8 Switching Characteristics, VCC = 5 V ±0.5 V over recommended operating free-air temperature range (unless otherwise noted) (see Section 7) PARAMETER FROM (INPUT) tpd A ten OE tdis OE tpd A ten OE tdis OE TO (OUTPUT) Y Y LOAD CAPACITANCE TA = 25°C MIN CL = 15 pF CL = 50 pF tsk(o) (1) (2) (3) 8 MIN MAX UNIT TYP MAX 3.4(1) 5.5(1) 1(2) 6.5(2) 4.6(1) 7.3(1) 1(2) 8.5(2) 7.4(1) 12.2(1) 1(2) 13.5(2) 4.4 7.5 1 8.5 5.6 9.3 1 10.5 9.7 14.2 1 15.5 1 ns ns 1(3) On products compliant to MIL-PRF-38535, this parameter is not production tested. This note applies to SN54LV240A only: On products compliant to MIL-PRF-38535, this parameter is not production tested. This values applies for SN74LV240A only Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV240A SN74LV240A www.ti.com SCLS384J – SEPTEMBER 1997 – REVISED DECEMBER 2022 6.9 Noise Characteristics for SN74LV240A VCC = 3.3 V, CL = 50 pF, TA = 25°C (see (1)) PARAMETER MIN TYP VOL(P) Quiet output, maximum dynamic VOL 0.56 VOL(V) Quiet output, minimum dynamic VOL –0.49 VOH(V) Quiet output, minimum dynamic VOH VIH(D) High-level dynamic input voltage VIL(D) Low-level dynamic input voltage (1) MAX UNIT V 2.82 2.31 0.99 Characteristics are for surface-mount packages only. 6.10 Operating Characteristics TA = 25°C PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS CL = 50 pF ƒ = 10 MHz VCC TYP 3.3 V 14 5V 16.4 UNIT pF 6.11 Typical Characteristics Figure 6-1. tpd vs Temperature at 3.3-V VCC Figure 6-2. tpd vs VCC at 25°C Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV240A 9 SN74LV240A www.ti.com SCLS384J – SEPTEMBER 1997 – REVISED DECEMBER 2022 7 Parameter Measurement Information 7.1 A. B. C. D. E. F. G. H. CL includes probe and jig capacitance. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. The outputs are measured one at a time, with one input transition per measurement. tPLZ and tPHZ are the same as tdis. tPZL and tPZH are the same as ten. tPHL and tPLH are the same as tpd. All parameters and waveforms are not applicable to all devices. Figure 7-1. Load Circuit and Voltage Waveforms 10 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV240A SN74LV240A www.ti.com SCLS384J – SEPTEMBER 1997 – REVISED DECEMBER 2022 8 Detailed Description 8.1 Overview These octal buffers/drivers with inverted outputs are designed for 2 V to 5.5 V VCC operation. The ’LV240A devices are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. These devices are organized as two 4-bit buffers/line drivers with separate output-enable ( OE) inputs. When OE is low, the device passes inverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. 8.2 Functional Block Diagram Figure 8-1. Logic Diagram (Positive Logic) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV240A 11 SN74LV240A SCLS384J – SEPTEMBER 1997 – REVISED DECEMBER 2022 www.ti.com 8.3 Feature Description • • • 12 Wide operating voltage range operates from 2 V to 5.5 V operation Allow down voltage translation inputs accept voltages to 5.5 V Ioff feature allows voltages on the inputs and outputs when VCC is 0 V Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV240A SN74LV240A www.ti.com SCLS384J – SEPTEMBER 1997 – REVISED DECEMBER 2022 8.4 Device Functional Modes Table 8-1. Function Table (Each Buffer) INPUTS(1) (1) (2) OUTPUT (2) OE A L H L L L H H X Z Y H = High Voltage Level, L = Low Voltage Level, X = Don’t Care H = Driving High, L = Driving Low, Z = High Impedance State Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV240A 13 SN74LV240A www.ti.com SCLS384J – SEPTEMBER 1997 – REVISED DECEMBER 2022 9 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 9.1 Application Information The SN74LV240A is a low-drive CMOS device that can be used for a multitude of bus interface type applications where the data needs to be retained or latched. It can produce 8 mA of drive current at 3.3 V making it ideal for driving multiple outputs and low-noise applications. The inputs are 5.5-V tolerant allowing it to translate down to VCC. 9.2 Typical Application Figure 9-1. Typical Application Schematic 9.2.1 Design Requirements This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus contention because it can drive currents that would exceed maximum limits. The high drive will also create fast edges into light loads so routing and load conditions should be considered to prevent ringing. 9.2.2 Detailed Design Procedure 1. Recommended input conditions • Rise time and fall time specifications see (Δt/ΔV) in Section 6.3. • Specified high and low levels. See (VIH and VIL) in Section 6.3. • Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC 2. Recommend output conditions • Load currents should not exceed 35 mA per output and 70 mA total for the part • Outputs should not be pulled above VCC 14 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV240A SN74LV240A www.ti.com SCLS384J – SEPTEMBER 1997 – REVISED DECEMBER 2022 9.2.3 Application Curve Figure 9-2. Switching Characteristics Comparison Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV240A 15 SN74LV240A SCLS384J – SEPTEMBER 1997 – REVISED DECEMBER 2022 www.ti.com 10 Power Supply Recommendations The power supply can be any voltage between the min and max supply voltage rating located in Section 6.3. Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single supply, TI recommends 0.1 µF and if there are multiple VCC terminals, then TI recommends .01 µF or .022 µF for each power terminal. It is okay to parallel multiple bypass capacitors to reject different frequencies of noise. A 0.1 µF and 1 µF are commonly used in parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results. 11 Layout 11.1 Layout Guidelines When using multiple bit logic devices inputs should not ever float. In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Specified below are the rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or VCC whichever make more sense or is more convenient. It is generally okay to float outputs unless the part is a transceiver. If the transceiver has an output enable pin it will disable the outputs section of the part when asserted. This does not disable the input section of the IOs so they cannot float when disabled. 11.2 Layout Example Figure 11-1. Layout Recommendation 16 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV240A SN74LV240A www.ti.com SCLS384J – SEPTEMBER 1997 – REVISED DECEMBER 2022 12 Device and Documentation Support 12.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 12-1. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY SN54LV240A Click here Click here Click here Click here Click here SN74LV240A Click here Click here Click here Click here Click here 12.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.3 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 12.4 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 12.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.6 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV240A 17 PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) SN74LV240ADBR ACTIVE SSOP DB 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LV240A Samples SN74LV240ADBRE4 ACTIVE SSOP DB 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LV240A Samples SN74LV240ADGVR ACTIVE TVSOP DGV 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LV240A Samples SN74LV240ADW ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LV240A Samples SN74LV240ADWR ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LV240A Samples SN74LV240ANSR ACTIVE SO NS 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 74LV240A Samples SN74LV240APW ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LV240A Samples SN74LV240APWG4 ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LV240A Samples SN74LV240APWR ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 LV240A Samples SN74LV240APWRG4 ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LV240A Samples SN74LV240APWT ACTIVE TSSOP PW 20 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LV240A Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of