SN74LV273A
SCLS399L – APRIL 1998 – REVISED NOVEMBER 2022
SN74LV273A Octal D-Type Flip-Flops With Clear
1 Features
3 Description
•
•
•
The SN74LV273A device is an octal D-type flip-flop
designed for 2-V to 5.5-V VCC operation.
•
•
•
•
•
2-V to 5.5-V VCC operation
Maximum tpd of 10.5 ns at 5 V
Typical VOLP (output ground bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (output VOH undershoot)
> 2.3 V at VCC = 3.3 V, TA = 25°C
Ioff supports partial-power-down mode operation
Supports mixed-mode voltage operation
on all ports
Latch-up performance exceeds 250 mA
per JESD 17
ESD protection exceeds JESD 22:
– 3000-V Human-Body Model
– 2000-V Charged-Device Model™
Package Information(1)
PART NUMBER
PACKAGE
SN74LV273A
2 Applications
•
•
•
•
•
•
(1)
Power sub-station controls
I/O modules; analog PLC/DCS inputs
Human machine interfaces (HMI)
Flow meters
Patient monitoring
Test and measurement solutions
1D
2D
3
4
3D
DB (SSOP, 20)
7.20 × 5.30 mm
DGV (TVSOP, 20)
5.00 × 4.40 mm
DW (SOIC, 20)
12.80 × 7.50 mm
NS (SOP, 20)
12.60 × 5.30 mm
PW (TSSOP, 20)
6.50 × 4.40 mm
RGY (VQFN 20)
4.50 × 3.50 mm
RKS (VQFN, 20)
4.50 × 2.50 mm
GQN (BGA, 20)
4.00 × 3.00 mm
ZQN (BGA, 20)
4.00 × 3.00 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
4D
7
BODY SIZE (NOM)
5D
8
6D
13
7D
14
8D
17
18
11
CLK
1D
1D
C1
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
C1
R
R
1
CLR
2
5
6
1Q
2Q
3Q
9
4Q
12
5Q
15
6Q
16
7Q
19
8Q
Logic Diagram (Positive Logic)
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LV273A
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SCLS399L – APRIL 1998 – REVISED NOVEMBER 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configurations and Functions.................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings ....................................... 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions ........................6
6.4 Thermal Information....................................................6
6.5 Electrical Characteristics.............................................7
6.6 Timing Requirements, VCC = 2.5 V ± 0.2 V.................7
6.7 Timing Requirements, VCC = 3.3 V ± 0.3 V.................7
6.8 Timing Requirements, VCC = 5 V ± 0.5 V....................8
6.9 Switching Characteristics, VCC = 2.5 V ± 0.2 V...........8
6.10 Switching Characteristics, VCC = 3.3 V ± 0.3 V.........8
6.11 Switching Characteristics, VCC = 5 V ± 0.5 V............ 9
6.12 Noise Characteristics ............................................... 9
6.13 Operating Characteristics......................................... 9
6.14 Typical Characteristics............................................ 10
7 Parameter Measurement Information.......................... 12
8 Detailed Description......................................................13
8.1 Overview................................................................... 13
8.2 Functional Block Diagram......................................... 13
8.3 Feature Description...................................................13
8.4 Device Functional Modes..........................................14
9 Application and Implementation.................................. 15
9.1 Application Information............................................. 15
9.2 Typical Application ................................................... 15
10 Power Supply Recommendations..............................18
11 Layout........................................................................... 18
11.1 Layout Guidelines................................................... 18
11.2 Layout Example...................................................... 18
12 Device and Documentation Support..........................19
12.1 Receiving Notification of Documentation Updates..19
12.2 Support Resources................................................. 19
12.3 Trademarks............................................................. 19
12.4 Electrostatic Discharge Caution..............................19
12.5 Glossary..................................................................19
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision K (April 2014) to Revision L (November 2022)
Page
• Removed 200-V Machine Model from the Features section...............................................................................1
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Added the RKS package to the data sheet.........................................................................................................1
• Added the Balanced CMOS Push-Pull Output, Latching Logic, Partial Power Down (Ioff) sections................. 13
• Removed the Design Requirements section.................................................................................................... 15
• Added the Power Considerations, Input Considerations, Output Considerations sections.............................. 15
• Updated the Layout Example section............................................................................................................... 18
Changes from Revision J (April 2005) to Revision K (December 2014)
Page
• Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information
table, Typical Characteristics, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section................... 1
• Deleted Ordering Information table.....................................................................................................................1
• Changed MAX operating temperature to 125°C in Recommended Operating Conditions table. ...................... 6
2
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VCC
19
8Q
1D
3
18
8D
2D
2Q
3Q
4
17
5
16
6
15
VCC
20
2
20
1
1Q
CLR
CLR
1
5 Pin Configurations and Functions
1Q
2
19
8Q
1D
3
18
8D
2D
4
17
7D
7D
7Q
Thermal
2Q
5
16
7Q
3Q
6
15
6Q
Pad
6Q
7
14
6D
3D
7
14
6D
4D
8
13
5D
4D
8
13
5D
4Q
9
12
5Q
12
5Q
10
11
CLK
GND
GND
Not to scale
Figure 5-1. SN74LV273A DB, DGV, DW, NS, or PW
Package, 20-Pin SSOP, TVSOP, SOP, or TSSOP
(Top View)
CLK
9
10
4Q
11
3D
Not to scale
Figure 5-2. SN74LV273A RGY or RKS Package, 20Pin VQFN (Top View)
Table 5-1. Pin Functions
PIN
NAME
NO.
TYPE(1)
DESCRIPTION
CLR
1
I
Clear Pin
1Q
2
O
1Q Output
1D
3
I
1D Input
2D
4
I
2D Input
2Q
5
O
2Q Output
3Q
6
O
3Q Output
3D
7
I
3D Input
4D
8
I
4D Input
4Q
9
O
4Q Output
GND
10
—
Ground Pin
CLK
11
I
Clock Pin
5Q
12
O
5Q Output
5D
13
I
5D Input
6D
14
I
6D Input
6Q
15
O
6Q Output
7Q
16
O
7Q Output
7D
17
I
7D Input
8D
18
I
8D Input
8Q
19
O
8Q Output
VCC
20
—
Power Pin
—
Thermal Pad(2)
Thermal Pad
(1)
(2)
I = input, O = output
RKS package only
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1 2 3 4
A
B
C
D
E
Figure 5-3. GQN or ZQN Package, 20-Pin BGA (Top View)
Table 5-2. GQN or ZQN Pin Assignments
A
4
1
2
3
4
1Q
CLR
VCC
8Q
B
2D
7D
1D
8D
C
3Q
2Q
6Q
7Q
D
4D
5D
3D
6D
E
GND
4Q
CLK
5Q
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
VCC
Supply voltage range
–0.5
7
V
VI
Input voltage range(2)
–0.5
7
V
–0.5
7
V
–0.5
VCC + 0.5
V
state(2)
VO
Voltage range applied to any output in the high-impedance or power-off
VO
Output voltage range(2) (3)
IIK
Input clamp current
VI < 0
–20
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
VO = 0 to VCC
±25
mA
±50
mA
150
°C
Continuous current through VCC or GND
Tstg
(1)
(2)
(3)
Storage temperature range
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
This value is limited to 5.5 V maximum.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
3000
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002, all
pins(2)
2000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
(1)
VCC
MIN
MAX
2
5.5
Supply voltage
VCC = 2 V
VIH
High-level input voltage
UNIT
V
1.5
VCC = 2.3 V to 2.7 V
VCC × 0.7
VCC = 3 V to 3.6 V
VCC × 0.7
VCC = 4.5 V to 5.5 V
VCC × 0.7
V
VCC = 2 V
0.5
VCC = 2.3 V to 2.7 V
VCC × 0.3
VCC = 3 V to 3.6 V
VCC × 0.3
VIL
Low-level input voltage
VI
Input voltage
0
5.5
V
VO
Output voltage
0
VCC
V
–50
µA
VCC = 4.5 V to 5.5 V
VCC × 0.3
VCC = 2 V
IOH
High-level output current
VCC = 2.3 V to 2.7 V
–2
VCC = 3 V to 3.6 V
–6
VCC = 4.5 V to 5.5 V
Low-level output current
Δt/Δv
Input transition rise or fall rate
TA
Operating free-air temperature
50
VCC = 2.3 V to 2.7 V
µA
2
VCC = 3 V to 3.6 V
6
VCC = 4.5 V to 5.5 V
12
VCC = 2.3 V to 2.7 V
200
VCC = 3 V to 3.6 V
100
VCC = 4.5 V to 5.5 V
(1)
mA
–12
VCC = 2 V
IOL
V
mA
ns/V
20
–40
125
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs (SCBA004).
6.4 Thermal Information
SN74LV273A
THERMAL
METRIC(1)
DB
DGV
DW
NS
PW
RGY
RKS
UNIT
20 PINS
RθJA
Junction-to-ambient thermal
resistance
98.7
118.1
81.8
79.4
104.7
37.1
75.2
RθJC(top)
Junction-to-case (top) thermal
resistance
60.4
33.4
47.8
45.9
38.8
46.1
79.4
RθJB
Junction-to-board thermal resistance
56.9
59.6
49.4
46.9
55.7
14.9
47.8
ψJT
Junction-to-top characterization
parameter
21.6
1.1
20.1
19.1
2.9
1.3
14.6
ψJB
Junction-to-board characterization
parameter
53.5
58.9
49.0
46.5
55.1
15.0
47.8
RθJC(bot)
Junction-to-case (bottom) thermal
resistance
—
—
—
—
—
9.8
31.5
(1)
6
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).
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6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25°C
MIN
–40°C to 85°C
TYP
MAX
MAX
MAX
UNIT
2 V to
5.5 V
IOH = –2 mA
2.3 V
2
2
2
IOH = –6 mA
3V
2.48
2.48
2.48
IOH = –12 mA
4.5 V
3.8
3.8
3.8
IOL = –50 µA
2 V to
5.5 V
0.1
0.1
0.1
IOL = –2 mA
2.3 V
0.4
0.4
0.4
IOL = –6 mA
3V
0.44
0.44
0.44
IOL = –12 mA
4.5 V
0.55
0.55
0.55
II
VI = 5.5 V or GND
0 to
5.5 V
±1
±1
±1
µA
ICC
VI = VCC or GND,
5.5 V
20
20
20
µA
Ioff
VI or VO = 0 to 5.5 V
0V
5
5
5
µA
Ci
VI = VCC or GND
VOL
IO = 0
VCC –
0.1
MIN
IOH = –50 µA
VOH
VCC –
0.1
MIN
–40°C to 125°C
3.3 V
VCC –
0.1
V
2
V
pF
6.6 Timing Requirements, VCC = 2.5 V ± 0.2 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-1)
TA = 25°C
MIN
tw
Pulse duration
tsu
Setup time, data before CLK↑
th
Hold time, data after CLK↑
CLR low
CLK high or low
Data
CLR inactive
MAX
–40°C to 85°C
MIN
MAX
–40°C to 125°C
MIN
6.5
7
7.5
7
8.5
9
8.5
10.5
12
4
4
4.5
0.5
1
2.5
MAX
UNIT
ns
ns
ns
6.7 Timing Requirements, VCC = 3.3 V ± 0.3 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-1)
TA = 25°C
MIN
tw
Pulse duration
tsu
Setup time, data before CLK↑
th
Hold time, data after CLK↑
MAX
–40°C to 85°C
MIN
MAX
–40°C to 125°C
MIN
CLR low
5
6
6.5
CLK high or low
5
6.5
7
Data
5.5
6.5
8
CLR inactive
2.5
2.5
3
1
1
2.5
MAX
UNIT
ns
ns
ns
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6.8 Timing Requirements, VCC = 5 V ± 0.5 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-1)
TA = 25°C
MIN
tw
Pulse duration
tsu
Setup time, data before CLK↑
th
Hold time, data after CLK↑
–40°C to 85°C
MAX
MIN
–40°C to 125°C
MAX
MIN
CLR low
5
5
5.5
CLK high or low
5
5
5.5
4.5
4.5
6
2
2
2.5
1
1
2
Data
CLR inactive
UNIT
MAX
ns
ns
ns
6.9 Switching Characteristics, VCC = 2.5 V ± 0.2 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
tpd
CLK
Q
tPHL
CLR
Q
tpd
CLK
Q
tPHL
CLR
Q
LOAD
CAPACITANCE
TA = 25°C
–40°C to 85°C
MIN
TYP
CL = 15 pF
55
95
45
45
CL = 50 pF
45
75
40
40
10.4
CL = 15 pF
CL = 50 pF
MAX
MIN
MAX
–40°C to 125°C
MIN
MAX
UNIT
MHz
18.3
1
20.5
1
22.5
ns
10.3
19
1
21
1
23
ns
12.9
22.1
1
25
1
27
ns
13.1
22.8
1
25.5
1
27.5
ns
2
ns
tsk(o)
2
6.10 Switching Characteristics, VCC = 3.3 V ± 0.3 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
tpd
CLK
Q
tPHL
CLR
Q
tpd
CLK
Q
tPHL
CLR
Q
tsk(o)
8
LOAD
CAPACITANCE
TA = 25°C
–40°C to 85°C
TYP
CL = 15 pF
75
140
65
65
CL = 50 pF
50
110
45
45
CL = 15 pF
CL = 50 pF
MAX
MIN
MAX
–40°C to 125°C
MIN
MIN
MAX
UNIT
MHz
7.1
13.6
1
16
1
17.5
ns
6.9
13.6
1
16
1
17.5
ns
9.1
17.1
1
19.5
1
21
ns
8.7
17.1
1
19.5
1
21
ns
1.5
ns
1.5
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6.11 Switching Characteristics, VCC = 5 V ± 0.5 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
CLK
Q
tPHL
CLR
Q
tpd
CLK
Q
tPHL
CLR
Q
–40°C to 85°C
–40°C to 125°C
MIN
TYP
CL = 15 pF
120
205
100
100
CL = 50 pF
80
160
70
70
fmax
tpd
TA = 25°C
LOAD
CAPACITANCE
CL = 15 pF
MAX
MIN
4.8
9
1
4.7
8.5
6.2
11
6
10.5
CL = 50 pF
tsk(o)
MAX
MIN
10.5
1
1
10
1
12.5
1
12
MAX
UNIT
MHz
11.5
ns
1
11
ns
1
14
ns
1
13.5
ns
1
ns
1
6.12 Noise Characteristics
VCC = 3.3 V, CL = 50 pF, TA = 25°C
SN74LV273A
PARAMETER
MIN
TYP
MAX
UNIT
VOL(P)
Quiet output, maximum dynamic VOL
0.4
0.8
V
VOL(V)
Quiet output, minimum dynamic VOL
–0.4
–0.8
V
VOH(V)
Quiet output, minimum dynamic VOH
2.9
VIH(D)
High-level dynamic input voltage
VIL(D)
Low-level dynamic input voltage
V
2.31
V
0.99
V
6.13 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
CL = 50 pF,
f = 10 MHz
VCC
TYP
3.3 V
15.9
5V
17.1
UNIT
pF
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6.14 Typical Characteristics
0.16
0.3
0.14
0.25
0.12
0.2
VOL (V)
VOL (V)
0.1
0.08
0.06
0.15
0.1
0.04
0.02
0.05
VCC = 2.3 V
VCC = 3 V
0
0
2
4
IOL (mA)
6
0
8
Figure 6-1. Output Voltage in LOW state, 2.3- and 3-V Supply
3
2.8
VOH (V)
VOH (V)
2.7
2.6
2.5
2.4
2.3
2.2
VCC = 2.3 V
VCC = 3 V
2
-8
-6
-4
IOH (mA)
-2
0
Figure 6-3. Output Voltage in HIGH state, 2.3- and 3-V Supply
6
8
IOL (mA)
10
12
14
16
5.5
5.4
5.3
5.2
5.1
5
4.9
4.8
4.7
4.6
4.5
4.4
4.3
4.2
4.1
4
-16
VCC = 4.5 V
VCC = 5.5 V
-14
-12
-10
-8
IOH (mA)
-6
-4
-2
0
0.6
VCC = 2.5 V
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
VCC = 3.3 V
VCC = 5 V
0.54
ICC - Supply Current (mA)
ICC - Supply Current (mA)
4
Figure 6-4. Output Voltage in HIGH state, 4.5- and 5.5-V Supply
0.1
0.09
0.48
0.42
0.36
0.3
0.24
0.18
0.12
0.06
0
0
0
0.25
0.5
0.75
1
1.25 1.5 1.75
VI - Input Voltage (V)
2
2.25
2.5
Figure 6-5. Supply Current across Input Voltage, 2.5-V Supply
10
2
Figure 6-2. Output Voltage in LOW state, 4.5- and 5.5-V Supply
2.9
2.1
VCC = 4.5 V
VCC = 5.5 V
0
0
0.5
1
1.5
2
2.5
3
3.5
VI - Input Voltage (V)
4
4.5
5
5.5
Figure 6-6. Supply Current across Input Voltage, 3.3- and 5-V
Supply
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6.14 Typical Characteristics (continued)
12
8
7
10
6
TPD (ns)
TPD (ns)
8
6
4
5
4
3
2
2
1
TPD in ns
TPD in ns
0
0
1
2
3
VCC
4
5
6
0
-100
D001
Figure 6-7. TPD vs VCC at 25°C
-50
0
50
Temperature (qC)
100
150
D002
Figure 6-8. TPD vs Temperature
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7 Parameter Measurement Information
RL = 1 kΩ
From Output
Under Test
Test
Point
From Output
Under Test
S1
VCC
Open
TEST
GND
CL
(see Note A)
CL
(see Note A)
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
VCC
50% VCC
Timing Input
tw
tsu
VCC
50% VCC
50% VCC
Input
0V
th
VCC
50% VCC
Data Input
50% VCC
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VCC
50% VCC
Input
50% VCC
tPLH
In-Phase
Output
tPHL
50% VCC
tPHL
Out-of-Phase
Output
0V
VOH
50% VCC
VOL
Output
Waveform 1
S1 at VCC
(see Note B)
VOH
50% VCC
VOL
C.
D.
E.
F.
G.
H.
50% VCC
0V
tPLZ
tPZL
≈VCC
50% VCC
VOL + 0.3 V
VOL
tPHZ
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
A.
B.
50% VCC
tPZH
tPLH
50% VCC
VCC
Output
Control
50% VCC
VOH – 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
CL includes probe and jig capacitance.
Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns,
tf ≤ 3 ns.
The outputs are measured one at a time, with one input transition per measurement.
tPLZ and tPHZ are the same as tdis.
tPZL and tPZH are the same as ten.
tPHL and tPLH are the same as tpd.
All parameters and waveforms are not applicable to all devices.
Figure 7-1. Load Circuit and Voltage Waveforms
12
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8 Detailed Description
8.1 Overview
The SN74LV273A device is an octal D-type flip-flop designed for 2-V to 5.5-V VCC operation.
This device is a positive-edge-triggered flip-flop with direct clear (CLR) input. Information at the data (D) inputs
meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock
pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the
positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no
effect at the output.
The SN74LV273A device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables
the outputs, preventing damaging current backflow through the devices when they are powered down.
8.2 Functional Block Diagram
1D
2D
3
4
3D
4D
7
5D
8
6D
13
7D
14
8D
17
18
11
CLK
1D
1D
C1
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
C1
R
R
1
CLR
2
5
6
1Q
2Q
3Q
9
4Q
12
5Q
15
6Q
16
7Q
19
8Q
8.3 Feature Description
8.3.1 Balanced CMOS Push-Pull Outputs
This device includes balanced CMOS push-pull outputs. The term balanced indicates that the device can sink
and source similar currents. The drive capability of this device may create fast edges into light loads, so routing
and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable
of driving larger currents than the device can sustain without being damaged. It is important for the output power
of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the
Absolute Maximum Ratings must be followed at all times.
Unused push-pull CMOS outputs should be left disconnected.
8.3.2 Latching Logic
This device includes latching logic circuitry. Latching circuits commonly include D-type latches and D-type
flip-flops, but include all logic circuits that act as volatile memory.
When the device is powered on, the state of each latch is unknown. There is no default state for each latch at
start-up.
The output state of each latching logic circuit only remains stable as long as power is applied to the device within
the supply voltage range specified in the Recommended Operating Conditions table.
8.3.3 Partial Power Down (Ioff)
This device includes circuitry to disable all outputs when the supply pin is held at 0 V. When disabled, the
outputs will neither source nor sink current, regardless of the input voltages applied. The amount of leakage
current at each output is defined by the Ioff specification in the Electrical Characteristics table.
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8.3.4 Clamp Diode Structure
Figure 8-1 shows the inputs and outputs to this device have negative clamping diodes only.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage
to the device. The input and output voltage ratings may be exceeded if the input and output clampcurrent ratings are observed.
VCC
Device
Logic
Input
Output
-IIK
-IOK
GND
Figure 8-1. Electrical Placement of Clamping Diodes for Each Input and Output
8.4 Device Functional Modes
Table 8-1. Function Table
(Each Flip-Flop)
INPUTS
CLR
14
CLK
OUTPUT
Q
D
L
X
X
L
H
↑
H
H
H
↑
L
L
H
L
X
Q0
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The SN74LV273A is a low-drive CMOS device that can be used for a multitude of bus interface type applications
where the data needs to be retained or latched. The low drive and slow edge rates will minimize overshoot and
undershoot on the outputs. The inputs are tolerant to 5.5 V at any valid VCC. This feature makes it Ideal for
translating down to the VCC level. Figure 9-2 shows the reduction in ringing compared to higher drive parts such
as AC.
9.2 Typical Application
Regulated 5 V
CLR
VCC
CLK
1D
1Q
µC
System Logic
LEDs
µC or
System Logic
8D
8Q
GND
Figure 9-1. Typical Application Schematic
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9.2.1 Power Considerations
Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions. The
supply voltage sets the device's electrical characteristics as described in the Electrical Characteristics section.
The positive voltage supply must be capable of sourcing current equal to the total current to be sourced by all
outputs of the SN74LV273A plus the maximum static supply current, ICC, listed in the Electrical Characteristics,
and any transient current required for switching. The logic device can only source as much current that is
provided by the positive supply source. Be sure to not exceed the maximum total current through VCC listed in
the Absolute Maximum Ratings.
The ground must be capable of sinking current equal to the total current to be sunk by all outputs of the
SN74LV273A plus the maximum supply current, ICC, listed in the Electrical Characteristics, and any transient
current required for switching. The logic device can only sink as much current that can be sunk into its ground
connection. Be sure to not exceed the maximum total current through GND listed in the Absolute Maximum
Ratings.
The SN74LV273A can drive a load with a total capacitance less than or equal to 50 pF while still meeting all of
the data sheet specifications. Larger capacitive loads can be applied; however, it is not recommended to exceed
50 pF.
The SN74LV273A can drive a load with total resistance described by RL ≥ VO / IO, with the output voltage and
current defined in the Electrical Characteristics table with VOH and VOL. When outputting in the HIGH state, the
output voltage in the equation is defined as the difference between the measured output voltage and the supply
voltage at the VCC pin.
Total power consumption can be calculated using the information provided in CMOS Power Consumption and
Cpd Calculation.
Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear
and Logic (SLL) Packages and Devices.
CAUTION
The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings, is an additional
limitation to prevent damage to the device. Do not violate any values listed in the Absolute Maximum
Ratings. These limits are provided to prevent damage to the device.
9.2.2 Input Considerations
Input signals must cross VIL(max) to be considered a logic LOW, and VIH(min) to be considered a logic HIGH. Do
not exceed the maximum input voltage range found in the Absolute Maximum Ratings.
Unused inputs must be terminated to either VCC or ground. The unused inputs can be directly terminated if the
input is completely unused, or they can be connected with a pull-up or pull-down resistor if the input will be used
sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used
for a default state of LOW. The drive current of the controller, leakage current into the SN74LV273A (as specified
in the Electrical Characteristics), and the desired input transition rate limits the resistor size. A 10-kΩ resistor
value is often used due to these factors.
The SN74LV273A has CMOS inputs and thus requires fast input transitions to operate correctly, as defined in
the Recommended Operating Conditions table. Slow input transitions can cause oscillations, additional power
consumption, and reduction in device reliability.
Refer to the Feature Description section for additional information regarding the inputs for this device.
16
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9.2.3 Output Considerations
The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will
decrease the output voltage as specified by the VOH specification in the Electrical Characteristics. The ground
voltage is used to produce the output LOW voltage. Sinking current into the output will increase the output
voltage as specified by the VOL specification in the Electrical Characteristics.
Push-pull outputs that could be in opposite states, even for a very short time period, should never be connected
directly together. This can cause excessive current and damage to the device.
Two channels within the same device with the same input signals can be connected in parallel for additional
output drive strength.
Unused outputs can be left floating. Do not connect outputs directly to VCC or ground.
Refer to the Feature Description section for additional information regarding the outputs for this device.
9.2.4 Detailed Design Procedure
1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the
device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout
section.
2. Ensure the capacitive load at the output is ≤ 50 pF. This is not a hard limit; it will, however, ensure optimal
performance. This can be accomplished by providing short, appropriately sized traces from the SN74LV273A
to one or more of the receiving devices.
3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum
output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load
measured in MΩ; much larger than the minimum calculated previously.
4. Thermal issues are rarely a concern for logic gates; the power consumption and thermal increase, however,
can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd
Calculation.
9.2.5 Application Curves
Figure 9-2. Switching Characteristics Comparison
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10 Power Supply Recommendations
The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, 0.1 μF is recommended. If there are multiple VCC pins, 0.01 μF or 0.022 μF is recommended for each
power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μF and
1 μF are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as
possible for best results.
11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states.
Specified in Figure 11-1 are rules that must be observed under all circumstances. All unused inputs of digital
logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should
be applied to any particular unused input depends on the function of the device. Generally they will be tied to
GND or VCC, whichever makes more sense or is more convenient. It is acceptable to float outputs unless the
part is a transceiver.
11.2 Layout Example
VCC
Recommend GND flood fill for
improved signal isolation, noise
reduction, and thermal dissipation
GND
F
CLR
1
1Q
2
20
19
8Q
1D
3
18
8D
4
17
7D
5
16
7Q
Unused input
tied to GND 2D
Unused output 2Q
left floating
Avoid 90°
corners for
signal lines
VCC
3Q
6
15
6Q
3D
7
14
6D
4D
8
13
5D
4Q
9
10
12
11
5Q
GND
GND
Bypass capacitor
placed close to the
device
CLK
Figure 11-1. Layout Example for SN74LV273A in the RKS Package
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN74LV273ADBR
ACTIVE
SSOP
DB
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV273A
Samples
SN74LV273ADBRE4
ACTIVE
SSOP
DB
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV273A
Samples
SN74LV273ADBRG4
ACTIVE
SSOP
DB
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV273A
Samples
SN74LV273ADGVR
ACTIVE
TVSOP
DGV
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV273A
Samples
SN74LV273ADW
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV273A
Samples
SN74LV273ADWG4
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV273A
Samples
SN74LV273ADWR
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV273A
Samples
SN74LV273ANSR
ACTIVE
SO
NS
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
74LV273A
Samples
SN74LV273APW
ACTIVE
TSSOP
PW
20
70
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV273A
Samples
SN74LV273APWE4
ACTIVE
TSSOP
PW
20
70
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV273A
Samples
SN74LV273APWG4
ACTIVE
TSSOP
PW
20
70
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV273A
Samples
SN74LV273APWR
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
LV273A
Samples
SN74LV273APWRE4
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV273A
Samples
SN74LV273APWRG4
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV273A
Samples
SN74LV273APWT
ACTIVE
TSSOP
PW
20
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV273A
Samples
SN74LV273ARGYR
ACTIVE
VQFN
RGY
20
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LV273A
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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3-Nov-2022
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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