SN74LV163ADGVR

SN54LV163A, SN74LV163A 4-BIT SYNCHRONOUS BINARY COUNTERS SCLS405F − APRIL 1998 − REVISED APRIL 2005 2 15 3 14 4 13 12 5 6 11 7 10 8 9 VCC RCO QA QB QC QD ENT LOAD CLK A B C D ENP 16 CLK CLR NC VCC RCO 1 SN54LV163A . . . FK PACKAGE (TOP VIEW) 15 RCO 14 QA 2 3 A B NC C D 13 QB 12 QC 4 5 11 QD 10 ENT 6 7 8 9 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 ENP GND NC 16 VCC 1 Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) SN74LV163A . . . RGY PACKAGE (TOP VIEW) SN54LV163A . . . J OR W PACKAGE SN74LV163A . . . D, DB, DGV, NS, OR PW PACKAGE (TOP VIEW) CLR CLK A B C D ENP GND D LOAD D D D CLR D 2.3 V at VCC = 3.3 V, TA = 25°C Support Mixed-Mode Voltage Operation on All Ports Internal Look Ahead for Fast Counting Carry Output for n-Bit Cascading GND D D Synchronous Counting D Synchronously Programmable D Ioff Supports Partial-Power-Down Mode QA QB NC QC QD LOAD ENT D 2-V to 5.5-V VCC Operation D Max tpd of 9.5 ns at 5 V D Typical VOLP (Output Ground Bounce) NC − No internal connection description/ordering information ORDERING INFORMATION QFN − RGY SN74LV163ARGYR Tube of 40 SN74LV163AD Reel of 2500 SN74LV163ADR SOP − NS Reel of 2000 SN74LV163ANSR 74LV163A SSOP − DB Reel of 2000 SN74LV163ADBR LV163A Tube of 90 SN74LV163APW Reel of 2000 SN74LV163APWR Reel of 250 SN74LV163APWT TVSOP − DGV Reel of 2000 SN74LV163ADGVR LV163A CDIP − J Tube of 25 SNJ54LV163AJ SNJ54LV163AJ CFP − W Tube of 150 SNJ54LV163AW SNJ54LV163AW LCCC − FK Tube of 55 SNJ54LV163AFK SNJ54LV163AFK TSSOP − PW −55°C to 125°C † TOP-SIDE MARKING Reel of 1000 SOIC − D −40°C 40 C to 85°C 85 C ORDERABLE PART NUMBER PACKAGE† TA LV163A LV163A LV163A Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright © 2005, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54LV163A, SN74LV163A 4-BIT SYNCHRONOUS BINARY COUNTERS SCLS405F − APRIL 1998 − REVISED APRIL 2005 description/ordering information (continued) The ’LV163A devices are 4-bit synchronous binary counters designed for 2-V to 5.5-V VCC operation. These synchronous, presettable counters feature an internal carry look ahead for application in high-speed counting designs. The ’LV163A devices are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes normally associated with synchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform. These counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs. The clear function for the ’LV163A devices is synchronous. A low level at the clear (CLR) input sets all four of the flip-flop outputs low after the next low-to-high transition of CLK, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The active-low output of the gate used for decoding is connected to CLR to synchronously clear the counter to 0000 (LLLL). The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. ENP, ENT, and a ripple-carry output (RCO) are instrumental in accomplishing this function. Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a high-level pulse while the count is maximum (9 or 15 with QA high). This high-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK. These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. FUNCTION TABLE INPUTS 2 CLR LOAD ENP OUTPUTS ENT CLK X QA QB QC QD FUNCTION L X X X H L X X H H X L No change No count H H L X No change No count H H H H Count up Count H X X X No change No count POST OFFICE BOX 655303 L L L L Reset to “0” A B C D Preset data • DALLAS, TEXAS 75265 SN54LV163A, SN74LV163A 4-BIT SYNCHRONOUS BINARY COUNTERS SCLS405F − APRIL 1998 − REVISED APRIL 2005 logic diagram (positive logic) LOAD ENT ENP 9 10 15 LD† 7 RCO CK† CLK CLR 2 1 CK LD R A B C D M1 G2 1, 2T/1C3 G4 3D 4R 3 M1 G2 1, 2T/1C3 G4 3D 4R 4 M1 G2 1, 2T/1C3 G4 3D 4R 5 M1 G2 1, 2T/1C3 G4 3D 4R 6 14 13 12 11 QA QB QC QD † For simplicity, routing of complementary signals LD and CK is not shown on this overall logic diagram. The uses of these signals are shown on the logic diagram of the D/T flip-flops. Pin numbers shown are for the D, DB, DGV, J, NS, PW, RGY, and W packages. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54LV163A, SN74LV163A 4-BIT SYNCHRONOUS BINARY COUNTERS SCLS405F − APRIL 1998 − REVISED APRIL 2005 logic diagram, each D/T flip-flop (positive logic) CK LD TE LD† TG TG Q TG LD† TG CK† D TG CK† R † 4 The origins of LD and CK are shown in the overall logic diagram of the device. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CK† TG CK† SN54LV163A, SN74LV163A 4-BIT SYNCHRONOUS BINARY COUNTERS SCLS405F − APRIL 1998 − REVISED APRIL 2005 typical clear, preset, count, and inhibit sequence The following sequence is illustrated below: 1. Clear outputs to zero (synchronous) 2. Preset to binary 12 3. Count to 13, 14, 15, 0, 1, and 2 4. Inhibit CLR LOAD A Data Inputs B C D CLK ENP ENT QA Data Outputs QB QC QD RCO 12 13 14 15 0 1 Count 2 Inhibit Sync Preset Clear Async Clear POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54LV163A, SN74LV163A 4-BIT SYNCHRONOUS BINARY COUNTERS SCLS405F − APRIL 1998 − REVISED APRIL 2005 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Output voltage range applied in high or low state, VO (see Notes 1 and 2) . . . . . . . . . . −0.5 V to VCC + 0.5 V Voltage range applied to any output in the power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . −0.5 V to 7 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W (see Note 3): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W (see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W (see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W (see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51-7. 4. The package thermal impedance is calculated in accordance with JESD 51-5. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54LV163A, SN74LV163A 4-BIT SYNCHRONOUS BINARY COUNTERS SCLS405F − APRIL 1998 − REVISED APRIL 2005 recommended operating conditions (see Note 5) SN54LV163A VCC MIN MAX 2 5.5 Supply voltage VCC = 2 V VIH High level input voltage High-level 1.5 Low level input voltage Low-level VI Input voltage VO Output voltage VCC × 0.7 VCC × 0.7 VCC × 0.7 VCC = 4.5 V to 5.5 V VCC × 0.7 VCC × 0.7 Input transition rise or fall rate TA Operating free-air temperature V V 0.5 0.5 VCC × 0.3 VCC × 0.3 VCC = 3 V to 3.6 V VCC × 0.3 VCC × 0.3 VCC × 0.3 5.5 0 5.5 0 VCC 0 VCC = 3 V to 3.6 V VCC V −50 μA −2 −2 −6 −6 −12 50 50 VCC = 2.3 V to 2.7 V 2 2 VCC = 3 V to 3.6 V 6 6 VCC = 4.5 V to 5.5 V 12 12 VCC = 2.3 V to 2.7 V 200 200 VCC = 3 V to 3.6 V 100 100 20 −55 V −50 −12 VCC = 4.5 V to 5.5 V V VCC × 0.3 0 VCC = 2 V Δt/Δv UNIT VCC = 2.3 V to 2.7 V VCC = 2.3 V to 2.7 V Low level output current Low-level 5.5 VCC × 0.7 VCC = 4.5 V to 5.5 V IOL 2 VCC = 2.3 V to 2.7 V VCC = 2 V High level output current High-level MAX VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V IOH MIN 1.5 VCC = 2 V VIL SN74LV163A 125 mA μA mA ns/V 20 −40 °C 85 NOTE 5: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54LV163A PARAMETER VOH TEST CONDITIONS MIN TYP SN74LV163A MAX MIN IOH = −50 μA 2 V to 5.5 V IOH = −2 mA 2.3 V 2 2 IOH = −6 mA 3V 2.48 2.48 4.5 V 3.8 IOH = −12 mA VOL VCC VCC−0.1 TYP MAX VCC−0.1 V 3.8 IOL = 50 μA 2 V to 5.5 V 0.1 0.1 IOL = 2 mA 2.3 V 0.4 0.4 IOL = 6 mA 3V 0.44 0.44 4.5 V IOL = 12 mA II VI = 5.5 V or GND ICC VI = VCC or GND, Ioff VI or VO = 0 to 5.5 V Ci VI = VCC or GND IO = 0 UNIT V 0.55 0.55 0 to 5.5 V ±1 ±1 μA 5.5 V 20 20 μA 0 5 5 μA 3.3 V 1.8 1.8 pF PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN54LV163A, SN74LV163A 4-BIT SYNCHRONOUS BINARY COUNTERS SCLS405F − APRIL 1998 − REVISED APRIL 2005 timing requirements over recommended operating VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) free-air TA = 25°C MIN tw Pulse duration, CLK high or low Set p time before CLK↑ Setup th Hold time, all synchronous inputs after CLK↑ SN54LV163A MAX 7 6 Data (A, B, C, and D) 7.5 8.5 8.5 ENP, ENT 9.5 11 11 10 11.5 11.5 1.5 1.5 1.5 TA = 25°C MIN Pulse duration, CLK high or low th Hold time, all synchronous inputs after CLK↑ MAX SN54LV163A MIN MAX MAX UNIT ns ns ns temperature range, SN74LV163A MIN 5 5 5 4 4 4 Data (A, B, C, and D) 5.5 6.5 6.5 ENP, ENT 7.5 9 9 LOAD low 8 9.5 9.5 1 1 1 CLR S t time Setup ti before b f CLK↑ MIN 6 free-air range, SN74LV163A 7 timing requirements over recommended operating VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) tsu MAX 6 LOAD low tw MIN 7 CLR tsu temperature MAX UNIT ns ns ns timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN tw Pulse duration, CLK high or low tsu S t time Setup ti before b f CLK↑ th Hold time, all synchronous inputs after CLK↑ SN54LV163A MIN MAX SN74LV163A MIN 5 5 5 CLR 3.5 3.5 3.5 Data (A, B, C, and D) 4.5 4.5 4.5 ENP, ENT 5 6 6 LOAD low 5 6 6 1 1 1 PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 8 MAX POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MAX UNIT ns ns ns SN54LV163A, SN74LV163A 4-BIT SYNCHRONOUS BINARY COUNTERS SCLS405F − APRIL 1998 − REVISED APRIL 2005 switching characteristics over recommended operating VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax TA = 25°C C CLK ENT CL = 15 pF 50* 115* 40* 40 CL = 50 pF 30 90 25 25 tpd RCO (preset mode) ENT MIN MAX MIN MAX UNIT MHz 8.5* 16.2* 1* 19.5* 1 19.5 9.1* 17* 1* 20.5* 1 20.5 12.1* 20.6* 1* 24.5* 1 24.5 8.7* 15.7* 1* 19* 1 19 11 19.2 1 22.5 1 22.5 11.9 20 1 23.5 1 23.5 14.6 23.6 1 27.5 1 27.5 11.7 18.7 1 22 1 22 CL = 15 pF ns RCO RCO (count mode) MAX range, SN74LV163A TYP Q C CLK SN54LV163A MIN RCO (count mode) RCO (preset mode) temperature LOAD CAPACITANCE Q tpd free-air CL = 50 pF ns RCO * On products compliant to MIL-PRF-38535, this parameter is not production tested. switching characteristics over recommended operating VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax C CLK tpd TA = 25°C tpd TYP CL = 15 pF 80* 160* 70* 70 CL = 50 pF 55 125 50 50 MAX MIN MAX MIN MAX UNIT MHz 12.8* 1* 15* 1 15 RCO (count mode) 6.8* 13.6* 1* 16* 1 16 8.8* 17.2* 1* 20* 1 20 6.5* 12.3* 1* 14.5* 1 14.5 8 16.3 1 18.5 1 18.5 8.8 17.1 1 19.5 1 19.5 10.7 20.7 1 23.5 1 23.5 8.2 15.8 1 18 1 18 CL = 15 pF ns RCO RCO (count mode) range, SN74LV163A MIN 6.2* RCO (preset mode) ENT SN54LV163A LOAD CAPACITANCE Q CLK C temperature Q RCO (preset mode) ENT free-air CL = 50 pF ns RCO * On products compliant to MIL-PRF-38535, this parameter is not production tested. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SN54LV163A, SN74LV163A 4-BIT SYNCHRONOUS BINARY COUNTERS SCLS405F − APRIL 1998 − REVISED APRIL 2005 switching characteristics over recommended operating VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax TA = 25°C C CLK CL = 15 pF 135* 210* 115* 115 CL = 50 pF 95 160 85 85 tpd MIN MAX MIN MAX 1* 9.5* 1 9.5 5.2* 8.1* 1* 9.5* 1 9.5 6.4* 10.3* 1* 12* 1 12 RCO 4.9* 8.1* 1* 9.5* 1 9.5 Q 6.1 10.1 1 11.5 1 11.5 6.6 10.1 1 11.5 1 11.5 7.8 12.3 1 14 1 14 6.3 10.1 1 11.5 1 11.5 RCO (preset mode) UNIT MHz 8.1* RCO (count mode) ENT MAX range, SN74LV163A TYP 4.7* RCO (preset mode) C CLK SN54LV163A MIN RCO (count mode) ENT temperature LOAD CAPACITANCE Q tpd free-air CL = 15 pF ns CL = 50 pF ns RCO * On products compliant to MIL-PRF-38535, this parameter is not production tested. noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25°C (see Note 6) SN74LV163A PARAMETER MIN TYP MAX UNIT VOL(P) Quiet output, maximum dynamic VOL 0.3 0.8 V VOL(V) Quiet output, minimum dynamic VOL −0.2 −0.8 V VOH(V) Quiet output, minimum dynamic VOH 3 VIH(D) High-level dynamic input voltage VIL(D) Low-level dynamic input voltage V 2.31 V 0.99 V UNIT NOTE 6: Characteristics are for surface-mount packages only. operating characteristics, TA = 25°C PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS CL = 50 pF, pF PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 f = 10 MHz VCC TYP 3.3 V 23.8 5V 26 pF SN54LV163A, SN74LV163A 4-BIT SYNCHRONOUS BINARY COUNTERS SCLS405F − APRIL 1998 − REVISED APRIL 2005 PARAMETER MEASUREMENT INFORMATION VCC Test Point From Output Under Test From Output Under Test RL = 1 kΩ S1 Open TEST GND LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain CL (see Note A) CL (see Note A) Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS VCC 50% VCC Timing Input 0V tw tsu VCC 50% VCC 50% VCC Input th VCC 50% VCC Data Input 50% VCC 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC 50% VCC Input 50% VCC tPLH In-Phase Output 50% VCC VOH 50% VCC VOL VOH 50% VCC VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 50% VCC 0V Output Waveform 1 S1 at VCC (see Note B) tPLZ ≈VCC 50% VCC tPZH tPLH 50% VCC 50% VCC tPZL tPHL tPHL Out-of-Phase Output 0V VCC Output Control Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ 50% VCC VOH − 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time, with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 PACKAGE OPTION ADDENDUM www.ti.com 13-Aug-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN74LV163AD ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV163A SN74LV163ADBR ACTIVE SSOP DB 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV163A SN74LV163ADGVR ACTIVE TVSOP DGV 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV163A SN74LV163ADR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV163A SN74LV163ANSR ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 74LV163A SN74LV163APW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV163A SN74LV163APWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV163A SN74LV163APWRG4 ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV163A SN74LV163APWT ACTIVE TSSOP PW 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV163A SN74LV163ARGYR ACTIVE VQFN RGY 16 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 LV163A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of