SN74LV165A-EP
PARALLEL-LOAD 8-BIT SHIFT REGISTER
www.ti.com
SCLS694 – JANUARY 2006
FEATURES
•
•
•
•
•
•
•
•
•
•
(1)
Controlled Baseline
– One Assembly/Test Site, One Fabrication
Site
Extended Temperature Performance of –55°C
to 125°C
Enhanced Diminishing Manufacturing
Sources (DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree (1)
2-V to 5.5-V VCC Operation
Max tpd of 10.5 ns at 5 V
Supports Mixed-Mode Voltage Operation on
All Ports
Ioff Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 250 mA Per
JESD 17
•
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
PW PACKAGE
(TOP VIEW)
SH/LD
CLK
E
F
G
H
QH
GND
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
CLK INH
D
C
B
A
SER
QH
Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
DESCRIPTION
The SN74LV165A-EP is a parallel-load, 8-bit shift register designed for 2-V to 5.5-V VCC operation.
When the device is clocked, data is shifted toward the serial output QH. Parallel-in access to each stage is
provided by eight individual direct data inputs that are enabled by a low level at the shift/load (SH/LD) input. The
SN74LV165A-EP features a clock-inhibit function and a complemented serial output, QH.
Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and clock
inhibit (CLK INH) is held low. The functions of CLK and CLK INH are interchangeable. Since a low CLK and a
low-to-high transition of CLK INH accomplishes clocking, CLK INH should be changed to the high level only while
CLK is high. Parallel loading is inhibited when SH/LD is held high. The parallel inputs to the register are enabled
while SH/LD is held low, independently of the levels of CLK, CLK INH, or SER.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the devices when they are powered down.
ORDERING INFORMATION
PACKAGE (1)
TA
–55°C to 125°C
(1)
TSSOP – PW
Reel of 2000
ORDERABLE PART NUMBER
SN74LV165AMPWREP
TOP-SIDE MARKING
LV165EP
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated
SN74LV165A-EP
PARALLEL-LOAD 8-BIT SHIFT REGISTER
www.ti.com
SCLS694 – JANUARY 2006
FUNCTION TABLE
INPUTS
SH/LD
CLK
CLK INH
OPERATION
L
X
X
Parallel load
H
H
X
Q0
H
X
H
Q0
H
L
↑
Shift
H
↑
L
Shift
LOGIC DIAGRAM (POSITIVE LOGIC)
A
SH/LD
CLK INH
CLK
SER
2
1
B
11
C
12
D
13
E
14
F
3
G
4
H
5
6
15
2
10
S
C1
1D
R
S
C1
1D
R
S
C1
1D
R
S
C1
1D
R
S
C1
1D
R
S
C1
1D
R
S
C1
1D
R
S
C1
1D
R
9
7
QH
QH
SN74LV165A-EP
PARALLEL-LOAD 8-BIT SHIFT REGISTER
www.ti.com
SCLS694 – JANUARY 2006
TYPICAL SHIFT, LOAD, AND INHIBIT SEQUENCES
CLK
CLK INH
SER
L
SH/LD
Data
Inputs
A
H
B
L
C
H
D
L
E
H
F
L
G
H
H
H
QH
H
H
L
H
L
H
L
H
QH
L
L
H
L
H
L
H
L
Inhibit
Serial Shift
Load
3
SN74LV165A-EP
PARALLEL-LOAD 8-BIT SHIFT REGISTER
www.ti.com
SCLS694 – JANUARY 2006
Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCC
Supply voltage range
–0.5
7
V
VI
Input voltage range (2)
–0.5
7
V
–0.5
7
V
–0.5
VCC + 0.5
state (2)
UNIT
VO
Voltage range applied to any output in the high-impedance or power-off
VO
Output voltage range (2) (3)
IIK
Input clamp current
VI < 0
–20
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
VO = 0 to VCC
±25
mA
±50
mA
108
°C/W
150
°C
Continuous current through VCC or GND
θJA
Package thermal
Tstg
Storage temperature range
(1)
(2)
(3)
(4)
impedance (4)
–65
V
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
This value is limited to 5.5 V maximum.
The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions (1)
VCC
Supply voltage
VCC = 2 V
VIH
High-level input voltage
MIN
MAX
2
5.5
UNIT
V
1.5
VCC = 2.3 V to 2.7 V
VCC × 0.7
VCC = 3 V to 3.6 V
VCC × 0.7
VCC = 4.5 V to 5.5 V
VCC × 0.7
VCC = 2 V
V
0.5
VCC = 2.3 V to 2.7 V
VCC × 0.3
VCC = 3 V to 3.6 V
VCC × 0.3
VIL
Low-level input voltage
VI
Input voltage
0
5.5
VO
Output voltage
0
VCC
V
–50
µA
VCC × 0.3
VCC = 4.5 V to 5.5 V
VCC = 2 V
IOH
High-level output current
VCC = 2.3 V to 2.7 V
–6
∆t/∆v
Input transition rise or fall rate
(1)
4
Operating free-air temperature
µA
50
VCC = 2.3 V to 2.7 V
2
VCC = 3 V to 3.6 V
6
VCC = 4.5 V to 5.5 V
12
VCC = 2.3 V to 2.7 V
200
VCC = 3 V to 3.6 V
100
VCC = 4.5 V to 5.5 V
TA
mA
–12
VCC = 2 V
Low-level output current
V
–2
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
IOL
V
mA
ns/V
20
–55
125
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
°C
SN74LV165A-EP
PARALLEL-LOAD 8-BIT SHIFT REGISTER
www.ti.com
SCLS694 – JANUARY 2006
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VOH
TEST CONDITIONS
MIN
2 V to 5.5 V
IOH = –2 mA
2.3 V
IOH = –6 mA
3V
2.48
4.5 V
3.8
IOH = –12 mA
VOL
VCC
IOH = –50 µA
TYP
MAX
2
V
IOL = 50 µA
2 V to 5.5 V
IOL = 2 mA
2.3 V
0.4
IOL = 6 mA
3V
0.44
IOL = 12 mA
4.5 V
0.55
II
VI = 5.5 V or GND
ICC
VI = VCC or GND,
Ioff
VI or VO = 0 to 5.5 V
Ci
VI = VCC or GND
IO = 0
UNIT
VCC – 0.1
0.1
V
0 to 5.5 V
±1
µA
5.5 V
20
µA
0
5
µA
3.3 V
1.7
pF
Timing Requirements
over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
tw
Pulse duration
Setup time
8.5
9
SH/LD low
11
13
SER before CLK↑
CLK INH before CLK↑
Data before SH/LD↑
SER data after CLK↑
th
Hold time
MIN
CLK high or low
SH/LD high before CLK↑
tsu
MAX
7
8.5
8.5
9.5
7
7
11.5
12
–1
0
Parallel data after SH/LD↑
0
0.5
SH/LD high after CLK↑
0
0
MAX
UNIT
ns
ns
ns
Timing Requirements
over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
tw
tsu
Pulse duration
Setup time
CLK high or low
6
7
9
SH/LD high before CLK↑
5
6
SER before CLK↑
5
6
CLK INH before CLK↑
5
5
7.5
8.5
SER data after CLK↑
Hold time
MIN
7.5
SH/LD low
Data before SH/LD↑
th
MAX
Parallel data after SH/LD↑
SH/LD high after CLK↑
0
0
0.5
0.5
0
0
MAX
UNIT
ns
ns
ns
5
SN74LV165A-EP
PARALLEL-LOAD 8-BIT SHIFT REGISTER
www.ti.com
SCLS694 – JANUARY 2006
Timing Requirements
over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
tw
Pulse duration
tsu
Setup time
CLK high or low
4
6.5
SH/LD low
5
6.5
SH/LD high before CLK↑
4
4
SER before CLK↑
4
4
3.5
4.5
CLK INH before CLK↑
Data before SH/LD↑
SER data after CLK↑
th
Hold time
MIN
MAX
Parallel data after SH/LD↑
SH/LD high after CLK↑
5
5
0.5
0.5
1
1
0.5
0.5
MAX
UNIT
ns
ns
ns
Switching Characteristics
over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
LOAD
CAPACITANCE
TA = 25°C
MIN
TYP
40
65
CL = 50 pF
CLK
tpd
SH/LD
QH or QH
CL = 50 pF
H
MIN
MAX
MAX
35
UNIT
MHz
15.3
23.3
1
26
16.1
25.1
1
28
15.9
25.3
1
28
ns
Switching Characteristics
over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
LOAD
CAPACITANCE
TA = 25°C
MIN
TYP
60
90
CL = 50 pF
CLK
tpd
SH/LD
QH or QH
CL = 50 pF
H
MIN
MAX
MAX
50
UNIT
MHz
10.9
14.9
1
16.9
11.3
19.3
1
22
11.1
17.6
1
20
ns
Switching Characteristics
over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
LOAD
CAPACITANCE
TA = 25°C
MIN
CL = 50 pF
75
CLK
tpd
SH/LD
QH or QH
CL = 50 pF
H
TYP
MIN
MAX
85
MAX
75
UNIT
MHz
7.7
11.9
1
13.5
7.7
11.9
1
13.5
7.6
11
1
12.5
ns
Operating Characteristics
TA = 25°C
PARAMETER
Cpd
6
Power dissipation capacitance
TEST CONDITIONS
CL = 50 pF,
f = 10 MHz
VCC
TYP
3.3 V
36.1
5V
37.5
UNIT
pF
SN74LV165A-EP
PARALLEL-LOAD 8-BIT SHIFT REGISTER
www.ti.com
SCLS694 – JANUARY 2006
PARAMETER MEASUREMENT INFORMATION
VCC
From Output
Under Test
Test
Point
RL = 1 kΩ
From Output
Under Test
CL
(see Note A)
S1
Open
TEST
GND
CL
(see Note A)
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
VCC
50% VCC
Timing Input
0V
tw
tsu
VCC
50% VCC
Input
50% VCC
th
VCC
50% VCC
Data Input
50% VCC
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
50% VCC
Input
50% VCC
tPLH
tPHL
50% VCC
tPHL
50% VCC
VOL
VOH
50% VCC
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
50% VCC
0V
tPLZ
≈VCC
Output
Waveform 1
S1 at VCC
(see Note B)
50% VCC
tPZH
tPLH
50% VCC
50% VCC
tPZL
VOH
In-Phase
Output
Out-of-Phase
Output
0V
VCC
Output
Control
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
50% VCC
VOH − 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time, with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPHL and tPLH are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuits and Voltage Waveforms
7
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN74LV165AMPWREP
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
LV165EP
V62/06603-01XE
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
LV165EP
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of