SN74LV74AMPWREP

SN74LV74A-EP DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS www.ti.com SCLS696 – JANUARY 2006 FEATURES • • • • • • • • • • • (1) Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of– 55°C to 125°C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree (1) 2-V to 5.5-V VCC Operation Max tpd of 13 ns at 5 V Typical VOLP (Output Ground Bounce) 2.3 V at VCC = 3.3 V, TA = 25°C Supports Mixed-Mode Voltage Operation on All Ports Ioff Supports Partial-Power-Down Mode Operation • • Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) PW PACKAGE (TOP VIEW) 1CLR 1D 1CLK 1PRE 1Q 1Q GND 1 14 VCC 2 13 2CLR 3 12 2D 4 11 2CLK 5 10 2PRE 6 7 9 2Q 8 2Q Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. DESCRIPTION/ORDERING INFORMATION These dual positive-edge-triggered D-type flip-flops are designed for 2-V to 5.5-V VCC operation. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. ORDERING INFORMATION PACKAGE (1) TA –55°C to 125°C (1) TSSOP – PW Reel of 2000 ORDERABLE PART NUMBER SN74LV74AMPWREP TOP-SIDE MARKING LV74AEP Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. UNLESS OTHERWISE NOTED this document contains ADVANCE INFORMATION on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. Copyright © 2006, Texas Instruments Incorporated SN74LV74A-EP DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS www.ti.com SCLS696 – JANUARY 2006 FUNCTION TABLE INPUTS (1) OUTPUTS PRE CLR CLK D Q L H X X H Q L H L X X L H L L X X H (1) H (1) H H ↑ H H L H H ↑ L L H H H L X Q0 Q0 This configuration is nonstable; that is, it does not persist when PRE or CLR returns to its inactive (high) level. LOGIC DIAGRAM, EACH FLIP-FLOP (POSITIVE LOGIC) PRE CLK C C C Q TG C C C C D TG TG TG C C C Q CLR 2 SN74LV74A-EP DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS www.ti.com SCLS696 – JANUARY 2006 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 7 V VI Input voltage range (2) –0.5 7 V –0.5 7 V –0.5 VCC + 0.5 state (2) UNIT VO Voltage range applied to any output in the high-impedance or power-off VO Output voltage range (2) (3) IIK Input clamp current VI < 0 –20 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current VO = 0 to VCC ±25 mA ±50 mA 113 °C/W 150 °C Continuous current through VCC or GND θJA Package thermal Tstg Storage temperature range (1) (2) (3) (4) impedance (4) –65 V Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. This value is limited to 5.5 V maximum. The package thermal impedance is calculated in accordance with JESD 51-7. 3 SN74LV74A-EP DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS www.ti.com SCLS696 – JANUARY 2006 Recommended Operating Conditions (1) VCC Supply voltage VCC = 2 V VIH High-level input voltage MIN MAX 2 5.5 Low-level input voltage VI Input voltage VO Output voltage VCC = 2.3 V to 2.7 V VCC × 0.7 VCC = 3 V to 3.6 V VCC × 0.7 VCC = 4.5 V to 5.5 V VCC × 0.7 V 0.5 VCC = 2.3 V to 2.7 V VCC × 0.3 VCC = 3 V to 3.6 V VCC × 0.3 0 5.5 0 VCC V –50 µA VCC = 2 V VCC = 2.3 V to 2.7 V High-level output current VCC = 3 V to 3.6 V –6 ∆t/∆v 2 VCC = 3 V to 3.6 V 6 VCC = 4.5 V to 5.5 V 12 VCC = 2.3 V to 2.7 V 200 VCC = 3 V to 3.6 V 100 VCC = 4.5 V to 5.5 V TA (1) µA 50 VCC = 2.3 V to 2.7 V Input transition rise or fall rate mA –12 VCC = 2 V Low-level output current V –2 VCC = 4.5 V to 5.5 V IOL V VCC × 0.3 VCC = 4.5 V to 5.5 V IOH V 1.5 VCC = 2 V VIL UNIT mA ns/V 20 Operating free-air temperature –55 °C 125 All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH TEST CONDITIONS IOH = –2 mA 2.3 V IOH = –6 mA 3V 2.48 4.5 V 3.8 4 MAX 2 IOL = 2 mA 2.3 V 0.4 IOL = 6 mA 3V 0.44 4.5 V 0.55 VI = 5.5 V or GND VI = VCC or GND, IO = 0 Ioff VI or VO = 0 to 5.5 V VI = VCC or GND UNIT V 2 V to 5.5 V ICC Ci TYP VCC – 0.1 IOL = 50 µA IOL = 12 mA II MIN 2 V to 5.5 V IOH = –12 mA VOL VCC IOH = –50 µA 0.1 V 0 to 5.5 V ±1 µA 5.5 V 20 µA 0 5 µA 3.3 V 2 5V 2 pF SN74LV74A-EP DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS www.ti.com SCLS696 – JANUARY 2006 Timing Requirements over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) TA = 25°C PARAMETER tw Pulse duration tsu Setup time before CLK↑ th Hold time, data after CLK↑ MIN MAX MIN PRE or CLR low 8 9 CLK 8 9 Data 8 9 PRE or CLR inactive 7 7 0.5 0.5 MAX UNIT ns ns ns Timing Requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) TA = 25°C PARAMETER tw Pulse duration tsu Setup time before CLK↑ th Hold time, data after CLK↑ MIN MAX MIN PRE or CLR low 6 7 CLK 6 7 Data 6 7 PRE or CLR inactive 5 5 1.45 2.15 MAX UNIT ns ns ns Timing Requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) TA = 25°C PARAMETER tw Pulse duration tsu Setup time before CLK↑ th Hold time, data after CLK↑ MIN MAX MIN PRE or CLR low 5 5 CLK 5 5 Data 5 5 PRE or CLR inactive 3 3 1.45 2.15 MAX UNIT ns ns ns Switching Characteristics over recommended operating free-air temperature range,VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax tpd LOAD CAPACITANCE CL = 50 pF PRE or CLR CLK Q or Q CL = 50 pF TA = 25°C MIN TYP 30 70 MAX MIN MAX 25 UNIT MHz 13 17.4 1 20 14.2 20 1 23 ns 5 SN74LV74A-EP DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS www.ti.com SCLS696 – JANUARY 2006 Switching Characteristics over recommended operating free-air temperature range,VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE fmax tpd CL = 50 pF PRE or CLR Q or Q CLK TA = 25°C MIN TYP 50 90 CL = 50 pF MIN MAX MAX UNIT 45 MHz 9.2 15.8 1 18 10.2 15.4 1 18 ns Switching Characteristics over recommended operating free-air temperature range,VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE fmax tpd CL = 50 pF PRE or CLR CLK Q or Q CL = 50 pF TA = 25°C MIN TYP 90 140 MIN MAX MAX UNIT 75 MHz 6.6 9.7 1 12 7.2 9.9 1 13 ns Noise Characteristics (1) VCC = 3.3 V, CL = 50 pF, TA = 25°C PARAMETER TYP MAX 0.1 0.8 V Quiet output, minimum dynamic VOL 0 –0.8 V Quiet output, minimum dynamic VOH 3.2 VOL(P) Quiet output, maximum dynamic VOL VOL(V) VOH(V) VIH(D) High-level dynamic input voltage VIL(D) Low-level dynamic input voltage (1) MIN UNIT V 2.31 V 0.99 V Characteristics are for surface-mount packages only. Operating Characteristics TA = 25°C PARAMETER Cpd 6 Power dissipation capacitance TEST CONDITIONS CL = 50 pF, f = 10 MHz VCC TYP 3.3 V 21 5V 23 UNIT pF SN74LV74A-EP DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS www.ti.com SCLS696 – JANUARY 2006 PARAMETER MEASUREMENT INFORMATION VCC From Output Under Test Test Point RL = 1 kΩ From Output Under Test CL (see Note A) S1 Open TEST GND CL (see Note A) LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS VCC 50% VCC Timing Input 0V tw tsu VCC 50% VCC Input 50% VCC th VCC 50% VCC Data Input 50% VCC 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC 50% VCC Input 50% VCC tPLH tPHL 50% VCC tPHL 50% VCC VOL 50% VCC VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS tPLZ ≈VCC 50% VCC tPZH VOH 50% VCC 0V Output Waveform 1 S1 at VCC (see Note B) tPLH 50% VCC 50% VCC tPZL VOH In-Phase Output Out-of-Phase Output 0V VCC Output Control Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ 50% VCC VOH − 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time, with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuits and Voltage Waveforms 7 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN74LV74AMPWREP ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 LV74AEP V62/06605-01XE ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 LV74AEP (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of