SN74LV373AIPWRQ1

SN74LV373A-Q1 OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCLS586C – JUNE 2004 – REVISED OCTOBER 2007 FEATURES 1 • • • • • • • • PW PACKAGE (TOP VIEW) Qualified for Automotive Applications 2-V to 5.5-V VCC Operation Maximum tpd of 8.5 ns at 5 V Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) > 2.3 V at VCC = 3.3 V, TA = 25°C Supports Mixed-Mode Voltage Operation on All Ports Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 250 mA Per JESD 17 OE 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q LE DESCRIPTION/ORDERING INFORMATION The SN74LV373A device is an octal transparent D-type latch designed for 2-V to 5.5-V VCC operation. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE shall be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION (1) PACKAGE (2) TA –40°C to 85°C (1) (2) TSSOP – PW Reel of 2000 ORDERABLE PART NUMBER SN74LV373AIPWRQ1 TOP-SIDE MARKING LV373AI For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004–2007, Texas Instruments Incorporated SN74LV373A-Q1 OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCLS586C – JUNE 2004 – REVISED OCTOBER 2007 FUNCTION TABLE (EACH LATCH) INPUTS OUTPUT OE LE D Q L H H H L H L L L L X Q0 H X X Z LOGIC DIAGRAM (POSITIVE LOGIC) OE LE 1 11 C1 1D 3 2 1Q 1D To Seven Other Channels Absolute Maximum Ratings (1) over operating free-air temperature (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 7 V VI Input voltage range (2) –0.5 7 V –0.5 7 V –0.5 VCC + 0.5 (2) UNIT VO Voltage range applied to any output in the high-impedance or power-off state VO Output voltage range (2) (3) IIK Input clamp current VI < 0 –20 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current VO = 0 to VCC ±35 mA Continuous current through VCC or GND θJA Package thermal impedance (4) Tstg Storage temperature range (1) (2) (3) (4) 2 –65 V ±70 mA 83 °C/W 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. This value is limited to 5.5 V maximum. The package thermal impedance is calculated in accordance with JESD 51-7. Submit Documentation Feedback Copyright © 2004–2007, Texas Instruments Incorporated SN74LV373A-Q1 OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCLS586C – JUNE 2004 – REVISED OCTOBER 2007 Recommended Operating Conditions (1) VCC MIN MAX 2 5.5 Supply voltage VCC = 2 V VIH High-level input voltage Low-level input voltage VI Input voltage VO Output voltage VCC = 2.3 V to 2.7 V VCC × 0.7 VCC = 3 V to 3.6 V VCC × 0.7 VCC = 4.5 V to 5.5 V VCC × 0.7 V 0.5 VCC = 2.3 V to 2.7 V VCC × 0.3 VCC = 3 V to 3.6 V VCC × 0.3 0 5.5 High or low state 0 VCC 3-state 0 5.5 VCC = 2 V –50 VCC = 2.3 V to 2.7 V High-level output current Δt/Δv –8 50 VCC = 2.3 V to 2.7 V 8 VCC = 4.5 V to 5.5 V 16 VCC = 2.3 V to 2.7 V 200 VCC = 3 V to 3.6 V 100 VCC = 4.5 V to 5.5 V TA (1) µA mA µA 2 VCC = 3 V to 3.6 V Input transition rise or fall rate V –16 VCC = 2 V Low-level output current V –2 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V IOL V VCC × 0.3 VCC = 4.5 V to 5.5 V IOH V 1.5 VCC = 2 V VIL UNIT mA ns/V 20 Operating free-air temperature –40 85 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL TEST CONDITIONS VCC MIN IOH = –50 µA 2 V to 5.5 V IOH = –2 mA 2.3 V IOH = –8 mA 3V 2.48 IOH = –16 mA 4.5 V 3.8 TYP MAX UNIT VCC – 0.1 2 V IOL = 50 µA 2 V to 5.5 V IOL = 2 mA 2.3 V 0.4 IOL = 8 mA 3V 0.44 IOL = 16 mA 4.5 V 0.55 0.1 V II VI = 5.5 V or GND 0 to 5.5 V ±1 µA IOZ VO = VCC or GND 5.5 V ±5 µA ICC VI = VCC or GND, IO = 0 5.5 V 20 µA Ioff VI or VO = 0 to 5.5 V 5 µA Ci VI = VCC or GND Copyright © 2004–2007, Texas Instruments Incorporated 0 3.3 V 2.9 Submit Documentation Feedback pF 3 SN74LV373A-Q1 OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCLS586C – JUNE 2004 – REVISED OCTOBER 2007 Timing Requirements over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) MIN tw Pulse duration, LE high tsu Setup time, data before LE↓ th Hold time, data after LE↓ MAX UNIT 6.5 ns High or low 5 ns High or low 1.5 ns Timing Requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) MIN tw Pulse duration, LE high tsu Setup time, data before LE↓ th Hold time, data after LE↓ MAX UNIT 5 ns High or low 4 ns High or low 1 ns Timing Requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) MIN MAX UNIT tw Pulse duration, LE high 5 ns tsu Setup time, data before LE↓ High or low 4 ns th Hold time, data after LE↓ High or low 1 ns Switching Characteristics over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE MIN MAX UNIT D Q 1 17 LE Q 1 19 ten OE Q 1 19 ns tdis OE Q 1 15 ns D Q 1 21 LE Q 1 22 ten OE Q 1 22 ns tdis OE Q 1 19 ns 2 ns tpd tpd tsk(o) CL = 15 pF CL = 50 pF CL = 50 pF ns ns Switching Characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) MIN MAX UNIT D Q 1 13.5 LE Q 1 13 ten OE Q 1 13.5 ns tdis OE Q 1 12 ns D Q 1 17 LE Q 1 16.5 ten OE Q 1 17 ns tdis OE Q 1 15 ns 1.5 ns tpd tpd tsk(o) 4 LOAD CAPACITANCE Submit Documentation Feedback CL = 15 pF CL = 50 pF CL = 50 pF ns ns Copyright © 2004–2007, Texas Instruments Incorporated SN74LV373A-Q1 OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCLS586C – JUNE 2004 – REVISED OCTOBER 2007 Switching Characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) D Q LE Q ten OE Q tdis OE Q PARAMETER tpd LOAD CAPACITANCE MIN MAX 1 8.5 1 8.5 1 9.5 ns 1 8.5 ns CL = 15 pF UNIT ns D Q 1 10.5 LE Q 1 10.5 ten OE Q 1 11.5 ns tdis OE Q 1 10.5 ns 1 ns tpd tsk(o) CL = 50 pF CL = 50 pF ns Noise Characteristics (1) VCC = 3.3 V, CL = 50 pF, TA = 25°C (unless otherwise noted) TYP MAX VOL(P) Quiet output, maximum dynamic VOL MIN 0.6 0.8 V VOL(V) Quiet output, minimum dynamic VOL –0.6 –0.8 V VOH(V) Quiet output, minimum dynamic VOH 2.9 VIH(D) High-level dynamic input voltage VIL(D) Low-level dynamic input voltage (1) UNIT V 2.31 V 0.99 V Characteristics are for surface-mount packages only. Operating Characteristics TA = 25°C PARAMETER Cpd Power dissipation capacitance (outputs enabled) Copyright © 2004–2007, Texas Instruments Incorporated TEST CONDITIONS CL = 50 pF, f = 10 MHz VCC TYP 3.3 V 17.4 5V 19.5 Submit Documentation Feedback UNIT pF 5 SN74LV373A-Q1 OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCLS586C – JUNE 2004 – REVISED OCTOBER 2007 PARAMETER MEASUREMENT INFORMATION VCC From Output Under Test Test Point RL = 1 kΩ From Output Under Test CL (see Note A) S1 Open TEST GND CL (see Note A) LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS S1 Open VCC GND VCC tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS VCC 50% VCC Timing Input tw tsu VCC 50% VCC Input 50% VCC 0V th VCC 50% VCC Data Input 50% VCC 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC 50% VCC Input 50% VCC 0V tPLH In-Phase Output tPHL 50% VCC tPHL Out-of-Phase Output VOH 50% VCC VOL Output Waveform 1 S1 at VCC (see Note B) VOH 50% VCC VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 50% VCC 50% VCC 0V tPLZ tPZL ≈VCC 50% VCC tPZH tPLH 50% VCC VCC Output Control Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ 50% VCC VOH - 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics:PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time, with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 6 Submit Documentation Feedback Copyright © 2004–2007, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN74LV373AIPWRG4Q1 ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV373AI SN74LV373AIPWRQ1 ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 LV373AI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of