SN74LV595A-Q1
SCLS539F – AUGUST 2003 – REVISED NOVEMBER 2022
SN74LV595A-Q1 8-Bit Shift Registers With 3-State Output Registers
1 Features
3 Description
•
•
•
The SN74LV595A-Q1 contains an 8-bit serial-in,
parallel-out shift register that feeds an 8-bit D-type
storage register. The storage register has parallel 3state outputs. Separate clocks are provided for both
the shift and storage register. The shift register has
a direct overriding clear (SRCLR) input, serial (SER)
input, and a serial output for cascading. When the
output-enable (OE) input is high, all outputs except
QH' are in the high-impedance state.
•
•
•
•
•
•
•
Qualified for automotive applications
Available in wettable flank QFN (WBQB) package
Customer-specific configuration control can be
supported along with major-change approval
2-V to 5.5-V VCC operation
Typical VOLP (output ground bounce) < 0.8 V at
VCC = 3.3 V, TA = 25°C
Typical VOHV (output VOH undershoot) > 2.3 V at
VCC = 3.3 V, TA = 25°C
Supports mixed-mode voltage operation on all
ports
8-bit serial-in, parallel-out shift
Ioff supports partial-power-down mode operation
Shift register has direct clear
The device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables
the outputs, preventing damaging current backflow
through the device when it is powered down.
Package Information(1)
2 Applications
•
•
•
PART NUMBER
Output expansion
LED matrix control
7-segment display control
SN74LV595A-Q1
(1)
OE
RCLK
SRCLR
SRCLK
SER
PACKAGE
BODY SIZE (NOM)
PW (TSSOP, 16)
5.00 mm × 4.40 mm
WBQB (WQFN, 16)
3.60 mm × 2.60 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
13
12
10
11
14
D
Q
D
Q
15
QA
R
D
Q
D
Q
1
QB
R
2
QC
3
QD
4
QE
5
QF
6
QG
D
Q
D
Q
7
QH
R
9
QH’
Logic Diagram (Positive Logic)
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LV595A-Q1
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SCLS539F – AUGUST 2003 – REVISED NOVEMBER 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................6
6.6 Timing Requirements, VCC = 2.5 V ± 0.2 V.................6
6.7 Timing Requirements, VCC = 3.3 V ± 0.3 V.................7
6.8 Timing Requirements, VCC = 5 V ± 0.5 V....................7
6.9 Switching Characteristics, VCC = 2.5 V ± 0.2 V...........8
6.10 Switching Characteristics, VCC = 3.3 V ± 0.3 V.........9
6.11 Switching Characteristics, VCC = 5 V ± 0.5 V............ 9
6.12 Noise Characteristics................................................ 9
6.13 Operating Characteristics......................................... 9
6.14 Typical Characteristics............................................ 10
7 Parameter Measurement Information.......................... 11
8 Detailed Description......................................................12
8.1 Overview................................................................... 12
8.2 Functional Block Diagram......................................... 12
8.3 Feature Description...................................................13
8.4 Device Functional Modes..........................................15
9 Application and Implementation.................................. 16
9.1 Application Information............................................. 16
9.2 Typical Application.................................................... 16
10 Power Supply Recommendations..............................19
11 Layout........................................................................... 19
11.1 Layout Guidelines................................................... 19
11.2 Layout Example...................................................... 19
12 Device and Documentation Support..........................20
12.1 Documentation Support.......................................... 20
12.2 Receiving Notification of Documentation Updates..20
12.3 Support Resources................................................. 20
12.4 Trademarks............................................................. 20
12.5 Electrostatic Discharge Caution..............................20
12.6 Glossary..................................................................20
13 Mechanical, Packaging, and Orderable
Information.................................................................... 20
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (June 2022) to Revision F (November 2022)
Page
• Changed the status of the data sheet from: Advanced Information to: Production Data ...................................1
2
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SCLS539F – AUGUST 2003 – REVISED NOVEMBER 2022
5 Pin Configuration and Functions
QB
VCC
1
16
QB
1
16
VCC
QC
2
QA
QC
2
15
QA
QD
QE
3
15
14
QD
3
13
QE
4
14
13
SER
4
SER
OE
QF
5
12
RCLK
QF
5
QG
QH
6
11
SRCLK
QG
6
11
SRCLK
7
8
10
SRCLR
QH¶
QH
7
10
SRCLR
GND
9
PAD
8
12
OE
RCLK
9
GND QH`
Figure 5-1. PW Package,
16-Pin TSSOP
(Top View)
Figure 5-2. WBQB Package,
16-Pin WQFN
Transparent (Top View)
Table 5-1. Pin Functions
PIN
NAME
NO.
GND
8
OE
QA
TYPE(1)
DESCRIPTION
G
Ground
13
I
Output Enable Pin
15
O
QA Output
QB
1
O
QB Output
QC
2
O
QC Output
QD
3
O
QD Output
QE
4
O
QE Output
QF
5
O
QF Output
QG
6
O
QG Output
QH
7
O
QH Output
QH'
9
O
QH' Output
SRCLR
10
I
SRCLR Input
SRCLK
11
I
SRCLK Input
RCLK
12
I
RCLK Input
SER
14
I
SER Input
VCC
16
P
Positive Supply
PAD
—
—
Thermal Pad(2)
(1)
(2)
I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power.
WBQB Package Only
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
VCC
VI
MIN
MAX
Supply voltage range
–0.5
7.0
V
range(2)
–0.5
7.0
V
–0.5
4.6
V
–0.5
VCC + 0.5
Input voltage
Voltage range applied to any output in the high-impedance or power-off state(2)
VO
Output voltage range applied to any output in the high or low
IIK
Input clamp current(2)
VI < 0
IOK
Output clamp current(2)
VO < 0
IO
Continuous output current
state(2) (3)
UNIT
V
–20
mA
-50
mA
±35
mA
Continuous current through VCC or GND
±70
mA
TJ
Junction temperature
150
°C
Tstg
Storage temperature
150
°C
(1)
(2)
(3)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The package thermal impedance is calculated in accordance with JESD 51-7.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per AEC Q100-002 HBM ESD Classification Level 2(1)
V(ESD)
(1)
4
Electrostatic
discharge
UNIT
±2000
Machine Model (MM), per JEDEC specification
±200
Charged-device model (CDM), per AEC Q100-011 CDM ESD Classification Level C4B
±1000
V
AEC Q100-002 indicate that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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6.3 Recommended Operating Conditions
VCC
Supply voltage
VCC = 2 V
VIH
High-level input voltage
MIN
MAX
2
5.5
Low-level input voltage
VI
Input voltage(1)
VO
Output voltage
VCC = 2.3 V to 2.7 V
VCC × 0.7
VCC = 3 V to 3.6 V
VCC × 0.7
VCC = 4.5 V to 5.5 V
VCC × 0.7
VCC = 2.3 V to 2.7 V
VCC × 0.3
VCC = 3 V to 3.6 V
VCC × 0.3
5.5
High or low state
0
VCC
3-state
0
5.5
–50
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
Δt/Δv
–8
50
VCC = 2.3 V to 2.7 V
8
VCC = 4.5 V to 5.5 V
16
VCC = 2.3 V to 2.7 V
200
VCC = 3 V to 3.6 V
100
VCC = 4.5 V to 5.5 V
TA
(1)
Operating free-air temperature
µA
mA
µA
2
VCC = 3 V to 3.6 V
Input transition rise/fall time
V
–16
VCC = 2 V
Low level output current
V
–2
VCC = 4.5 V to 5.5 V
IOL
V
VCC × 0.3
0
VCC = 2 V
High level output current
V
0.5
VCC = 4.5 V to 5.5 V
IOH
V
1.5
VCC = 2 V
VIL
UNIT
mA
ns/V
20
SN74LV595AIPWRQ1
–40
85
SN74LV595AQPWRQ1
or SN74LV595AQWBQRQ1
–40
125
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report,
Implications of Slow or Floating CMOS Inputs.
6.4 Thermal Information
SN74LV595A-Q1
THERMAL
METRIC(1)
PW (TSSOP)
WBQB (WQFN)
16 PINS
16 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
108
86
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
40.8
82.6
°C/W
RθJB
Junction-to-board thermal resistance
51.1
54.9
°C/W
ΨJT
Junction-to-top characterization parameter
3.8
9.5
°C/W
ΨJB
Junction-to-board characterization parameter
50.6
54.9
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
32.5
°C/W
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VOH
VOL
TEST CONDITIONS
VCC
IOH = –50 µA
2 V to 5.5 V
IOH = –2 mA
2.3 V
QH’
IOH = –6 mA
QA –QH
IOH = –8 mA
QH’
IOH = –12 mA
QA–QH
IOH = –16 mA
3V
4.5 V
IOL = 50 µA
2 V to 5.5 V
IOL = 2 mA
2.3 V
QH’
IOL = 6 mA
QA−QH
IOL = 8 mA
QH’
IOL = 12 mA
QA−QH
IOL = 16 mA
II
VI = 5.5 V or GND
IOZ
QA – QH
ICC
VI = VCC or GND, IO = 0
Ioff
VI or VO = 0 to 5.5 V
Ci
VI = VCC or GND
–40°C to 85°C
MIN
TYP
–40°C to 125°C
MAX
MIN
VCC – 0.1
VCC – 0.1
2
2
2.48
2.45
2.48
2.45
3.8
3.7
3.8
TYP
MAX
UNIT
V
3.7
3V
4.5 V
0.1
0.1
0.4
0.45
0.44
0.5
0.44
0.5
0.55
0.65
0.55
0.65
V
0 to 5.5 V
±1
±1
µA
5.5 V
±5
±10
µA
5.5 V
20
40
µA
10
µA
VO = VCC or GND,
0V
5
3.3 V
3.5
3.5
pF
6.6 Timing Requirements, VCC = 2.5 V ± 0.2 V
over operating free-air temperature range (unless otherwise noted)
TA = 25°C
MIN
tw
Pulse duration
Setup time
(1)
6
Hold time
MAX
MIN
7
7.5
8.5
RCLK high or low
7
7.5
8.5
SRCLR low
6
6.5
7.5
5.5
5.5
6.5
8
9
10
8.5
9.5
10.5
4
4
5
1.5
1.5
2.5
SRCLK↑ before RCLK↑(1)
SRCLR low before RCLK↑
SRCLR high (inactive) before SRCLK↑
th
MIN
TA = −40°C
TO 125°C
SRCLK high or low
SER before SRCLK↑
tsu
MAX
TA = −40°C
TO 85°C
SER after SRCLK↑
UNIT
MAX
ns
ns
ns
This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case
the shift register is one clock pulse ahead of the storage register.
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6.7 Timing Requirements, VCC = 3.3 V ± 0.3 V
over operating free-air temperature range (unless otherwise noted)
TA = 25°C
MIN
tw
Pulse duration
th
(1)
Hold time
MAX
MIN
5.5
5.5
6.5
RCLK high or low
5.5
5.5
6.5
5
5
6
SER before SRCLK↑
Setup time
MIN
TA = −40°C
TO 125°C
SRCLK high or low
SRCLR low
tsu
MAX
TA = −40°C
TO 85°C
3.5
3.5
4.5
SRCLK↑ before RCLK↑(1)
8
8.5
9.5
SRCLR low before RCLK↑
8
9
10
SRCLR high (inactive) before SRCLK↑
3
3
4
1.5
1.5
2.5
SER after SRCLK↑
UNIT
MAX
ns
ns
ns
This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case
the shift register is one clock pulse ahead of the storage register.
6.8 Timing Requirements, VCC = 5 V ± 0.5 V
over operating free-air temperature range (unless otherwise noted)
TA = 25°C
MIN
tw
Pulse duration
th
Hold time
MIN
5
5
6
5
5
6
5.2
5.2
6.2
3
3
4
5
5
6
5
5
6
2.5
2.5
3.5
2
2
3
SRCLK↑ before
RCLK↑(1)
SRCLR low before RCLK↑
SRCLR high (inactive) before SRCLK↑
(1)
MAX
RCLK high or low
SER before SRCLK↑
Setup time
MIN
TA = −40°C
TO 125°C
SRCLK high or low
SRCLR low
tsu
MAX
TA = −40°C
TO 85°C
SER after SRCLK↑
UNIT
MAX
ns
ns
ns
This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case
the shift register is one clock pulse ahead of the storage register.
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SRCLK
SER
RCLK
SRCLR
OE
QA
QB
QC
QD
QE
QF
QG
QH
QH′
NOTE:
Copyright © 2016, Texas Instruments Incorporated
implies that the output is in 3-State mode.
Figure 6-1. Timing Diagram
6.9 Switching Characteristics, VCC = 2.5 V ± 0.2 V
over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
tPLH
tPHL
tPLH
tPHL
tPHL
tPZH
tPZL
tPHZ
tPLZ
8
RCLK
QA−QH
SRCLK
QH'
SRCLR
QH'
OE
OE
QA−QH
QA−QH
TA = −40°C
TO 85°C
TA = 25°C
MIN
TYP
60
70
MAX
MIN
MAX
40
TA = −40°C
TO 125°C
MIN
UNIT
MAX
30
MHz
11.2
17.2
1
19.3
1
22.3
ns
11.2
17.2
1
19.3
1
22.3
ns
13.1
22.5
1
25.5
1
28.5
ns
13.1
22.5
1
25.5
1
28.5
ns
12.4
18.8
1
21.1
1
24.1
ns
10.8
17
1
18.3
1
21.3
ns
13.4
21
1
23
1
26
ns
12.2
18.3
1
19.5
1
22.5
ns
14
20.9
1
22.6
1
25.6
ns
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6.10 Switching Characteristics, VCC = 3.3 V ± 0.3 V
over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
tPLH
tPHL
tPLH
tPHL
tPHL
tPZH
RCLK
QA−QH
SRCLK
QH'
SRCLR
QH'
OE
tPZL
tPHZ
tPLZ
MIN
TYP
55
105
QA−QH
OE
TA = −40°C
TO 85°C
TA = 25°C
QA−QH
MAX
MIN
TA = −40°C
TO 125°C
MAX
MIN
50
UNIT
MAX
40
MHz
7.9
15.4
1
17
1
20
ns
7.9
15.4
1
17
1
20
ns
9.2
16.5
1
18.5
1
21.5
ns
9.2
16.5
1
18.5
1
21.5
ns
9
16.3
1
17.2
1
20.2
ns
7.8
15
1
17
1
20
ns
9.6
15
1
17
1
20
ns
8.1
15.7
1
16.2
1
19.2
ns
9.3
15.7
1
16.2
1
19.2
ns
6.11 Switching Characteristics, VCC = 5 V ± 0.5 V
over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
tPLH
tPHL
tPLH
tPHL
tPHL
tPZH
tPZL
tPHZ
tPLZ
RCLK
QA−QH
SRCLK
QH'
SRCLR
QH'
OE
QA−QH
OE
QA−QH
TA = −40°C
TO 85°C
TA = 25°C
MIN
TYP
95
140
MAX
MIN
TA = −40°C
TO 125°C
MAX
85
MIN
UNIT
MAX
75
MHz
5.6
9.4
1
10.5
1
13.5
ns
5.6
9.4
1
10.5
1
13.5
ns
6.4
10.2
1
11.4
1
14.4
ns
6.4
10.2
1
11.4
1
14.4
ns
6.4
10
1
11.1
1
14.1
ns
5.7
10.6
1
12
1
15
ns
6.8
10.6
1
12
1
15
ns
3.5
10.3
1
11
1
14
ns
3.4
10.3
1
11
1
14
ns
MIN
TYP
MAX
6.12 Noise Characteristics
VCC = 3.3 V, CL = 50 pF, TA = 25°C(1)
PARAMETER
UNIT
VOL(P)
Quiet output, maximum dynamic VOL
0.3
V
VOL(V)
Quiet output, minimum dynamic VOL
–0.2
V
VOH(V)
Quiet output, minimum dynamic VOH
2.8
V
VIH(D)
High-level dynamic input voltage
VIL(D)
Low-level dynamic input voltage
(1)
2.31
V
0.99
V
TYP
UNIT
Characteristics are for surface-mount packages only.
6.13 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
CL = 50 pF, f = 10 MHz
VCC = 3.3 V
111
VCC = 5 V
114
pF
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6.14 Typical Characteristics
13
CL=50pF
12
tPD (ns)
11
10
9
8
7
6
2.5
3
3.5
4
4.5
VCC (V)
5
C001
Figure 6-2. TPD vs VCC
10
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7 Parameter Measurement Information
VCC
Test
Point
From Output
Under Test
RL = 1 kΩ
From Output
Under Test
S1
Open
TEST
GND
CL
(see Note A)
CL
(see Note A)
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
VCC
50% VCC
Timing Input
0V
tw
tsu
VCC
50% VCC
50% VCC
Input
th
VCC
50% VCC
Data Input
50% VCC
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
50% VCC
Input
50% VCC
tPLH
tPHL
50% VCC
tPHL
50% VCC
VOL
VOH
50% VCC
VOL
tPLZ
≈VCC
50% VCC
tPZH
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
50% VCC
0V
Output
Waveform 1
S1 at VCC
(see Note B)
tPLH
50% VCC
50% VCC
tPZL
VOH
In-Phase
Output
Out-of-Phase
Output
0V
VCC
Output
Control
VOL + 0.3 V
VOL
tPHZ
50% VCC
VOH
0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time, with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. t PZL and tPZH are the same as ten.
G. tPHL and tPLH are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 7-1. Load Circuit and Voltage Waveforms
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8 Detailed Description
8.1 Overview
The SN74LV595A-Q1 contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage
register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift
and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and
a serial output for cascading. When the output-enable (OE) input is high, all outputs except QH' are in the
high-impedance state.
Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both
clocks are connected together, the shift register always is one clock pulse ahead of the storage register.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
8.2 Functional Block Diagram
OE
RCLK
SRCLR
SRCLK
SER
13
12
10
11
14
D
Q
D
Q
15
QA
R
D
Q
D
Q
1
QB
R
2
QC
3
QD
4
QE
5
QF
6
QG
D
Q
D
Q
7
QH
R
9
QH’
Figure 8-1. Logic Diagram (Positive Logic)
12
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8.3 Feature Description
8.3.1 Balanced CMOS 3-State Outputs
This device includes balanced CMOS 3-state outputs. Driving high, driving low, and high impedance are the
three states that these outputs can be in. The term balanced indicates that the device can sink and source
similar currents. The drive capability of this device may create fast edges into light loads, so routing and load
conditions should be considered to prevent ringing. Additionally, the outputs of this device can drive larger
currents than the device can sustain without being damaged. It is important for the output power of the device
to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the Absolute
Maximum Ratings must be followed at all times.
When placed into the high-impedance mode, the output will neither source nor sink current, with the exception of
minor leakage current as defined in the Electrical Characteristics table. In the high-impedance state, the output
voltage is not controlled by the device and is dependent on external factors. If no other drivers are connected
to the node, then this is known as a floating node and the voltage is unknown. A pull-up or pull-down resistor
can be connected to the output to provide a known voltage at the output while it is in the high-impedance state.
The value of the resistor will depend on multiple factors, including parasitic capacitance and power consumption
limitations. Typically, a 10-kΩ resistor can be used to meet these requirements.
Unused 3-state CMOS outputs should be left disconnected.
8.3.2 Balanced CMOS Push-Pull Outputs
This device includes balanced CMOS push-pull outputs. The term balanced indicates that the device can sink
and source similar currents. The drive capability of this device may create fast edges into light loads, so routing
and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable
of driving larger currents than the device can sustain without being damaged. It is important for the output power
of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the
Absolute Maximum Ratings must be followed at all times.
Unused push-pull CMOS outputs should be left disconnected.
8.3.3 Latching Logic
This device includes latching logic circuitry. Latching circuits commonly include D-type latches and D-type
flip-flops, but include all logic circuits that act as volatile memory.
When the device is powered on, the state of each latch is unknown. There is no default state for each latch at
start-up.
The output state of each latching logic circuit only remains stable as long as power is applied to the device within
the supply voltage range specified in the Recommended Operating Conditions table.
8.3.4 Partial Power Down (Ioff)
This device includes circuitry to disable all outputs when the supply pin is held at 0 V. When disabled, the
outputs will neither source nor sink current, regardless of the input voltages applied. The amount of leakage
current at each output is defined by the Ioff specification in the Electrical Characteristics table.
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8.3.5 Wettable Flanks
This device includes wettable flanks for at least one package. See the Features section on the front page of the
data sheet for which packages include this feature.
Package
Package
Solder
Weable Flank Lead
Standard Lead
Pad
PCB
Figure 8-2. Simplified Cutaway View of Wettable-Flank QFN Package and Standard QFN Package After
Soldering
Wettable flanks help improve side wetting after soldering, which makes QFN packages easier to inspect with
automatic optical inspection (AOI). As shown in Figure 8-2, a wettable flank can be dimpled or step-cut to
provide additional surface area for solder adhesion which assists in reliably creating a side fillet. Please see the
mechanical drawing for additional details.
8.3.6 Clamp Diode Structure
Figure 8-3 shows the inputs and outputs to this device have negative clamping diodes only.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage
to the device. The input and output voltage ratings may be exceeded if the input and output clampcurrent ratings are observed.
Device
VCC
Logic
Input
-IIK
Output
-IOK
GND
Figure 8-3. Electrical Placement of Clamping Diodes for Each Input and Output
14
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8.4 Device Functional Modes
Table 8-1. Function Table
INPUTS(1)
(1)
FUNCTION
SER
SRCLK
SRCLR
RCLK
OE
X
X
X
X
H
Outputs QA−QH are disabled.
QH' remains enabled.
X
X
X
X
L
Outputs QA−QH are enabled.
X
X
L
X
X
Shift register is cleared.
L
↑
H
X
X
First stage of the shift register goes low.
Other stages store the data of previous
stage, respectively.
H
↑
H
X
X
First stage of the shift register goes high.
Other stages store the data of previous
stage, respectively.
X
X
X
↑
X
Shift-register data is stored in the storage
register.
H = High Voltage Level, L = Low Voltage Level, X = Do not Care, Z = High Impedance
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The SN74LV595A-Q1 is a low-drive CMOS device that can be used for a multitude of bus interface type
applications where output ringing is a concern. The low drive and slow edge rates will minimize overshoot and
undershoot on the outputs. The inputs are 5-V tolerant allowing for down translation to VCC.
8
1K
R9
13
270
LED2
SRCLK
SRCLR
OB
OC
R3
270
OD
LED3
RCLK
OE
OF
OE
OG
R4
270
LED4
OH
GND
OH*
R5
270
LED5
R6
270
LED6
R7
270
LED7
R8
270
LED8
1
2
3
4
5
6
7
9
SN74LV595A-Q1
GND
VCC
GND
OA
15
GND
VCC
GND
12
µC
R2
16
SER
GND
10
LED1
GND
VCC
11
270
GND
IC1
14
R1
GND
VCC
GND
9.2 Typical Application
Figure 9-1. SN74LV595A-Q1 Expanding IOs to Drive LEDs
9.2.1 Power Considerations
Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions. The
supply voltage sets the device's electrical characteristics as described in the Electrical Characteristics section.
The positive voltage supply must be capable of sourcing current equal to the total current to be sourced
by all outputs of the SN74LV595A-Q1 plus the maximum static supply current, ICC, listed in the Electrical
Characteristics, and any transient current required for switching. The logic device can only source as much
current that is provided by the positive supply source. Be sure to not exceed the maximum total current through
VCC listed in the Absolute Maximum Ratings.
16
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The ground must be capable of sinking current equal to the total current to be sunk by all outputs of the
SN74LV595A-Q1 plus the maximum supply current, ICC, listed in the Electrical Characteristics, and any transient
current required for switching. The logic device can only sink as much current that can be sunk into its ground
connection. Be sure to not exceed the maximum total current through GND listed in the Absolute Maximum
Ratings.
The SN74LV595A-Q1 can drive a load with a total capacitance less than or equal to 50 pF while still meeting
all of the data sheet specifications. Larger capacitive loads can be applied; however, it is not recommended to
exceed 50 pF.
The SN74LV595A-Q1 can drive a load with total resistance described by RL ≥ VO / IO, with the output voltage
and current defined in the Electrical Characteristics table with VOH and VOL. When outputting in the HIGH state,
the output voltage in the equation is defined as the difference between the measured output voltage and the
supply voltage at the VCC pin.
Total power consumption can be calculated using the information provided in CMOS Power Consumption and
Cpd Calculation.
Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear
and Logic (SLL) Packages and Devices.
CAUTION
The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings, is an additional
limitation to prevent damage to the device. Do not violate any values listed in the Absolute Maximum
Ratings. These limits are provided to prevent damage to the device.
9.2.2 Input Considerations
Input signals must cross VIL(max) to be considered a logic LOW, and VIH(min) to be considered a logic HIGH. Do
not exceed the maximum input voltage range found in the Absolute Maximum Ratings.
Unused inputs must be terminated to either VCC or ground. The unused inputs can be directly terminated if the
input is completely unused, or they can be connected with a pull-up or pull-down resistor if the input will be used
sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is
used for a default state of LOW. The drive current of the controller, leakage current into the SN74LV595A-Q1 (as
specified in the Electrical Characteristics), and the desired input transition rate limits the resistor size. A 10-kΩ
resistor value is often used due to these factors.
The SN74LV595A-Q1 has CMOS inputs and thus requires fast input transitions to operate correctly, as defined
in the Recommended Operating Conditions table. Slow input transitions can cause oscillations, additional power
consumption, and reduction in device reliability.
Refer to the Feature Description section for additional information regarding the inputs for this device.
9.2.3 Output Considerations
The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will
decrease the output voltage as specified by the VOH specification in the Electrical Characteristics. The ground
voltage is used to produce the output LOW voltage. Sinking current into the output will increase the output
voltage as specified by the VOL specification in the Electrical Characteristics.
Push-pull outputs that could be in opposite states, even for a very short time period, should never be connected
directly together. This can cause excessive current and damage to the device.
Two channels within the same device with the same input signals can be connected in parallel for additional
output drive strength.
Unused outputs can be left floating. Do not connect outputs directly to VCC or ground.
Refer to the Feature Description section for additional information regarding the outputs for this device.
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9.2.4 Detailed Design Procedure
1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the
device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout
section.
2. Ensure the capacitive load at the output is ≤ 50 pF. This is not a hard limit; it will, however, ensure
optimal performance. This can be accomplished by providing short, appropriately sized traces from the
SN74LV595A-Q1 to one or more of the receiving devices.
3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum
output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load
measured in MΩ; much larger than the minimum calculated previously.
4. Thermal issues are rarely a concern for logic gates; the power consumption and thermal increase, however,
can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd
Calculation.
9.2.5 Application Curves
SER
QA
QB
QC
QC
QD
QE
QF
Output Registers
QB
Serial Registers
Output Registers
QA
Serial Registers
SER
QD
QE
QF
QG
QG
QH
QH
QH¶
QH¶
SRCLK rising edge shifts data
in the serial registers only
RCLK rising edge shifts data
to the output registers
Figure 9-2. Simplified Functional Diagram Showing Clock Operation
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10 Power Supply Recommendations
The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a
single supply, a 0.1 μF capacitor is recommended. If there are multiple VCC terminals then 0.01 μF or 0.022 μF
capacitors are recommended for each power terminal. It is ok to parallel multiple bypass capacitors to reject
different frequencies of noise. 0.1 μF and 1.0 μF capacitors are commonly used in parallel. The bypass capacitor
should be installed as close to the power terminal as possible for the best results.
11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states.
Specified in Figure 11-1 are rules that must be observed under all circumstances. All unused inputs of digital
logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should
be applied to any particular unused input depends on the function of the device. Generally they will be tied to
GND or VCC, whichever makes more sense or is more convenient. It is acceptable to float outputs unless the
part is a transceiver. If the transceiver has an output enable pin, it will disable the outputs section of the part
when asserted. This will not disable the input section of the I/Os so they also cannot float when disabled.
11.2 Layout Example
Recommend GND flood fill for
improved signal isolation, noise
reduction, and thermal dissipation
Unused inputs tie to GND or VCC
Avoid 90°
corners for
signal lines
GND VCC
Bypass capacitor
placed close to
the device
0.1 F
QB
1
16
VCC
QC
2
15
QA
QD
3
14
SER
QE
4
13
OE
QF
5
12
RCLK
QG
6
11
SRCLK
QH
7
10
GND
8
9
SRCLR
QH¶
Unused output
left floating
Figure 11-1. Layout Example for the SN74LV595A-Q1
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
•
•
Texas Instruments, CMOS Power Consumption and Cpd Calculation application report
Texas Instruments, Thermal Characteristics of Standard Linear and Logic (SLL) Packages and Devices
appliation report
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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15-Nov-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
PCLV595AQWBQBRQ1
ACTIVE
WQFN
BQB
16
3000
TBD
Call TI
Call TI
-40 to 125
SN74LV595AIPWRG4Q1
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV595AI
Samples
SN74LV595AIPWRQ1
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
LV595AI
Samples
SN74LV595AQPWRQ1
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV595AQ
Samples
SN74LV595AQWBQBRQ1
ACTIVE
WQFN
BQB
16
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV595Q
Samples
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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