SN74LV541A
SCLS410K – APRIL 1998 – REVISED NOVEMBER 2022
SN74LV541A Octal Buffers/Drivers With 3-State Outputs
1 Features
2 Applications
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
2-V to 5.5-V VCC operation
Max tpd of 6 ns at 5 V
Typical VOLP (output ground bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (output VOH undershoot)
> 2.3 V at VCC = 3.3 V, TA = 25°C
Support mixed-mode voltage operation on all ports
Ioff supports partial-power-down mode operation
Latch-up performance exceeds 250 mA per JESD
17
ESD protection exceeds JESD 22
– 3000-V Human-Body Model
– 2000-V Charged-Device Model
Smart grids
TVs
Set-top-boxes
Audio
Servers
Surveillance cameras
Network switches
Infotainment
3 Description
The SN74LV541A device is an octal buffer/driver
designed for 2-V to 5.5-V VCC operation.
Package Information(1)
PART NUMBER
SN74LV541A
(1)
PACKAGE
BODY SIZE (NOM)
RGY (VQFN, 20)
4.50 mm × 3.50 mm
RKS (VQFN, 20)
4.50 mm × 2.50 mm
DB (SSOP, 20)
7.20 mm × 5.30 mm
NS (SOP, 20)
12.60 mm × 5.30 mm
PW (TSSOP, 20)
6.50 mm × 4.40 mm
DGV (TVSOP, 20)
5.00 mm × 4.40 mm
DW (SOIC, 20)
12.80 mm × 7.50 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
OE1
OE2
A1
Y1
To Seven Other Channels
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LV541A
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SCLS410K – APRIL 1998 – REVISED NOVEMBER 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................6
6.6 Switching Characteristics, VCC = 2.5 V ± 0.2 V...........6
6.7 Switching Characteristics, VCC = 3.3 V ± 0.3 V...........6
6.8 Switching Characteristics, VCC = 5 V ± 0.5 V..............7
6.9 Noise Characteristics(1) ..............................................7
6.10 Operating Characteristics......................................... 7
6.11 Typical Characteristics.............................................. 8
7 Parameter Measurement Information.......................... 10
8 Detailed Description...................................................... 11
8.1 Overview................................................................... 11
8.2 Functional Block Diagram......................................... 11
8.3 Feature Description...................................................11
8.4 Device Functional Modes..........................................12
9 Application and Implementation.................................. 13
9.1 Application Information............................................. 13
9.2 Typical Application.................................................... 13
10 Power Supply Recommendations..............................15
11 Layout........................................................................... 16
11.1 Layout Guidelines................................................... 16
11.2 Layout Example...................................................... 16
12 Device and Documentation Support..........................17
12.1 Documentation Support.......................................... 17
12.2 Receiving Notification of Documentation Updates..17
12.3 Support Resources................................................. 17
12.4 Trademarks............................................................. 17
12.5 Glossary..................................................................17
12.6 Electrostatic Discharge Caution..............................17
12.7 Glossary..................................................................17
13 Mechanical, Packaging, and Orderable
Information.................................................................... 17
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision J (December 2014) to Revision K (November 2022)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Removed 200-V Machine Model from the Features section ..............................................................................1
• Added the RKS package information to the data sheet......................................................................................1
• Updated the Pin Functions table.........................................................................................................................3
• Updated the Typical Characteristics section.......................................................................................................8
• Updated the Functional Block Diagram figure...................................................................................................11
• Added the Balanced CMOS 3-State Outputs, Partial Power Down (Ioff), and Clamp Diode Structure sections...
11
• Updated the Application Information section.................................................................................................... 13
• Updated the Design Requirments section to include the Power Considerations, Input Considerations, and
Output Considerations sections........................................................................................................................13
• Updated the Detailed Design Procedure section..............................................................................................13
• Updated the Layout Example section............................................................................................................... 16
Changes from Revision I (April 2005) to Revision J (December 2014)
Page
• Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information
table, Typical Characteristics, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section................... 1
• Deleted Ordering Information table.....................................................................................................................1
• Changed MAX operating temperature tp 125°C in Recommended Operating Conditions table........................ 5
2
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5 Pin Configuration and Functions
OE1 VCC
OE1
1
20
VCC
A1
2
19
OE2
A1
2
19
OE2
3
18
Y1
1
20
A2
3
18
Y1
A2
A3
4
17
Y2
A3
4
17
Y2
A4
5
16
Y3
A4
5
16
Y3
A5
6
15
Y4
A5
6
15
Y4
A6
7
14
Y5
A6
7
14
Y5
A7
8
13
Y6
A8
9
12
Y7
A7
8
13
Y6
A8
9
12
Y7
10
11
Y8
GND
PAD
10
GND
Figure 5-1. DB, DGV, DW, NS, and PW Package,
20-Pin SSOP, TVSOP, SOIC, SO, TSSOP (Top View)
11
Y8
Figure 5-2. RGY and RKS Package, 20-Pin VQFN
with (Exposed Thermal Pad Top View)
Table 5-1. Pin Functions
PIN
NAME
NO.
TYPE(1)
DESCRIPTION
OE1
1
I
Output enable input 1, active low
A1
2
I
Input for channel 1
A2
3
I
Input for channel 2
A3
4
I
Input for channel 3
A4
5
I
Input for channel 4
A5
6
I
Input for channel 5
A6
7
I
Input for channel 6
A7
8
I
Input for channel 7
A8
9
I
Input for channel 8
GND
10
G
Ground
Y8
11
O
Output for channel 8
Y7
12
O
Output for channel 7
Y6
13
O
Output for channel 6
Y5
14
O
Output for channel 5
Y4
15
O
Output for channel 4
Y3
16
O
Output for channel 3
Y2
17
O
Output for channel 2
Y1
18
O
Output for channel 1
OE2
19
I
Output enable input 2, active low
VCC
20
P
Postive supply
—
The thermal pad can be connect to GND or left floating. Do not connect to any other signal
or supply.
Thermal Pad(2)
(1)
(2)
I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power.
RKS package only
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
VCC
MIN
MAX
Supply voltage range
–0.5
7
V
range(2)
–0.5
7
V
–0.5
7
V
–0.5
VCC + 0.5
VI
Input voltage
VO
Voltage range applied to any output in the high-impedance or power-off state(2)
state(2) (3)
UNIT
VO
Output voltage range applied in the high or low
IIK
Input clamp current
VI < 0
–20
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
VO = 0 to VCC
±35
mA
±70
mA
150
°C
Continuous current through VCC or GND
Tstg
(1)
(2)
(3)
Storage temperature range
–65
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Section 6.3 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
This value is limited to 5.5-V maximum.
6.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
V(ESD)
(1)
(2)
4
Electrostatic discharge
pins(1)
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002, all
pins(2)
UNIT
3000
2000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
SN74LV541A
VCC
MAX
2
5.5
Supply voltage
VCC = 2 V
VIH
MIN
High-level input voltage
Low-level input voltage
VI
Input voltage
VO
Output voltage
VCC × 0.7
VCC = 3 V to 3.6 V
VCC × 0.7
VCC = 4.5 V to 5.5 V
VCC × 0.7
V
0.5
VCC = 2.3 V to 2.7 V
VCC × 0.3
VCC = 3 V to 3.6 V
VCC × 0.3
VCC = 4.5 V to 5.5 V
IOH
IOL
High-level output current
Low-level output current
Δt/Δv
Input transition rise or fall rate
TA
Operating free-air temperature
V
VCC × 0.3
0
5.5
High or low state
0
VCC
3-state
0
5.5
VCC = 2 V
–50
VCC = 2.3 V to 2.7 V
–2
VCC = 3 V to 3.6 V
–8
VCC = 4.5 V to 5.5 V
–16
VCC = 2 V
50
VCC = 2.3 V to 2.7 V
2
VCC = 3 V to 3.6 V
8
VCC = 4.5 V to 5.5 V
16
VCC = 2.3 V to 2.7 V
200
VCC = 3 V to 3.6 V
100
VCC = 4.5 V to 5.5 V
(1)
V
1.5
VCC = 2.3 V to 2.7 V
VCC = 2 V
VIL
UNIT
V
V
µA
mA
µA
mA
ns/V
20
–40
125
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs (SCBA004).
6.4 Thermal Information
SN74LV541A
THERMAL
METRIC(1)
DB
DGV
DW
NS
PW
RGY
RKS
UNIT
20 PINS
RθJA
Junction-to-ambient thermal
resistance
96.0
116.1
79.8
77.1
102.8
35.1
75.2
RθJC(top)
Junction-to-case (top) thermal
resistance
57.7
31.3
45.8
43.6
36.8
43.3
79.4
RθJB
Junction-to-board thermal resistance
51.2
57.6
47.4
44.6
53.8
12.9
47.8
ψJT
Junction-to-top characterization
parameter
19.4
1.0
18.5
17.2
2.5
0.9
14.6
ψJB
Junction-to-board characterization
parameter
50.8
56.9
47.0
44.2
53.3
12.9
47.8
RθJC(bot)
Junction-to-case (bottom) thermal
resistance
—
—
—
—
—
7.9
31.5
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).
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6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25°C
MIN
TYP
MAX
–40°C to 125°C
MIN
MIN
MAX
UNIT
2 V to
5.5 V
IOH = –2 mA
2.3 V
2
2
2
IOH= –8 mA
3V
2.48
2.48
2.48
IOH = –16 mA
4.5 V
3.8
3.8
3.8
IOL = 50 µA
2 V to
5.5 V
0.1
0.1
0.1
IOL = 2 mA
2.3 V
0.4
0.4
0.4
IOL = 8 mA
3V
0.44
0.44
0.44
IOL = 16 mA
4.5 V
0.55
0.55
0.55
II
VI = 5.5 V or GND
0 to
5.5 V
±1
±1
±1
µA
VOL
IOZ
VO = VCC or GND
ICC
VI = VCC or GND,
Ioff
VI or VO = 0 to 5.5 V
Ci
VI = VCC or GND
IO = 0
VCC –
0.1
MAX
IOH = –50 µA
VOH
VCC –
0.1
–40°C to 85°C
VCC – 0.1
V
V
5.5 V
±5
±5
±5
µA
5.5 V
20
20
20
µA
5
5
5
µA
0
3.3 V
2
pF
6.6 Switching Characteristics, VCC = 2.5 V ± 0.2 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
Y
ten
OE
Y
tdis
OE
Y
tpd
A
ten
OE
tdis
OE
Y
LOAD
CAPACITANCE
TA = 25°C
MIN
–40°C to 85°C
–40°C to 125°C
TYP
MAX
MIN
MAX
MIN
MAX
6.7
11.3
1
13.5
1
13.5
8.5
16.6
1
19.5
1
19.5
8.4
13.1
1
15
1
15
Y
8.7
15.9
1
18.5
1
18.5
Y
10.5
20.7
1
24
1
24
12.3
17.9
1
20
1
20
CL = 15 pF
CL = 50 pF
tsk(o)
2
2
UNIT
ns
ns
2
6.7 Switching Characteristics, VCC = 3.3 V ± 0.3 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-1)
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
Y
ten
OE
Y
tdis
OE
Y
tpd
A
Y
ten
OE
Y
tdis
OE
Y
PARAMETER
tsk(o)
6
LOAD
CAPACITANCE
CL = 15 pF
CL = 50 pF
TA = 25°C
MIN
TYP
–40°C to 85°C
MAX
MIN
4.8
7
6.1
10.5
5.8
6.1
7.4
14
8.8
15.4
–40°C to 125°C
MAX
MIN
1
8.5
1
8.5
1
12.5
1
12.5
11
1
12
1
12
10.5
1
12
1
12
1
16
1
16
1
17.5
1
17.5
1.5
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1.5
MAX
UNIT
ns
ns
1.5
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6.8 Switching Characteristics, VCC = 5 V ± 0.5 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
Y
ten
OE
Y
tdis
OE
Y
tpd
A
Y
ten
OE
Y
tdis
OE
Y
LOAD
CAPACITANCE
TA = 25°C
MIN
CL = 15 pF
CL = 50 pF
–40°C to 85°C
–40°C to 125°C
TYP
MAX
MIN
MAX
MIN
MAX
3.5
5
1
6
1
6
4.3
7.2
1
8.5
1
8.5
3.9
7.5
1
8
1
8
4.3
7
1
8
1
8
5.3
9.2
1
10.5
1
10.5
5.6
8.8
1
10
1
10
tsk(o)
1
1
UNIT
ns
ns
1
6.9 Noise Characteristics(1)
VCC = 3.3 V, CL = 50 pF, TA = 25°C
SN74LV541A
PARAMETER
MIN
TYP
MAX
UNIT
VOL(P)
Quiet output, maximum dynamic VOL
0.5
0.8
V
VOL(V)
Quiet output, minimum dynamic VOL
–0.4
–0.8
V
VOH(V)
Quiet output, minimum dynamic VOH
VIH(D)
High-level dynamic input voltage
VIL(D)
Low-level dynamic input voltage
(1)
2.9
V
2.31
V
0.99
V
UNIT
Characteristics are for surface-mount packages only.
6.10 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
Outputs enabled
CL = 50 pF,
f = 10 MHz
VCC
TYP
3.3 V
16.3
5V
17.8
pF
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6.11 Typical Characteristics
0.16
0.3
0.14
0.25
0.12
0.2
VOL (V)
VOL (V)
0.1
0.08
0.06
0.15
0.1
0.04
0.02
0.05
VCC = 2.3 V
VCC = 3 V
0
0
2
4
IOL (mA)
6
0
8
Figure 6-1. Output Voltage in LOW State, 2.3- and 3-V Supply
3
2.8
VOH (V)
VOH (V)
2.7
2.6
2.5
2.4
2.3
2.2
VCC = 2.3 V
VCC = 3 V
2
-8
-6
-4
IOH (mA)
-2
0
Figure 6-3. Output Voltage in HIGH State, 2.3- and 3-V Supply
6
8
IOL (mA)
10
12
14
16
5.5
5.4
5.3
5.2
5.1
5
4.9
4.8
4.7
4.6
4.5
4.4
4.3
4.2
4.1
4
-16
VCC = 4.5 V
VCC = 5.5 V
-14
-12
-10
-8
IOH (mA)
-6
-4
-2
0
0.6
VCC = 2.5 V
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
VCC = 3.3 V
VCC = 5 V
0.54
ICC - Supply Current (mA)
ICC - Supply Current (mA)
4
Figure 6-4. Output Voltage in HIGH State, 4.5- and 5.5-V Supply
0.1
0.09
0.48
0.42
0.36
0.3
0.24
0.18
0.12
0.06
0
0
0
0.25
0.5
0.75
1
1.25 1.5 1.75
VI - Input Voltage (V)
2
2.25
2.5
Figure 6-5. Supply Current Across Input Voltage, 2.5-V Supply
8
2
Figure 6-2. Output Voltage in LOW State, 4.5- and 5.5-V Supply
2.9
2.1
VCC = 4.5 V
VCC = 5.5 V
0
0
0.5
1
1.5
2
2.5
3
3.5
VI - Input Voltage (V)
4
4.5
5
5.5
Figure 6-6. Supply Current Across Input Voltage, 3.3- and 5-V
Supply
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6.11 Typical Characteristics (continued)
4.5
7
TPD in ns
4
6
3.5
5
TPD (ns)
TPD (ns)
3
2.5
2
1.5
4
3
2
1
1
0.5
TPD in ns
0
-100
0
-50
0
50
Temperature (qC)
100
150
0
D001
Figure 6-7. TPD vs Temperature
1
2
3
VCC
4
5
6
D002
Figure 6-8. TPD vs VCC at 25°C
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7 Parameter Measurement Information
VCC
RL = 1 kΩ
From Output
Under Test
Test
Point
From Output
Under Test
S1
Open
TEST
GND
CL
(see Note A)
CL
(see Note A)
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
VCC
50% VCC
Timing Input
0V
tw
tsu
VCC
50% VCC
50% VCC
Input
th
VCC
50% VCC
Data Input
50% VCC
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
50% VCC
Input
50% VCC
tPLH
0V
tPHL
50% VCC
tPHL
Out-of-Phase
Output
50% VCC
VOL
VOH
50% VCC
VOL
tPLZ
≈VCC
50% VCC
tPZH
VOL + 0.3 V
VOL
tPHZ
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
50% VCC
0V
Output
Waveform 1
S1 at VCC
(see Note B)
tPLH
50% VCC
50% VCC
tPZL
VOH
In-Phase
Output
VCC
Output
Control
50% VCC
VOH – 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time, with one input transition per measurement.
E. tPLZ and tPHZ are the same as t dis.
F. t PZL and tPZH are the same as t en .
G. tPHL and tPLH are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 7-1. Load Circuit and Voltage Waveforms
10
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8 Detailed Description
8.1 Overview
The SN74LV541A device is an octal buffers/driver designed for 2-V to 5.5-V VCC operation.
The SN74LV541A device is ideal for driving bus lines or buffer memory address registers. It features inputs and
outputs on opposite sides of the package to facilitate printed circuit board layout.
The 3-state control gate is a two-input AND gate with active-low inputs so that if either output-enable (OE1 or
OE2) input is high, all corresponding outputs are in the high-impedance state. The outputs provide non-inverted
data when they are not in the high-impedance state.
To ensure the high-impedance state during power up or power down, both OE should be tied to VCC through a
pull-up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74LV541A device are fully specified for partial-power-down applications using Ioff. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
8.2 Functional Block Diagram
Shared Control Logic
OE1
OE2
Ax
Yx
One of Eight 3-State Buffers
Figure 8-1. Logic Diagram (Positive Logic)
8.3 Feature Description
8.3.1 Balanced CMOS 3-State Outputs
This device includes balanced CMOS 3-state outputs. Driving high, driving low, and high impedance are the
three states that these outputs can be in. The term balanced indicates that the device can sink and source
similar currents. The drive capability of this device may create fast edges into light loads, so routing and load
conditions should be considered to prevent ringing. Additionally, the outputs of this device can drive larger
currents than the device can sustain without being damaged. It is important for the output power of the device
to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the Absolute
Maximum Ratings must be followed at all times.
When placed into the high-impedance mode, the output will neither source nor sink current, with the exception of
minor leakage current as defined in the Electrical Characteristics table. In the high-impedance state, the output
voltage is not controlled by the device and is dependent on external factors. If no other drivers are connected
to the node, then this is known as a floating node and the voltage is unknown. A pull-up or pull-down resistor
can be connected to the output to provide a known voltage at the output while it is in the high-impedance state.
The value of the resistor will depend on multiple factors, including parasitic capacitance and power consumption
limitations. Typically, a 10-kΩ resistor can be used to meet these requirements.
Unused 3-state CMOS outputs should be left disconnected.
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8.3.2 Partial Power Down (Ioff)
This device includes circuitry to disable all outputs when the supply pin is held at 0 V. When disabled, the
outputs will neither source nor sink current, regardless of the input voltages applied. The amount of leakage
current at each output is defined by the Ioff specification in the Electrical Characteristics table.
8.3.3 Clamp Diode Structure
Figure 8-2 shows the inputs and outputs to this device have negative clamping diodes only.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage
to the device. The input and output voltage ratings may be exceeded if the input and output clampcurrent ratings are observed.
VCC
Device
Logic
Input
-IIK
Output
-IOK
GND
Figure 8-2. Electrical Placement of Clamping Diodes for Each Input and Output
8.4 Device Functional Modes
Table 8-1. Function Table
(Each Buffer or Driver)
INPUTS
12
A
OUTPUT
Y
OE1
OE2
L
L
L
L
L
L
H
H
H
X
X
Z
X
H
X
Z
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The SN74LV541A can be used to drive signals over relatively long traces or transmission lines. In order to
reduce ringing caused by impedance mismatches between the driver, transmission line, and receiver, a series
damping resistor placed in series with the transmitter’s output can be used. The figure in the Application Curve
section shows the received signal with three separate resistor values. Just a small amount of resistance can
make a significant impact on signal integrity in this type of application.
9.2 Typical Application
Regulated 3.3 V or 5 V
OE
VCC
OE
A1
Y1
A8
Y8
µC or
System Logic
µC
System Logic
LEDs
GND
Figure 9-1. Typical Application Schematic
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9.2.1 Power Considerations
Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions. The
supply voltage sets the device's electrical characteristics as described in the Electrical Characteristics section.
The positive voltage supply must be capable of sourcing current equal to the total current to be sourced by all
outputs of the SN74LV541A plus the maximum static supply current, ICC, listed in the Electrical Characteristics,
and any transient current required for switching. The logic device can only source as much current that is
provided by the positive supply source. Be sure to not exceed the maximum total current through VCC listed in
the Absolute Maximum Ratings.
The ground must be capable of sinking current equal to the total current to be sunk by all outputs of the
SN74LV541A plus the maximum supply current, ICC, listed in the Electrical Characteristics, and any transient
current required for switching. The logic device can only sink as much current that can be sunk into its ground
connection. Be sure to not exceed the maximum total current through GND listed in the Absolute Maximum
Ratings.
The SN74LV541A can drive a load with a total capacitance less than or equal to 50 pF while still meeting all of
the data sheet specifications. Larger capacitive loads can be applied; however, it is not recommended to exceed
50 pF.
The SN74LV541A can drive a load with total resistance described by RL ≥ VO / IO, with the output voltage and
current defined in the Electrical Characteristics table with VOH and VOL. When outputting in the HIGH state, the
output voltage in the equation is defined as the difference between the measured output voltage and the supply
voltage at the VCC pin.
Total power consumption can be calculated using the information provided in CMOS Power Consumption and
Cpd Calculation.
Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear
and Logic (SLL) Packages and Devices.
CAUTION
The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings, is an additional
limitation to prevent damage to the device. Do not violate any values listed in the Absolute Maximum
Ratings. These limits are provided to prevent damage to the device.
9.2.2 Input Considerations
Input signals must cross VIL(max) to be considered a logic LOW, and VIH(min) to be considered a logic HIGH. Do
not exceed the maximum input voltage range found in the Absolute Maximum Ratings.
Unused inputs must be terminated to either VCC or ground. The unused inputs can be directly terminated if the
input is completely unused, or they can be connected with a pull-up or pull-down resistor if the input will be used
sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used
for a default state of LOW. The drive current of the controller, leakage current into the SN74LV541A (as specified
in the Electrical Characteristics), and the desired input transition rate limits the resistor size. A 10-kΩ resistor
value is often used due to these factors.
The SN74LV541A has CMOS inputs and thus requires fast input transitions to operate correctly, as defined in
the Recommended Operating Conditions table. Slow input transitions can cause oscillations, additional power
consumption, and reduction in device reliability.
Refer to the Feature Description section for additional information regarding the inputs for this device.
14
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9.2.3 Output Considerations
The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will
decrease the output voltage as specified by the VOH specification in the Electrical Characteristics. The ground
voltage is used to produce the output LOW voltage. Sinking current into the output will increase the output
voltage as specified by the VOL specification in the Electrical Characteristics.
Push-pull outputs that could be in opposite states, even for a very short time period, should never be connected
directly together. This can cause excessive current and damage to the device.
Two channels within the same device with the same input signals can be connected in parallel for additional
output drive strength.
Unused outputs can be left floating. Do not connect outputs directly to VCC or ground.
Refer to the Feature Description section for additional information regarding the outputs for this device.
9.2.4 Detailed Design Procedure
1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the
device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout
section.
2. Ensure the capacitive load at the output is ≤ 50 pF. This is not a hard limit; it will, however, ensure optimal
performance. This can be accomplished by providing short, appropriately sized traces from the SN74LV541A
to one or more of the receiving devices.
3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum
output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load
measured in MΩ; much larger than the minimum calculated previously.
4. Thermal issues are rarely a concern for logic gates; the power consumption and thermal increase, however,
can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd
Calculation.
9.2.5 Application Curves
Figure 9-2. Switching Characteristics Comparison
10 Power Supply Recommendations
The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, 0.1 μF is recommended. If there are multiple VCC pins, 0.01 μF or 0.022 μF is recommended for each
power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μF and
1 μF are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as
possible for best results.
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11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states.
Specified in Figure 11-1 are rules that must be observed under all circumstances. All unused inputs of digital
logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should
be applied to any particular unused input depends on the function of the device. Generally they will be tied to
GND or VCC, whichever makes more sense or is more convenient. It is acceptable to float outputs unless the
part is a transceiver. If the transceiver has an output enable pin, it will disable the outputs section of the part
when asserted. This will not disable the input section of the I/Os so they also cannot float when disabled.
11.2 Layout Example
VCC
Recommend GND flood fill for
improved signal isolation, noise
reduction, and thermal dissipation
GND
F
OE1
1
Unused input
tied to GND
Avoid 90°
corners for
signal lines
VCC
A1
2
20
19
A2
3
18
Y1
A3
4
17
Y2
A4
5
16
Y3
A5
6
15
Y4
A6
7
14
Y5
A7
8
13
Y6
A8
9
10
12
11
Y7
GND
Y8
GND
Bypass capacitor
placed close to the
device
OE2
Unused output
left floating
Figure 11-1. Layout Example for the SN74LV541A in the RKS package
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
•
•
•
Texas Instruments, CMOS Power Consumption and Cpd Calculation
Texas Instruments, Implications of Slow or Floating CMOS Inputs application notes
Texas Instruments, Thermal Characteristics of Standard Linear and Logic (SLL) Packages and Devices
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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11-Dec-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN74LV541ADBR
ACTIVE
SSOP
DB
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV541A
Samples
SN74LV541ADBRE4
ACTIVE
SSOP
DB
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV541A
Samples
SN74LV541ADW
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV541A
Samples
SN74LV541ADWR
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV541A
Samples
SN74LV541ANSR
ACTIVE
SO
NS
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
74LV541A
Samples
SN74LV541APW
ACTIVE
TSSOP
PW
20
70
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV541A
Samples
SN74LV541APWG4
ACTIVE
TSSOP
PW
20
70
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV541A
Samples
SN74LV541APWR
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
LV541A
Samples
SN74LV541APWRG4
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV541A
Samples
SN74LV541APWT
ACTIVE
TSSOP
PW
20
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV541A
Samples
SN74LV541ARGYR
ACTIVE
VQFN
RGY
20
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LV541A
Samples
SN74LV541ARKSR
ACTIVE
VQFN
RKS
20
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV541A
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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