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SN54LV74A, SN74LV74A
SCLS381M – AUGUST 1997 – REVISED MARCH 2015
SNx4LV74A Dual Positive-Edge-Triggered D-Type Flip-Flops
1 Features
3 Description
•
•
•
These dual positive-edge-triggered D-type flip-flops
are designed for 2-V to 5.5-V VCC operation.
1
•
•
•
•
•
2-V to 5.5-V VCC Operation
Maximum tpd of 8.5 ns at 5 V
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
> 2.3 V at VCC = 3.3 V, TA = 25°C
Support Mixed-Mode Voltage Operation on
All Ports
Ioff Supports Partial-Power-Down
Mode Operation
Latch-up Performance Exceeds 250 mA
Per JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 500-V Charged-Device Model (C101)
Device Information(1)
PART NUMBER
PACKAGE
SN74LV74A
BODY SIZE (NOM)
VQFN (14)
3.50 mm × 3.50 mm
SOIC (14)
8.65 mm × 3.91 mm
SOP (14)
10.30 mm × 5.30 mm
SSOP (14)
6.20 mm × 5.30 mm
TSSOP (14)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram, Each Flip-Flop
(Positive Logic)
PRE
CLK
C
C
C
Q
2 Applications
•
•
•
•
•
•
Programmable Logic Controller (PLC)
DCS and PAC: Analog Input Module
AV Receiver
Server PSU
STB, DVR, and Streaming Media (Withdraw)
Server Motherboard
TG
C
C
C
C
D
TG
TG
TG
C
C
C
Q
CLR
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
SN54LV74A, SN74LV74A
SCLS381M – AUGUST 1997 – REVISED MARCH 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
4
4
5
5
6
6
6
6
7
7
7
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Electrical Characteristics...........................................
Switching Characteristics: VCC = 2.5 V ± 0.2 V ........
Switching Characteristics: VCC = 3.3 V ± 0.3 V ........
Switching Characteristics: VCC = 5 V ± 0.5 V ...........
Timing Requirements: VCC = 2.5 V ± 0.2 V ..............
Timing Requirements: VCC = 3.3 V ± 0.3 V ..............
Timing Requirements: VCC = 5 V ± 0.5 V ...............
Noise Characteristics ..............................................
Operating Characteristics........................................
Typical Characteristics ............................................
7
8
Parameter Measurement Information .................. 9
Detailed Description ............................................ 10
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
10
10
10
11
Application and Implementation ........................ 12
9.1 Application Information............................................ 12
9.2 Typical Application ................................................. 12
10 Power Supply Recommendations ..................... 14
11 Layout................................................................... 14
11.1 Layout Guidelines ................................................. 14
11.2 Layout Example .................................................... 14
12 Device and Documentation Support ................. 15
12.1
12.2
12.3
12.4
Documentation Support ........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
15
15
15
15
13 Mechanical, Packaging, and Orderable
Information ........................................................... 15
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision L (April 2005) to Revision M
Page
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
•
Removed Ordering Information table. .................................................................................................................................... 1
2
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SN74LV74A
SN54LV74A, SN74LV74A
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SCLS381M – AUGUST 1997 – REVISED MARCH 2015
5 Pin Configuration and Functions
D, DGV, NS, or PW Package
14-PIN SOIC, SOP, SSOP, or TSSOP
Top View
1CLR
1D
1CLK
1PRE
1Q
1Q
GND
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
2CLR
2D
2CLK
2PRE
2Q
2Q
VCC
1
14
2
13 2CLR
3
12 2D
2CLK
4
11
5
10 2PRE
9 2Q
7
8
2Q
6
GND
1D
1CLK
1PRE
1Q
1Q
1CLR
RGY Package
14-PIN VQFN
Top View
Pin Functions
PIN
I/O
DESCRIPTION
NO.
NAME
1
1CLR
I
1 clear
2
1D
I
1D input
3
1CLK
I
1 clock
4
1PRE
I
1 preset
5
1Q
O
1Q output
6
1Q
O
1Q output
7
GND
–
GND
8
2Q
O
2Q output
9
2Q
O
2Q output
10
2PRE
I
2 preset
11
2CLK
I
2 clock
12
2D
I
2D input
13
2CLR
I
2 clear
14
Vcc
–
Supply voltage input
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6 Specifications
6.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
VCC
MIN
MAX
UNIT
Supply voltage
–0.5
7
V
(2)
VI
Input voltage
–0.5
7
V
VO
Voltage applied to any output in the high-impedance or power-off state (2)
–0.5
7
V
VO
Output voltage (2) (3)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–20
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
VO = 0 to VCC
±25
mA
±50
mA
Continuous current through VCC or GND
D package (4)
θJA
Package thermal impedance
Tstg
(1)
(2)
(3)
(4)
(5)
86
DB package (4)
96
DGV package (4)
127
NS package (4)
76
PW package (4)
113
RGY package (5)
47
Storage temperature
–65
150
°C/W
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
This value is limited to 5.5 V maximum.
The package thermal impedance is calculated in accordance with JESD 51-7.
The package thermal impedance is calculated in accordance with JESD 51-5.
6.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
4
Electrostatic discharge
(1)
UNIT
2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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SCLS381M – AUGUST 1997 – REVISED MARCH 2015
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
SN54LV74A (2)
VCC
MIN
MAX
MIN
MAX
2
5.5
2
5.5
Supply voltage
VCC = 2 V
VIH
High-level input voltage
Low-level input voltage
UNIT
V
1.5
VCC = 2.3 V to 2.7 V
VCC × 0.7
VCC × 0.7
VCC = 3 V to 3.6 V
VCC × 0.7
VCC × 0.7
VCC = 4.5 V to 5.5 V
VCC × 0.7
V
VCC × 0.7
VCC = 2 V
VIL
SN74LV74A
0.5
0.5
VCC = 2.3 V to 2.7 V
VCC × 0.3
VCC × 0.3
VCC = 3 V to 3.6 V
VCC × 0.3
VCC × 0.3
VCC = 4.5 V to 5.5 V
VCC × 0.3
VCC × 0.3
V
VI
Input voltage
0
5.5
0
5.5
VO
Output voltage
0
VCC
0
VCC
V
–50
–50
µA
–2
–2
VCC = 2 V
IOH
VCC = 2.3 V to 2.7 V
High-level output current
VCC = 3 V to 3.6 V
–6
–6
–12
–12
50
50
VCC = 2.3 V to 2.7 V
2
2
VCC = 3 V to 3.6 V
6
6
VCC = 4.5 V to 5.5 V
12
12
VCC = 2.3 V to 2.7 V
200
200
VCC = 3 V to 3.6 V
100
100
20
20
VCC = 4.5 V to 5.5 V
VCC = 2 V
IOL
Low-level output current
Δt/Δv
Input transition rise or fall rate
VCC = 4.5 V to 5.5 V
TA
(1)
(2)
Operating free-air temperature
–55
125
–40
V
mA
µA
mA
ns/V
125
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, SCBA004.
Product Preview
6.4 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VOH
TEST CONDITIONS
MIN TYP
MIN TYP
MAX
SN74LV74A
–40°C to 125°C
MAX
VCC–0.
1
VCC–0.1
MIN
IOH = –2 mA
2.3 V
2
2
2
IOH = –6 mA
3V
2.48
2.48
2.48
4.5 V
3.8
TYP
UNIT
MAX
VCC–0.1
3.8
V
3.8
IOL = 50 µA
2 V to 5.5 V
0.1
0.1
IOL = 2 mA
2.3 V
0.4
0.4
0.4
IOL = 6 mA
3V
0.44
0.44
0.44
4.5 V
IOL = 12 mA
VI = 5.5 V or GND
ICC
VI = VCC or GND,
Ioff
VI or VO = 5.5 V
(1)
SN74LV74A
–40°C to 85°C
2 V to 5.5 V
II
Ci
SN54LV74A (1)
IOH = –50 µA
IOH = –12 mA
VOL
VCC
VI = VCC or GND
IO = 0
0.1
V
0.55
0.55
0.55
0 to 5.5 V
±1
±1
±1
µA
5.5 V
20
20
20
µA
0
5
5
5
µA
3.3 V
2
2
2
5V
2
2
2
pF
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6.5 Switching Characteristics: VCC = 2.5 V ± 0.2 V
over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
PRE or CLR
tpd
CLK
PRE or CLR
tpd
(1)
(2)
CLK
LOAD
CAPACITANCE
SN74LV74A
–40°C to 85°C
SN54LV74A (1)
TA = 25°C
MIN
TYP
CL = 15 pF
50 (2)
100 (2)
40 (2)
40
40
CL = 50 pF
30
70
25
25
25
Q or Q
CL = 15 pF
Q or Q
CL = 50 pF
9.8
MAX
(2)
14.8
MIN
(2)
1
(2)
MAX
17
(2)
MIN
SN74LV74A
–40°C to 125°C
MAX
MIN
UNIT
MAX
MHz
1
17
1
18
11.1 (2)
16.4 (2)
1 (2)
19 (2)
1
19
1
20
13
17.4
1
20
1
20
1
21
14.2
20
1
23
1
23
1
24
ns
ns
Product Preview
On products compliant to MIL-PRF-38535, this parameter is not production tested.
6.6 Switching Characteristics: VCC = 3.3 V ± 0.3 V
over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
CL = 15 pF
fmax
CL = 50 pF
PRE or CLR
tpd
CLK
PRE or CLR
tpd
(1)
(2)
LOAD
CAPACITANCE
CLK
Q or Q
CL = 15 pF
Q or Q
CL = 50 pF
MIN
TYP
MAX
80 (2) 140 (2)
50
SN74LV74A
–40°C to 85°C
SN54LV74A (1)
TA = 25°C
90
MIN
MAX
MIN
SN74LV74A
–40°C to 125°C
MAX
MIN
70 (2)
70
70
45
45
45
MHz
6.9 (2)
12.3 (2)
1 (2)
14.5 (2)
1
14.5
1
15.5
(2)
(2)
(2)
14 (2)
1
14
1
15
7.9
11.9
1
UNIT
MAX
9.2
15.8
1
18
1
18
1
19
10.2
15.4
1
17.5
1
17.5
1
18.5
ns
ns
Product Preview
On products compliant to MIL-PRF-38535, this parameter is not production tested.
6.7 Switching Characteristics: VCC = 5 V ± 0.5 V
over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
tpd
tpd
(1)
(2)
PRE or CLR
CLK
PRE or CLR
CLK
LOAD
CAPACITANCE
SN54LV74A (1)
TA = 25°C
TYP
CL = 15 pF
130 (2)
180 (2)
110 (2)
110
110
CL = 50 pF
90
140
75
75
75
CL = 15 pF
Q or Q
CL = 50 pF
MIN
MAX
MIN
SN74LV74A
–40°C to 125°C
MIN
Q or Q
MAX
SN74LV74A
–40°C to 85°C
MAX
MIN
MHz
5 (2)
7.7 (2)
1 (2)
9 (2)
1
9
1
10
(2)
(2)
(2)
(2)
1
8.5
1
9.5
5.6
7.3
1
8.5
UNIT
MAX
6.6
9.7
1
11
1
11
1
12
7.2
9.3
1
10.5
1
10.5
1
11.5
ns
ns
Product Preview
On products compliant to MIL-PRF-38535, this parameter is not production tested.
6.8 Timing Requirements: VCC = 2.5 V ± 0.2 V
over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 3)
TA = 25°C
MIN
tw
Pulse duration
tsu
Setup time before CLK↑
th
Hold time, data after CLK↑
(1)
6
MAX
SN54LV74A (1)
MIN
MAX
SN74LV74A
–40°C to 85°C
MIN
MAX
SN74LV74A
–40°C to 125°C
MIN
PRE or CLR low
8
9
9
9
CLK
8
9
9
9
Data
8
9
9
9
PRE or CLR inactive
7
7
7
7
0.5
0.5
0.5
0.5
UNIT
MAX
ns
ns
ns
Product Preview
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6.9 Timing Requirements: VCC = 3.3 V ± 0.3 V
over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 3)
TA = 25°C
MIN
tw
Pulse duration
tsu
Setup time before CLK↑
th
Hold time, data after CLK↑
(1)
MAX
SN54LV74A (1)
MIN
MAX
SN74LV74A
–40°C to 85°C
MIN
SN74LV74A
–40°C to 125°C
MAX
MIN
PRE or CLR low
6
7
7
7
CLK
6
7
7
7
Data
6
7
7
7
PRE or CLR inactive
5
5
5
5
0.5
0.5
0.5
0.5
UNIT
MAX
ns
ns
ns
Product Preview
6.10 Timing Requirements: VCC = 5 V ± 0.5 V
over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 3)
TA = 25°C
MIN
tw
Pulse duration
tsu
Setup time before CLK↑
th
Hold time, data after CLK↑
(1)
MAX
SN54LV74A (1)
MIN
MAX
SN74LV74A
–40°C to 85°C
MIN
SN74LV74A
–40°C to 125°C
MAX
MIN
PRE or CLR low
5
5
5
5
CLK
5
5
5
5
Data
5
5
5
5
PRE or CLR inactive
3
3
3
3
0.5
0.5
0.5
0.5
UNIT
MAX
ns
ns
ns
Product Preview
6.11 Noise Characteristics (1)
VCC = 3.3 V, CL = 50 pF, TA = 25°C
SN74LV74A
PARAMETER
MIN
TYP
UNIT
MAX
VOL(P)
Quiet output, maximum dynamic VOL
0.1
0.8
V
VOL(V)
Quiet output, minimum dynamic VOL
0
–0.8
V
VOH(V)
Quiet output, minimum dynamic VOH
3.2
VIH(D)
High-level dynamic input voltage
VIL(D)
Low-level dynamic input voltage
(1)
V
2.31
V
0.99
V
Characteristics are for surface-mount packages only.
6.12 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
CL = 50 pF
f = 10 MHz
VCC
TYP
3.3 V
21
5V
23
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SN74LV74A
UNIT
pF
7
SN54LV74A, SN74LV74A
SCLS381M – AUGUST 1997 – REVISED MARCH 2015
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6.13 Typical Characteristics
12
8
7
10
8
5
TPD (ns)
TPD (ns)
6
4
3
6
4
2
2
1
0
-100
0
-50
0
50
Temperature
100
150
0
D001
Figure 1. TPD vs. Temperature at 3.3 V
8
1
2
3
VCC
4
5
6
D002
Figure 2. TPD vs. VCC at 25°C
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SCLS381M – AUGUST 1997 – REVISED MARCH 2015
7 Parameter Measurement Information
VCC
From Output
Under Test
Test
Point
From Output
Under Test
RL = 1 kΩ
S1
Open
TEST
GND
CL
(see Note A)
CL
(see Note A)
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
VCC
50% VCC
Timing Input
0V
tw
tsu
VCC
50% VCC
50% VCC
Input
th
VCC
50% VCC
Data Input
50% VCC
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
50% VCC
Input
50% VCC
tPLH
In-Phase
Output
tPHL
Out-of-Phase
Output
0V
tPHL
50% VCC
VOH
50% VCC
VOL
VOH
50% VCC
VOL
50% VCC
tPZL
tPLZ
≈VCC
50% VCC
tPZH
VOL + 0.3 V
VOL
tPHZ
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
50% VCC
0V
Output
Waveform 1
S1 at VCC
(see Note B)
tPLH
50% VCC
VCC
Output
Control
50% VCC
VOH − 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time, with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. t PZL and tPZH are the same as ten.
G. tPHL and tPLH are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
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8 Detailed Description
8.1 Overview
These dual positive-edge-triggered D-type flip-flops are designed for 2-V to 5.5-V VCC operation.
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) inputs meeting the setup-time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,
data at the D input can be changed without affecting the levels at the outputs. The state of the output upon
power-up is not known until the first valid clock edge has occurred while VCC is within Recommended Operating
Conditions.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the devices when they are powered down.
8.2 Functional Block Diagram
PRE
CLK
C
C
C
Q
TG
C
C
C
C
D
TG
TG
TG
C
C
C
Q
CLR
Figure 4. Logic Diagram, Each Flip-Flop (Positive Logic)
8.3 Feature Description
The device’s wide operating range allows it to be used in a variety of systems that use different logic levels. The
low propagation delay allows fast switching and higher speeds of operation. In addition, the low ground bounce
stabilizes the performance of non-switching outputs while another output is switching.
10
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8.4 Device Functional Modes
Table 1. Function Table
INPUTS
OUTPUTS
PRE
CLR
CLK
D
Q
L
H
X
X
H
L
H
L
X
X
L
H
L
L
X
X
H (1)
H (1)
H
H
↑
H
H
L
H
H
↑
L
L
H
H
H
L
X
Q0
Q0
(1)
Q
This configuration is nonstable; that is, it does not persist when PRE
or CLR returns to its inactive (high) level.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74LV74A is a Low drive CMOS device that can be used for a multitude of bus interface type applications
where output ringing is a concern. The low drive and slow edge rates will minimize overshoot and undershoot on
the outputs. The inputs can accept voltages to 5.5 V at any valid VCC making it Ideal for down translation.
9.2 Typical Application
Figure 5. Typical Application Schematic
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it
can drive currents that would exceed maximum limits. The high drive will also create fast edges into light loads
so consider routing and load conditions to prevent ringing.
12
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Typical Application (continued)
9.2.2 Detailed Design Procedure
• Recommended input conditions:
– Specified High and low levels. See (VIH and VIL) in Recommended Operating Conditions.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
• Recommended output conditions:
– Load currents should not exceed 25 mA per output and 50 mA total for the part.
– Outputs should not be pulled above VCC.
9.2.3 Application Curves
Figure 6. Switching Characteristics Comparison
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10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, TI recommends a 0.1-μF capacitor and if there are multiple VCC terminals then TI recommends a 0.01-μF
or 0.022-μF capacitor for each power terminal. Multiple bypass capacitors can be paralleled to reject different
frequencies of noise. Frequencies of 0.1 μF and 1 μF are commonly used in parallel. The bypass capacitor
should be installed as close as possible to the power terminal for best results.
11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices inputs should not ever float.
In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two
inputs of a triple-input AND gate are used or only three of the four buffer gates are used. Such input pins should
not be left unconnected because the undefined voltages at the outside connections result in undefined
operational states. Specified below are the rules that must be observed under all circumstances. All unused
inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic
level that should be applied to any particular unused input depends on the function of the device. Generally they
will be tied to GND or VCC whichever make more sense or is more convenient. Floating outputs is generally
acceptable, unless the part is a transceiver. If the transceiver has an output enable pin it will disable the outputs
section of the part when asserted. This will not disable the input section of the I.O’s so they also cannot float
when disabled.
11.2 Layout Example
Figure 7. Layout Recommendation
14
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
Implications of Slow or Floating CMOS Inputs, SCBA004
12.2 Trademarks
All trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN74LV74AD
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV74A
SN74LV74ADBR
ACTIVE
SSOP
DB
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV74A
SN74LV74ADGVR
ACTIVE
TVSOP
DGV
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV74A
SN74LV74ADR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV74A
SN74LV74ANSR
ACTIVE
SO
NS
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
74LV74A
SN74LV74APW
ACTIVE
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV74A
SN74LV74APWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
LV74A
SN74LV74APWRG4
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV74A
SN74LV74APWT
ACTIVE
TSSOP
PW
14
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV74A
SN74LV74ARGYR
ACTIVE
VQFN
RGY
14
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LV74A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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