SN74LV74AQDRQ1

SN74LV74A-Q1 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP SCLS556B − DECEMBER 2003 − REVISED APRIL 2008 D D D D D D D D D D OR PW PACKAGE (TOP VIEW) Qualified for Automotive Applications 2-V to 5.5-V VCC Operation Max tpd of 13 ns at 5 V Typical VOLP (Output Ground Bounce) 2.3 V at VCC = 3.3 V, TA = 25°C Support Mixed-Mode Voltage Operation on All Ports Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) 1CLR 1D 1CLK 1PRE 1Q 1Q GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 2CLR 2D 2CLK 2PRE 2Q 2Q description/ordering informationS This dual positive-edge-triggered D-type flip-flop is designed for 2-V to 5.5-V VCC operation. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION{ 40°C to 125°C −40°C ORDERABLE PART NUMBER PACKAGE‡ TA TOP-SIDE MARKING SOIC − D Tape and reel SN74LV74AQDRQ1 LV74A TSSOP − PW Tape and reel SN74LV74AQPWRQ1 LV74A † For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at http://www.ti.com. ‡ Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2008, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74LV74A-Q1 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP SCLS556B − DECEMBER 2003 − REVISED APRIL 2008 FUNCTION TABLE OUTPUTS INPUTS † PRE CLR CLK D Q L H X X H Q L H L X X L H L L X X H† H† H H ↑ H H L H H ↑ L L H H H L X Q0 Q0 This configuration is nonstable; that is, it does not persist when PRE or CLR returns to its inactive (high) level. logic diagram, each flip-flop (positive logic) PRE CLK C C C Q TG C C C C D TG TG TG C C C Q CLR absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74LV74A-Q1 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP SCLS556B − DECEMBER 2003 − REVISED APRIL 2008 recommended operating conditions (see Note 4) VCC Supply voltage VCC = 2 V VIH High level input voltage High-level MIN MAX 2 5.5 Low level input voltage Low-level V 1.5 VCC = 2.3 V to 2.7 V VCC × 0.7 VCC = 3 V to 3.6 V VCC × 0.7 VCC = 4.5 V to 5.5 V VCC × 0.7 V VCC = 2 V VIL UNIT 0.5 VCC = 2.3 V to 2.7 V VCC × 0.3 VCC = 3 V to 3.6 V VCC × 0.3 VCC = 4.5 V to 5.5 V VCC × 0.3 V VI Input voltage 0 5.5 VO Output voltage 0 VCC V −50 µA VCC = 2 V IOH High level output current High-level VCC = 2.3 V to 2.7 V −2 VCC = 3 V to 3.6 V −6 VCC = 4.5 V to 5.5 V ∆t/∆v 2 VCC = 3 V to 3.6 V Input transition rise or fall rate 6 VCC = 4.5 V to 5.5 V 12 VCC = 2.3 V to 2.7 V 200 VCC = 3 V to 3.6 V 100 VCC = 4.5 V to 5.5 V TA µA 50 VCC = 2.3 V to 2.7 V Low level output current Low-level mA −12 VCC = 2 V IOL V Operating free-air temperature mA ns/V 20 −40 °C 125 NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH TEST CONDITIONS VCC 2 V to 5.5 V IOH = −2 mA 2.3 V 2 IOH = −6 mA 3V 2.48 4.5 V 3.8 IOH = −12 mA VOL TYP MAX V 2 V to 5.5 V IOL = 2 mA 2.3 V 0.4 IOL = 6 mA 3V 0.44 4.5 V 0.55 IOL = 12 mA VI = 5.5 V or GND ICC VI = VCC or GND, Ioff VI or VO = 0 to 5.5 V 0.1 V 0 to 5.5 V ±1 µA 5.5 V 20 µA 0 5 µA IO = 0 VI = VCC or GND POST OFFICE BOX 655303 UNIT VCC−0.1 IOL = 50 µA II Ci MIN IOH = −50 µA • DALLAS, TEXAS 75265 3.3 V 2 5V 2 pF 3 SN74LV74A-Q1 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP SCLS556B − DECEMBER 2003 − REVISED APRIL 2008 timing requirements over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) TA = 25°C PARAMETER tw Pulse duration tsu Setup time before CLK↑ th Hold time, data after CLK↑ MIN MAX MIN PRE or CLR low 8 9 CLK 8 9 Data 8 9 PRE or CLR inactive 7 7 0.5 0.5 MAX UNIT ns ns ns timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) TA = 25°C PARAMETER tw Pulse duration tsu Setup time before CLK↑ th Hold time, data after CLK↑ MIN MAX MIN PRE or CLR low 6 7 CLK 6 7 Data 6 7 PRE or CLR inactive 5 5 0.5 0.5 MAX UNIT ns ns ns timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) TA = 25°C PARAMETER tw Pulse duration tsu Setup time before CLK↑ th Hold time, data after CLK↑ MIN FROM (INPUT) TO (OUTPUT) fmax PRE or CLR low 5 5 5 5 Data 5 5 PRE or CLR inactive 3 3 0.5 0.5 tpd LOAD CAPACITANCE CLK Q or Q TYP 30 70 CL = 50 pF FROM (INPUT) TO (OUTPUT) fmax tpd 4 LOAD CAPACITANCE CL = 50 pF PRE or CLR CLK Q or Q POST OFFICE BOX 655303 CL = 50 pF • DALLAS, TEXAS 75265 ns range, MIN UNIT MAX MAX 25 MHz 1 20 14.2 20 1 23 ns temperature range, MIN UNIT TA = 25°C 50 ns 17.4 TYP UNIT ns 13 free-air MIN MAX temperature TA = 25°C switching characteristics over recommended operating VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER free-air MIN CL = 50 pF PRE or CLR MIN CLK switching characteristics over recommended operating VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) PARAMETER MAX MAX 90 MAX 45 MHz 9.2 15.8 1 18 10.2 15.4 1 18 ns SN74LV74A-Q1 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP SCLS556B − DECEMBER 2003 − REVISED APRIL 2008 switching characteristics over recommended operating VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax tpd Q or Q CLK temperature range, MIN UNIT TA = 25°C LOAD CAPACITANCE CL = 50 pF PRE or CLR free-air MIN TYP 90 140 CL = 50 pF MAX MAX 75 MHz 6.6 9.7 1 12 7.2 9.3 1 13 MIN TYP MAX ns noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25°C (see Note 5) PARAMETER UNIT VOL(P) Quiet output, maximum dynamic VOL 0.1 0.8 V VOL(V) Quiet output, minimum dynamic VOL 0 −0.8 V VOH(V) Quiet output, minimum dynamic VOH VIH(D) High-level dynamic input voltage VIL(D) Low-level dynamic input voltage 3.2 V 2.31 V 0.99 V TYP UNIT NOTE 5: Characteristics are for surface-mount packages only. operating characteristics, TA = 25°C PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS pF CL = 50 pF, POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 f = 10 MHz VCC 3.3 V 21 5V 23 pF 5 SN74LV74A-Q1 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP SCLS556B − DECEMBER 2003 − REVISED APRIL 2008 PARAMETER MEASUREMENT INFORMATION VCC From Output Under Test Test Point RL = 1 kΩ From Output Under Test CL (see Note A) S1 Open TEST GND S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain CL (see Note A) Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input 0V tw tsu VCC 50% VCC 50% VCC Input th VCC 50% VCC Data Input 50% VCC 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC 50% VCC Input 50% VCC tPLH tPHL 50% VCC tPHL 50% VCC VOL tPLZ ≈VCC 50% VCC tPZH VOH 50% VCC VOL Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 50% VCC 0V Output Waveform 1 S1 at VCC (see Note B) tPLH 50% VCC 50% VCC tPZL VOH In-Phase Output Out-of-Phase Output 0V VCC Output Control VOL + 0.3 V VOL tPHZ 50% VCC VOH − 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time, with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN74LV74AQDRG4Q1 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LV74A SN74LV74AQDRQ1 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LV74A SN74LV74AQPWRG4Q1 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LV74A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of