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SN74LVC1G80-Q1
SCES885 – APRIL 2017
SN74LVC1G80-Q1 Single Positive-Edge-Triggered D-Type Flip-Flop
1 Features
3 Description
•
•
The SN74LVC1G80-Q1 device is an automotive
AEC-Q100 qualified, single positive-edge-triggered Dtype flip-flop that is designed for 1.65-V to 5.5-V VCC
operation.
1
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– ±4000-V Human-Body Model (HBM) ESD
Classification Level 3A
– ±1000-V Charged-Device Model (CDM) ESD
Classification Level C5
Supports 5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Supports Down Translation to VCC
Maximum tpd of 6 ns at 3.3 V
Low Power Consumption, 10-µA Max ICC
±24-mA Output Drive at 3.3 V
Ioff supports Partial-Power-Down Mode and BackDrive Protection
When data at the data (D) input meets the setup time
requirement, the data is transferred to the Q output
on the positive-going edge of the clock pulse. Clock
triggering occurs at a voltage level and is not directly
related to the rise time of the clock pulse. Following
the hold-time interval, data at the D input can be
changed without affecting the level at the output.
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs when the device is powered down. This
inhibits current backflow into the device which
prevents damage to the device.
Device Information(1)
2 Applications
•
•
•
•
•
Automotive
Automotive
Automotive
Automotive
Automotive
PART NUMBER
Infotainment
Cluster
ADAS
Body Electronics
HEV/EV Powertrain
SN74LVC1G80-Q1
PACKAGE
SC70 (5)
BODY SIZE
2.00 mm × 1.25 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
2
CLK
C
C
C
4
TG
C
C
Q
C
C
D
1
TG
TG
TG
C
C
C
Copyright © 2017, Texas Instruments Incorporated
(1)
TG - Transmission Gate
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC1G80-Q1
SCES885 – APRIL 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
8
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
11
11
11
12
Application and Implementation ........................ 13
9.1 Application Information............................................ 13
9.2 Typical Application ................................................. 13
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
Absolute Maximum Ratings ..................................... 3
ESD Ratings.............................................................. 3
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 4
Electrical Characteristics........................................... 5
Timing Requirements: TA = –40°C to +85°C ............ 5
Timing Requirements: TA = –40°C to +125°C .......... 6
Switching Characteristics: TA = –40°C to +85°C, CL =
15 pF .......................................................................... 6
6.9 Switching Characteristics: TA = –40°C to +85°C, CL =
30 pF or 50 pF ........................................................... 6
6.10 Switching Characteristics: TA = –40°C to +125°C,
CL = 30 pF or 50 pF ................................................... 7
6.11 Operating Characteristics........................................ 7
6.12 Typical Characteristics ............................................ 8
7
Detailed Description ............................................ 11
10 Power Supply Recommendations ..................... 15
11 Layout................................................................... 15
11.1 Layout Guidelines ................................................. 15
11.2 Layout Example .................................................... 15
12 Device and Documentation Support ................. 16
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
16
16
16
16
16
16
13 Mechanical, Packaging, and Orderable
Information ........................................................... 16
Parameter Measurement Information .................. 9
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
April 2017
*
Initial release.
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SCES885 – APRIL 2017
5 Pin Configuration and Functions
DCK Package
5-Pin SC70
Top View
D
1
CLK
2
GND
3
5
VCC
4
Q
Pin Functions (1)
PIN
NO.
NAME
I/O
DESCRIPTION
1
D
I
Data input
2
CLK
I
Positive-Edge-Triggered Clock input
3
GND
—
Ground pin
4
Q
O
Inverted output
5
VCC
—
Positive Supply
(1)
See Mechanical, Packaging, and Orderable Information for dimensions
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
UNIT
Supply voltage
–0.5
6.5
V
(2)
VI
Input voltage
–0.5
6.5
V
VO
Voltage applied to any output in the high-impedance or power-off state (2)
–0.5
6.5
V
VO
Voltage applied to any output in the high or low state (2) (3)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
Continuous current through VCC or GND
±100
mA
TJ
Junction temperature
150
°C
Tstg
Storage temperature
150
ºC
(1)
(2)
(3)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
The value of VCC is provided in .
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002
(1)
Charged-device model (CDM), per AEC Q100-011
±4000
±1000
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VCC
Operating
Supply voltage
Data retention only
1.65
5.5
VCC = 3 V to 3.6 V
V
2
0.7 × VCC
VCC = 1.65 V to 1.95 V
Low-level input voltage
V
1.7
VCC = 4.5 V to 5.5 V
VIL
UNIT
0.65 × VCC
VCC = 2.3 V to 2.7 V
High-level input voltage
MAX
1.5
VCC = 1.65 V to 1.95 V
VIH
MIN
0.35 × VCC
VCC = 2.3 V to 2.7 V
0.7
VCC = 3 V to 3.6 V
0.8
VCC = 4.5 V to 5.5 V
V
0.3 × VCC
VI
Input voltage
0
5.5
V
VO
Output voltage
0
VCC
V
IOH
High-level output current
VCC = 1.65 V
–4
VCC = 2.3 V
–8
–16
VCC = 3 V
VCC = 4.5 V
–32
VCC = 1.65 V
4
VCC = 2.3 V
IOL
Low-level output current
8
16
VCC = 3 V
Δt/Δv
Input transition rise or fall rate
TA
Operating free-air temperature
mA
–24
mA
24
VCC = 4.5 V
32
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V
20
VCC = 3.3 V ± 0.3 V
10
VCC = 5 V ± 0.5 V
ns/V
5
–40
125
°C
6.4 Thermal Information
SN74LVC1G80-Q1
THERMAL METRIC (1)
DCK (SC70)
UNIT
5 PINS
RθJA
Junction-to-ambient thermal resistance
278.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
121.3
°C/W
RθJB
Junction-to-board thermal resistance
65.6
°C/W
ψJT
Junction-to-top characterization parameter
7.5
°C/W
ψJB
Junction-to-board characterization parameter
64.9
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –100 µA
VOH
1.65 V to 5.5 V
1.65 V
1.2
2.3 V
1.9
3V
2.3
IOL = 100 µA
1.65 V to 5.5 V
0.1
IOL = 4 mA
1.65 V
0.45
IOL = 8 mA
2.3 V
0.3
3.8
0.4
3V
IOL = 32 mA
VI = 5.5 V or GND
Ioff
VI or VO = 5.5 V
ICC
VI = 5.5 V or GND,
ΔICC
One input at VCC – 0.6 V,
Other inputs at VCC or GND
Ci
VI = VCC or GND
IO = 0
TA = –40°C to 85°C
UNIT
V
2.4
4.5 V
IOL = 24 mA
(1)
MAX
IOH = –32 mA
IOL = 16 mA
CLK or D inputs
TYP (1)
VCC – 0.1
IOH = –8 mA
IOH = –24 mA
II
MIN
IOH = –4 mA
IOH = –16 mA
VOL
VCC
V
0.55
4.5 V
0.55
0 to 5.5 V
±10
µA
0
±10
µA
1.65 V to 5.5 V
10
µA
3 V to 5.5 V
500
µA
3.3 V
3.5
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
6.6 Timing Requirements: TA = –40°C to +85°C
over recommended operating free-air temperature range, TA = –40°C to +85°C (unless otherwise noted) (see Figure 3)
VCC
MIN
MAX
UNIT
160
MHz
VCC = 1.8 V ± 0.15 V
fclock
VCC = 2.5 V ± 0.2 V
Clock frequency
VCC = 3.3 V ± 0.3 V
VCC = 5.5 V ± 0.5 V
VCC = 1.8 V ± 0.15 V
tw
VCC = 2.5 V ± 0.2 V
Pulse duration, CLK high or low
VCC = 3.3 V ± 0.3 V
2.5
ns
VCC = 5.5 V ± 0.5 V
Data high
tsu
Setup time before CLK↑
Data low
th
Hold time, data after CLK↑
VCC = 1.8 V ± 0.15 V
2.3
VCC = 2.5 V ± 0.2 V
1.5
VCC = 3.3 V ± 0.3 V
1.3
VCC = 5.5 V ± 0.5 V
1.1
VCC = 1.8 V ± 0.15 V
2.5
VCC = 2.5 V ± 0.2 V
1.5
VCC = 3.3 V ± 0.3 V
1.3
VCC = 5.5 V ± 0.5 V
1.1
VCC = 1.8 V ± 0.15 V
0
VCC = 2.5 V ± 0.2 V
0.2
VCC = 3.3 V ± 0.3 V
0.9
VCC = 5.5 V ± 0.5 V
0.4
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ns
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6.7 Timing Requirements: TA = –40°C to +125°C
over recommended operating free-air temperature range, TA = –40°C to +125°C (unless otherwise noted) (see Figure 3)
VCC
MIN
MAX
UNIT
160
MHz
VCC = 1.8 V ± 0.15 V
fclock
VCC = 2.5 V ± 0.2 V
Clock frequency
VCC = 3.3 V ± 0.3 V
VCC = 5.5 V ± 0.5 V
VCC = 1.8 V ± 0.15 V
tw
VCC = 2.5 V ± 0.2 V
Pulse duration, CLK high or low
VCC = 3.3 V ± 0.3 V
2.5
ns
VCC = 5.5 V ± 0.5 V
Data high
tsu
Setup time before CLK↑
Data low
th
Hold time, data after CLK↑
VCC = 1.8 V ± 0.15 V
2.3
VCC = 2.5 V ± 0.2 V
1.5
VCC = 3.3 V ± 0.3 V
1.3
VCC = 5.5 V ± 0.5 V
1.1
VCC = 1.8 V ± 0.15 V
2.5
VCC = 2.5 V ± 0.2 V
1.5
VCC = 3.3 V ± 0.3 V
1.3
VCC = 5.5 V ± 0.5 V
1.1
VCC = 1.8 V ± 0.15 V
0
VCC = 2.5 V ± 0.2 V
0.2
VCC = 3.3 V ± 0.3 V
0.9
VCC = 5.5 V ± 0.5 V
0.4
ns
ns
6.8 Switching Characteristics: TA = –40°C to +85°C, CL = 15 pF
over recommended operating free-air temperature range, TA = –40°C to +85°C, CL = 15 pF (unless otherwise noted) (see
Figure 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
MIN
MAX
UNIT
VCC = 1.8 V ± 0.15 V
VCC = 2.5 V ± 0.2 V
fmax
VCC = 3.3 V ± 0.3 V
160
MHz
VCC = 5 V ± 0.5 V
tpd
CLK
Q
VCC = 1.8 V ± 0.15 V
3
VCC = 2.5 V ± 0.2 V
1.5
9.1
6
VCC = 3.3 V ± 0.3 V
1.3
4.2
VCC = 5 V ± 0.5 V
1.1
3.8
ns
6.9 Switching Characteristics: TA = –40°C to +85°C, CL = 30 pF or 50 pF
over recommended operating free-air temperature range, TA = –40°C to +85°C, CL = 30 pF or 50 pF (unless otherwise noted)
(see Figure 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
MIN
MAX
UNIT
VCC = 1.8 V ± 0.15 V
VCC = 2.5 V ± 0.2 V
fmax
VCC = 3.3 V ± 0.3 V
160
MHz
VCC = 5 V ± 0.5 V
tpd
6
CLK
Q
VCC = 1.8 V ± 0.15 V
4.4
VCC = 2.5 V ± 0.2 V
2.3
7
VCC = 3.3 V ± 0.3 V
2
5.2
VCC = 5 V ± 0.5 V
1.3
4.5
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9.9
ns
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6.10 Switching Characteristics: TA = –40°C to +125°C, CL = 30 pF or 50 pF
over recommended operating free-air temperature range, TA = –40°C to +125°C, CL = 30 pF or 50 pF (unless otherwise
noted) (see Figure 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
MIN
MAX
UNIT
VCC = 1.8 V ± 0.15 V
VCC = 2.5 V ± 0.2 V
fmax
VCC = 3.3 V ± 0.3 V
160
MHz
VCC = 5 V ± 0.5 V
tpd
CLK
Q
VCC = 1.8 V ± 0.15 V
4.4
12.5
VCC = 2.5 V ± 0.2 V
2.3
8.5
VCC = 3.3 V ± 0.3 V
2
6
VCC = 5 V ± 0.5 V
1.3
5.5
ns
6.11 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
f = 10 MHz
VCC
TYP
VCC = 1.8 V
24
VCC = 2.5 V
24
VCC = 3.3 V
25
VCC = 5 V
27
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UNIT
pF
7
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SCES885 – APRIL 2017
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6.12 Typical Characteristics
This plot shows the different ICC values for various voltages on the data input (D). Voltage sweep on the input is from 0 V to
6.5 V.
20
2
VCC = 1.8 V
VCC = 2.5 V
1.6
1.4
1.2
1
0.8
0.6
16
14
12
10
8
6
0.4
4
0.2
2
0
0
0
0.5
1
VCC = 1.8 V
1.5
2 2.5 3 3.5 4 4.5
Data (D) Input Voltage [V]
5
5.5
6
6.5
VCC = 2.5 V
0
0.5
1
VCC = 3.3 V
Figure 1. Supply Current (ICC) vs Data (D) Input Voltage
8
VCC = 3.3 V
VCC = 5.0 V
18
Supply Current ICC [mA]
Supply Current ICC [mA]
1.8
1.5
2 2.5 3 3.5 4 4.5
Data (D) Input Voltage [V]
5
5.5
6
6.5
VCC = 5 V
Figure 2. Supply Current (ICC) vs Data (D) Input Voltage
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7 Parameter Measurement Information
VLOAD
S1
RL
From Output
Under Test
Open
GND
CL
(see Note A)
RL
TEST
S1
tPLH/tPHL
Open
tPLZ/tPZL
VLOAD
tPHZ/tPZH
GND
LOAD CIRCUIT
INPUTS
VCC
VM
VLOAD
CL
RL
VD
£2 ns
VCC/2
2 × VCC
15 pF
1 MW
0.15 V
£2 ns
VCC/2
2 × VCC
15 pF
1 MW
0.15 V
3V
£2.5 ns
1.5 V
6V
15 pF
1 MW
0.3 V
VCC
£2.5 ns
VCC/2
2 × VCC
15 pF
1 MW
0.3 V
VI
tr/tf
1.8 V ± 0.15 V
VCC
2.5 V ± 0.2 V
VCC
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
Timing Input
VM
0V
tW
tsu
VI
Input
th
VI
VM
VM
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VM
VOL
tPHL
0V
VLOAD/2
VM
tPZH
VOH
VM
VOL
VOL + VD
VOL
tPHZ
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
NOTES:
tPLZ
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
VM
VM
tPZL
VOH
Output
VM
tPHL
VM
Output
VI
Output
Control
VOH – VD
VOH
VM
»0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
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Parameter Measurement Information (continued)
VLOAD
S1
RL
From Output
Under Test
Open
GND
CL
(see Note A)
RL
TEST
S1
tPLH/tPHL
Open
tPLZ/tPZL
VLOAD
tPHZ/tPZH
GND
LOAD CIRCUIT
INPUTS
VCC
VM
VLOAD
CL
£2 ns
VCC/2
2 × VCC
£2 ns
VCC/2
2 × VCC
3V
£2.5 ns
1.5 V
VCC
£2.5 ns
VCC/2
VI
tr/tf
1.8 V ± 0.15 V
VCC
2.5 V ± 0.2 V
VCC
3.3 V ± 0.3 V
5 V ± 0.5 V
RL
VD
30 pF
1 kW
0.15 V
30 pF
500 W
0.15 V
6V
50 pF
500 W
0.3 V
2 × VCC
50 pF
500 W
0.3 V
VI
Timing Input
VM
0V
tW
tsu
VI
Input
th
VI
VM
VM
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VM
VOL
tPHL
0V
VLOAD/2
VM
tPZH
VOH
VM
VOL
VOL + VD
VOL
tPHZ
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
NOTES:
tPLZ
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
VM
VM
tPZL
VOH
Output
VM
tPHL
VM
Output
VI
Output
Control
VOH – VD
VOH
VM
»0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 4. Load Circuit and Voltage Waveforms
10
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8 Detailed Description
8.1 Overview
The SN74LVC1G80-Q1 is a single positive-edge-trigger D-type flip-flop and is AEC-Q100 qualified for automotive
applications. Data at the input (D) is transferred to the output (Q) on the positive-going edge of the clock pulse
when the setup time requirement is met. Because the clock triggering occurs at a voltage level, it is not directly
related to the rise time of the clock pulse. This allows for data at the input to be changed without affecting the
level at the output, following the hold-time interval.
8.2 Functional Block Diagram
CLK
2
C
C
C
4
TG
C
C
Q
C
C
D
1
TG
TG
TG
C
C
C
Copyright © 2017, Texas Instruments Incorporated
Figure 5. Logic Diagram (Positive Logic)
8.3 Feature Description
8.3.1 Balanced High-Drive CMOS Push-Pull Outputs
A balanced output allows the device to sink and source similar currents. The high drive capability of this device
creates fast edges into light loads so routing and load conditions should be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. It is important for the power output of the device to be limited to avoid thermal runaway and
damage due to over-current. The electrical and thermal limits defined the in the Absolute Maximum Ratings must
be followed at all times.
8.3.2 Standard CMOS Inputs
Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input
capacitance given in the Electrical Characteristics. The worst case resistance is calculated with the maximum
input voltage, given in the Recommended Operating Conditions, and the maximum input leakage current, given
in the Electrical Characteristics, using ohm's law (R = V ÷ I).
Signals applied to the inputs need to have fast edge rates, as defined by Δt/Δv in Recommended Operating
Conditions to avoid excessive currents and oscillations. If tolerance to a slow or noisy input signal is required, a
device with a Schmitt-trigger input should be utilized to condition the input signal prior to the standard CMOS
input.
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Feature Description (continued)
8.3.3 Clamp Diodes
The inputs and outputs to this device have negative clamping diodes.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can
cause damage to the device. The input negative-voltage and output voltage ratings
may be exceeded if the input and output clamp-current ratings are observed.
VCC
Device
Logic
Input
Output
-IIK
-IOK
GND
Figure 6. Electrical Placement of Clamping Diodes for Each Input and Output
8.3.4 Partial Power Down (Ioff)
The inputs and outputs for this device enter a high impedance state when the supply voltage is 0 V. The
maximum leakage into or out of any input or output pin on the device is specified by Ioff in the Electrical
Characteristics.
8.3.5 Over-Voltage Tolerant Inputs
Input signals to this device can be driven above the supply voltage so long as they remain below the maximum
input voltage value specified in the Absolute Maximum Ratings .
8.4 Device Functional Modes
Table 1 lists the functional modes of the SN74LVC1G80-Q1.
Table 1. Function Table
INPUTS
12
CLK
D
OUTPUT
Q
↑
H
L
↑
L
H
L
X
Q0
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
A useful application for the SN74LVC1G80-Q1 is using it as a frequency divider. By feeding back the output (Q)
to the input (D), the output will toggle on every rising edge of the clock waveform. The output goes HIGH once
every two clock cycles so essentially the frequency of the clock signal is divided by a factor of two. The
SN74LVC1G80-Q1 does not have preset or clear functions so the initial state of the output is unknown. This
application implements the use of a microcontroller GPIO pin to initially set the input HIGH, so the output LOW.
Initialization is not needed, but should be kept in mind. Post initialization, the GPIO pin is set to a high
impedance mode. Depending on the microcontroller, the GPIO pin could be set to an input and used to monitor
the clock division.
9.2 Typical Application
10 k
VCC
GPIO Output
5
1 D
MCU
SN74LVC1G80
CLK
2 CLK
Q
4
CLK/2
3
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Figure 7. Clock Frequency Division
9.2.1 Design Requirements
For this application, a resistor needs to be placed on the feedback line in order for the initialization voltage from
the microcontroller to overpower the signal coming from the output (Q). Without it the state at the input would be
challenged by the GPIO from the microcontroller and from the output of the SN74LVC1G80-Q1.
The SN74LVC1G80-Q1 device uses CMOS technology and has balanced output drive. Take care to avoid bus
contention because it can drive currents that would exceed maximum limits.
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Typical Application (continued)
9.2.2 Detailed Design Procedure
1. Recommended input conditions:
– For rise time and fall time specifications, see Δt/Δv in Recommended Operating Conditions.
– For specified high and low levels, see VIH and VIL in Recommended Operating Conditions.
– Input voltages are recommended to not go below 0 V and not exceed 5.5 V for any VCC. See
Recommended Operating Conditions.
2. Recommended output conditions:
– Load currents should not exceed ±50 mA. See Absolute Maximum Ratings .
– Output voltages are recommended to not go below 0 V and not exceed the VCC voltage. See
Recommended Operating Conditions.
3. Feedback resistor:
– A 10-kΩ resistor is chosen here to bias the input so the microcontroller GPIO output can initialize the
input and output. The resistor value is important because a resistance too high, say at 1 MΩ, would
cause too much of a voltage drop, causing the output to no longer be able to drive the input. On the other
hand, a resistor too low, such as a 1 Ω, would not bias enough and might cause current to flow into the
microcontroller, possibly damaging the device.
9.2.3 Application Curve
Figure 8. Frequency Division
14
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10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating listed in
Recommended Operating Conditions. A 0.1-µF bypass capacitor is recommended to be connected from the VCC
terminal to GND to prevent power disturbance. To reject different frequencies of noise, use multiple bypass
capacitors in parallel. Capacitors with values of 0.1 µF and 1 µF are commonly used in parallel. The bypass
capacitor must be installed as close to the power terminal as possible for best results.
11 Layout
11.1 Layout Guidelines
When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of
the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This
increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance
of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must
turn corners. Figure 9 shows progressively better techniques of rounding corners. Only the last example (BEST)
maintains constant trace width and minimizes reflections.
11.2 Layout Example
BETTER
BEST
2W
WORST
1W min.
W
Figure 9. Trace Example
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
Implications of Slow or Floating CMOS Inputs, SCBA004.
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
16
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN74LVC1G80QDCKRQ1
ACTIVE
SC70
DCK
5
3000
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
17U
SN74LVC1G80QDCKTQ1
ACTIVE
SC70
DCK
5
250
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
17U
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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