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SN74LVC1G66-Q1
SCES499E – JUNE 2001 – REVISED APRIL 2015
SN74LVC1G66-Q1 Single Bilateral Analog Switch
1 Features
3 Description
•
•
This single analog switch is designed for 1.65-V to
5.5-V VCC operation.
1
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature Range
– Device HBM Classification Level H2
– Device CDM Classification Level C5
– Device MM Classification Level M3
1.65-V to 5.5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Max tpd of 0.8 ns at 3.3 V
High On-Off Output Voltage Ratio
High Degree of Linearity
High Speed, Typically 0.5 ns (VCC = 3 V,
CL = 50 pF)
Low ON-State Resistance, Typically ≉5.5 Ω
(VCC = 4.5 V)
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
The SN74LVC1G66-Q1 device supports analog and
digital signals. The device permits bidirectional
transmission of signals with amplitudes of up to 5.5 V
(peak).
Device Information(1)
PART NUMBER
SN74LVC1G66-Q1
PACKAGE
BODY SIZE (NOM)
SOT-23 (5)
2.90 mm × 1.60 mm
SC70 (5)
1.60 mm × 1.20 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Logic Diagram (Positive Logic)
1
A
2
B
4
C
2 Applications
•
•
•
•
•
•
•
Infotainment Systems
Wireless Devices
Audio and Video Signal Routing
Portable Computing
Wearable Devices
Signal Gating, Chopping, Modulation or
Demodulation (Modem)
Signal Multiplexing for Analog-to-Digital and
Digital-to-Analog Conversion Systems
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC1G66-Q1
SCES499E – JUNE 2001 – REVISED APRIL 2015
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Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
4
4
4
5
5
5
6
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Analog Switch Characteristics ..................................
Operating Characteristics..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 8
Detailed Description ............................................ 12
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
12
12
12
12
Application and Implementation ........................ 13
9.1 Application Information............................................ 13
9.2 Typical Application ................................................. 13
10 Power Supply Recommendations ..................... 14
11 Layout................................................................... 14
11.1 Layout Guidelines ................................................. 14
11.2 Layout Example .................................................... 15
12 Device and Documentation Support ................. 15
12.1
12.2
12.3
12.4
Documentation Support ........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
15
15
15
15
13 Mechanical, Packaging, and Orderable
Information ........................................................... 15
4 Revision History
Changes from Revision D (January 2008) to Revision E
•
2
Page
Added Device Information and ESD Ratings tables and the following sections: Pin Configurations and Functions,
Detailed Description, Application and Implementation, Power Supply Recommendations, Layout, Device and
Documentation Support, and Mechanical, Packaging, and Orderable Information................................................................ 1
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5 Pin Configuration and Functions
DBV and DCK Packages
5-Pin SOT-23 and SC70
Top View
A
1
B
2
GND
3
5
VCC
4
C
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
A
1
I/O
Bidirectional signal to be switched
B
2
I/O
Bidirectional signal to be switched
C
4
I
GND
3
—
Ground pin
VCC
5
—
Power pin
Controls the switch (L = OFF, H = ON)
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
UNIT
Supply voltage (2)
–0.5
6.5
V
(2) (3)
–0.5
6.5
V
–0.5
VCC + 0.5
V
VI
Input voltage
VI/O
Switch I/O voltage (2) (3) (4)
IIK
Control input clamp current
VI < 0
–50
mA
IIOK
I/O port diode current
VI/O < 0
–50
mA
IT
ON-state switch current
VI/O < 0 to VCC
±50
mA
±100
mA
150
°C
Continuous current through VCC or GND
Tstg
(1)
(2)
(3)
(4)
Storage temperature
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to ground, unless otherwise specified.
The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
This value is limited to 5.5 V maximum.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
2000
Charged-device model (CDM), per AEC Q100-011
1000
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
VCC
Supply voltage
1.65
5.5
V
VI/O
I/O port voltage
0
VCC
V
VCC = 1.65 V to 1.95 V
VIH
High-level input voltage, control input
VCC × 0.65
VCC = 2.3 V to 2.7 V
VCC × 0.7
VCC = 3 V to 3.6 V
VCC × 0.7
VCC = 4.5 V to 5.5 V
VCC × 0.7
VCC = 1.65 V to 1.95 V
VIL
VI
Low-level input voltage, control input
VCC × 0.35
VCC = 2.3 V to 2.7 V
VCC × 0.3
VCC = 3 V to 3.6 V
VCC × 0.3
VCC = 4.5 V to 5.5 V
VCC × 0.3
Control input voltage
Δt/Δv Input transition rise and fall time
0
20
VCC = 2.3 V to 2.7 V
20
VCC = 3 V to 3.6 V
10
(1)
4
Operating free-air temperature
V
5.5
VCC = 1.65 V to 1.95 V
VCC = 4.5 V to 5.5 V
TA
V
V
ns/V
10
–40
125
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, SCBA004.
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6.4 Thermal Information
SN74LVC1G66-Q1
THERMAL METRIC (1)
RθJA
(1)
DBV (SOT-23)
DCK (SC70)
5 PINS
5 PINS
206
252
Junction-to-ambient thermal resistance
UNIT
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
ron
ON-state switch resistance
TEST CONDITIONS
VI = VCC or GND,
VC = VIH
(see Figure 2 and
Figure 1)
VCC
MIN TYP (1)
MAX
IS = 4 mA
1.65 V
12
35
IS = 8 mA
2.3 V
9
30
IS = 16 mA
3V
9
30
IS = 16 mA
4.5 V
5.5
25
IS = 4 mA
1.65 V
74.5
165
IS = 8 mA
2.3 V
20
60
IS = 16 mA
3V
12.5
35
IS = 16 mA
4.5 V
7.5
25
UNIT
Ω
Peak on resistance
VI = VCC or GND,
VC = VIH
(see Figure 2 and
Figure 1)
IS(off)
OFF-state switch leakage current
VI = VCC and VO = GND or
VI = GND and VO = VCC,
VC = VIL (see Figure 3)
5.5 V
IS(on)
ON-state switch leakage current
VI = VCC or GND, VC = VIH, VO = Open
(see Figure 4)
5.5 V
II
Control input current
VC = VCC or GND
5.5 V
ICC
Supply current
VC = VCC or GND
5.5 V
ΔICC
Supply current change
VC = VCC – 0.6 V
5.5 V
Cic
Control input capacitance
5V
2
pF
Cio(off)
Switch input and output capacitance
5V
6
pF
Cio(on)
Switch input and output capacitance
5V
13
pF
ron(p)
(1)
Ω
±1
±0.1 (1)
±1
±0.1 (1)
±1
±0.1 (1)
10
1 (1)
500
μA
μA
μA
μA
μA
TA = 25°C
6.6 Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 5)
PARAMETER
tpd (1)
Propagation delay
FROM
(INPUT)
TO
(OUTPUT)
A or B
B or A
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V
± 0.15 V
± 0.2 V
± 0.3 V
VCC = 5 V
± 0.5 V
UNIT
MIN MAX
MIN MAX
MIN MAX
MIN MAX
5.5
3.2
2.8
2.6
ns
(2)
Enable time
C
A or B
2.5
14
1.9
9.5
1.8
8
1.5
7.2
ns
tdis (3)
Disable time
C
A or B
2.2
12
1.4
8.9
2
8.4
1.4
6.9
ns
ten
(1)
(2)
(3)
tPLH and tPHL are the same as tpd. The propagation delay is the calculated RC time constant of the typical ON-state resistance of the
switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
tPZL and tPZH are the same as ten.
tPLZ and tPHZ are the same as tdis.
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6.7 Analog Switch Characteristics
TA = 25°C
FROM
(INPUT)
PARAMETER
TO
(OUTPUT)
TEST
CONDITIONS
VCC
CL = 50 pF, RL = 600 Ω,
fin = sine wave
(see Figure 6)
Frequency response
(switch ON)
(1)
A or B
B or A
CL = 5 pF, RL = 50 Ω,
fin = sine wave
(see Figure 6)
Crosstalk
(control input to signal output)
C
A or B
CL = 50 pF, RL = 600 Ω,
fin = 1 MHz (square wave)
(see Figure 7)
CL = 50 pF, RL = 600 Ω,
fin = 1 MHz (sine wave)
(see Figure 8)
Feedthrough attenuation
(switch OFF)
(2)
A or B
B or A
CL = 5 pF, RL = 50 Ω,
fin = 1 MHz (sine wave)
(see Figure 8)
CL = 50 pF, RL = 10 kΩ,
fin = 1 kHz (sine wave)
(see Figure 9)
Sine-wave distortion
A or B
B or A
CL = 50 pF, RL = 10 kΩ,
fin = 10 kHz (sine wave)
(see Figure 9)
(1)
(2)
TYP
1.65 V
35
2.3 V
120
3V
175
4.5 V
195
1.65 V
>300
2.3 V
>300
3V
>300
4.5 V
>300
1.65 V
35
2.3 V
50
3V
70
4.5 V
100
1.65 V
–58
2.3 V
–58
3V
–58
4.5 V
–58
1.65 V
–42
2.3 V
–42
3V
–42
4.5 V
–42
1.65 V
0.1%
2.3 V
0.025%
3V
0.015%
4.5 V
0.01%
1.65 V
0.15%
2.3 V
0.025%
3V
0.015%
4.5 V
0.01%
UNIT
MHz
mV
dB
Adjust fin voltage to obtain 0 dBm at output. Increase fin frequency until dB meter reads –3 dB.
Adjust fin voltage to obtain 0 dBm at input.
6.8 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
6
Power dissipation capacitance
TEST
CONDITIONS
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
VCC = 5 V
TYP
TYP
TYP
TYP
f = 10 MHz
8
9
9
11
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UNIT
pF
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6.9 Typical Characteristics
TA = 25°C
100
VCC = 1.65 V
r on − Ω
VCC = 2.3 V
VCC = 3.0 V
10
1
0.0
VCC = 4.5 V
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
VIN − V
Figure 1. Typical ron as a Function of Input Voltage (VI) for VI = 0 to VCC
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7 Parameter Measurement Information
VCC
VCC
B or A
A or B
VI = VCC or GND
VIH
VO
C
VC
(ON)
GND
IS
r on +
V
VI * VO
W
IS
VI − VO
Figure 2. ON-State Resistance Test Circuit
VCC
VCC
VI
B or A
A or B
A
VIL
VO
C
VC
(OFF)
GND
Condition 1: VI = GND, VO = VCC
Condition 2: VI = VCC, VO = GND
Figure 3. OFF-State Switch Leakage-Current Test Circuit
VCC
VCC
VI = VCC or GND
A
B or A
A or B
VO
VO = Open
VIH
C
VC
(ON)
GND
Figure 4. ON-State Switch Leakage-Current Test Circuit
8
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Parameter Measurement Information (continued)
VLOAD
S1
RL
From Output
Under Test
CL
(see Note A)
Open
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
VCC
VCC
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
VCC/2
VCC/2
2 × VCC
2 × VCC
2 × VCC
2 × VCC
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VI
VM
Input
VM
0V
VOH
VM
Output
VM
VOL
VM
0V
VLOAD/2
VM
tPZH
VOH
Output
VM
tPLZ
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPHL
VM
tPZL
tPHL
tPLH
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOL + V∆
VOL
tPHZ
Output
Waveform 2
S1 at GND
(see Note B)
VM
VOH − V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 5. Load Circuit and Voltage Waveforms
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Parameter Measurement Information (continued)
VCC
VCC
0.1 µF
fin
50 Ω
B or A
A or B
C
VC
VIH
VO
RL
(ON)
GND
CL
VCC/2
RL/CL: 600 Ω/50 pF
RL/CL: 50 Ω/5 pF
Figure 6. Frequency Response (Switch ON)
VCC
VCC
Rin
600 Ω
A or B
VCC/2
B or A
VO
RL
600 Ω
C
VC
GND
50 Ω
CL
50 pF
VCC/2
Figure 7. Crosstalk (Control Input – Switch Output)
10
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Parameter Measurement Information (continued)
VCC
VCC
0.1 µF
50 Ω
fin
B or A
A or B
RL
VO
C
VC
VIL
CL
RL
(OFF)
GND
VCC/2
VCC/2
RL/CL: 600 Ω/50 pF
RL/CL: 50 Ω/5 pF
Figure 8. Feedthrough (Switch OFF)
VCC
VCC
10 µF
fin
600 Ω
VIH
10 µF
B or A
A or B
VO
RL
10 kΩ
C
VC
(ON)
GND
CL
50 pF
VCC/2
VCC = 1.65 V, VI = 1.4 VP-P
VCC = 2.3 V, VI = 2 VP-P
VCC = 3 V, VI = 2.5 VP-P
VCC = 4.5 V, VI = 4 VP-P
Figure 9. Sine-Wave Distortion
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8 Detailed Description
8.1 Overview
This single analog switch is designed for 1.65-V to 5.5-V VCC operation in automotive applications.
The SN74LVC1G66-Q1 device supports analog and digital signals. The device permits bidirectional transmission
of signals with amplitudes of up to 5.5 V (peak). Like all analog switches, the SN74LVC1G66-Q1 is bidirectional.
8.2 Functional Block Diagram
1
2
A
B
4
C
Figure 10. Logic Diagram (Positive Logic)
8.3 Feature Description
This device is tested for operation in automotive applications. The SN74LVC1G66-Q1 has a wide VCC range,
allowing rail-to-rail operation of signals anywhere from a 1.8-V system to a 5-V system. In addition, the control
input (C Pin) is 5.5-V tolerant, allowing higher-voltage logic to interface to the switch control system.
8.4 Device Functional Modes
Table 1. Function Table
12
CONTROL INPUT (C)
SWITCH
L
OFF
H
ON
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74LVC1G66-Q1 device can be used in any situation where an SPST switch would be used and a solidstate, voltage-controlled version is preferred.
9.2 Typical Application
2.5 V
C
or
System Logic
C
VCC
A
B
GND
To/From
System
Figure 11. Typical Application Schematic
9.2.1 Design Requirements
The SN74LVC1G66-Q1 device allows on and off control of analog and digital signals with a digital control signal.
All input signals must be between 0 V and VCC for optimal operation.
9.2.2 Detailed Design Procedure
1. Recommended input conditions:
– For rise time and fall time specifications, see Δt/Δv in the Recommended Operating Conditions table.
– For specified high and low levels, see VIH and VIL in the Recommended Operating Conditions table.
– Inputs and outputs are overvoltage tolerant and can therefore go as high as 5.5 V at any valid VCC.
2. Recommended output conditions:
– Load currents should not exceed ±50 mA.
3. Frequency selection criterion:
– Maximum frequency tested is 150 MHz.
– Added trace resistance and capacitance can reduce maximum frequency capability; follow the layout
practices listed in the Layout section.
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Typical Application (continued)
9.2.3 Application Curve
20
15
ron
85°C
10
25°C
−40°C
5
0
0
1
2
3
VI
Figure 12. ron vs VI, VCC = 2.5 V (SN74LVC1G66-Q1)
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating listed in the
Recommended Operating Conditions table.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, a 0.1-μF bypass capacitor is recommended. If multiple pins are labeled VCC, then a 0.01-μF or 0.022-μF
capacitor is recommended for each VCC because the VCC pins are tied together internally. For devices with dual
supply pins operating at different voltages, for example VCC and VDD, a 0.1-µF bypass capacitor is recommended
for each supply pin. To reject different frequencies of noise, use multiple bypass capacitors in parallel. Capacitors
with values of 0.1 μF and 1 μF are commonly used in parallel. The bypass capacitor should be installed as close
to the power terminal as possible for best results.
11 Layout
11.1 Layout Guidelines
Reflections and matching are closely related to the loop antenna theory but are different enough to be discussed
separately from the theory. When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection
occurs primarily because of the change of width of the trace. At the apex of the turn, the trace width increases to
1.414 times the width. This increase upsets the transmission-line characteristics, especially the distributed
capacitance and self–inductance of the trace which results in the reflection. Not all PCB traces can be straight
and therefore some traces must turn corners. Figure 13 shows progressively better techniques of rounding
corners. Only the last example (BEST) maintains constant trace width and minimizes reflections.
14
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Copyright © 2001–2015, Texas Instruments Incorporated
Product Folder Links: SN74LVC1G66-Q1
SN74LVC1G66-Q1
www.ti.com
SCES499E – JUNE 2001 – REVISED APRIL 2015
11.2 Layout Example
BETTER
BEST
2W
WORST
1W min.
W
Figure 13. Trace Example
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Implications of Slow or Floating CMOS Inputs, SCBA004
• Selecting the Right Texas Instruments Signal Switch, SZZA030
12.2 Trademarks
All trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Copyright © 2001–2015, Texas Instruments Incorporated
Product Folder Links: SN74LVC1G66-Q1
15
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
1P1G66QDBVRG4Q1
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C66R
1P1G66QDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C66R
SN74LVC1G66QDCKRQ1
ACTIVE
SC70
DCK
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C6O
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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