SN74LVC1T45TDCKRQ1

SN74LVC1T45-Q1 SCES677E – SEPTEMBER 2006 – REVISED DECEMBER 2022 SN74LVC1T45-Q1 Automotive 1.65-V to 5.5-V Single-Bit Dual-Supply Level Shifter 1 Features 3 Description • • The SN74LVC1T45-Q1 device is a single-bit, noninverting bus transceiver that uses two separate configurable power supply rails. The A-port is designed to track VCCA. VCCA accepts any supply voltage from 1.65 V to 5.5 V. The B-port is designed to track VCCB. VCCB accepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional translation between any of the 1.8-V, 2.5V, 3.3-V, and 5-V voltage nodes. • • • • • • Qualified for automotive applications AEC-Q100 qualified with the following results: – Device temperature grade 1: –40°C to +125°C ambient operating temperature range – Device HBM ESD Classification Level H2 – Device CDM ESD Classification Level C3B Fully configurable dual-rail design allows each port to operate over the full 1.65-V to 5.5-V powersupply range VCC isolation feature – if either VCC input is at GND, both ports are in the high-impedance state DIR input circuit referenced to VCCA ±24-mA output drive at 3.3 V Ioff supports partial-power-down mode operation Maximum data rates: – 420 Mbps (3.3-V to 5-V translation) – 210 Mbps (translate to 3.3 V) – 140 Mbps (translate to 2.5 V) – 75 Mbps (translate to 1.8 V) 2 Applications • • • Head units ADAS – cameras Telematics The SN74LVC1T45-Q1 device is a single-bit, noninverting level translator. The fully configurable dualrail design allows each port to overate over the full 1.65-V to 5.5-V power supply range. It is ideal for applications that need a wide bidirectional translation range. The SN74LVC1T45-Q1 is designed so that the DIR input is powered by VCCA. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The VCC isolation feature assures that if either VCC input is at GND, then both ports are in the highimpedance state. Package Information(1) PART NUMBER SN74LVC1T45-Q1 (1) DIR A PACKAGE DCK (SC70, 6) BODY SIZE (NOM) 1.25 mm × 2.00 mm For all available packages, see the orderable addendum at the end of the data sheet. 5 3 4 VCCA B VCCB Copyright © 2016, Texas Instruments Incorporated Logic Diagram (Positive Logic) An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN74LVC1T45-Q1 www.ti.com SCES677E – SEPTEMBER 2006 – REVISED DECEMBER 2022 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................3 6 Specifications.................................................................. 4 6.1 Absolute Maximum Ratings........................................ 4 6.2 ESD Ratings............................................................... 4 6.3 Recommended Operating Conditions.........................4 6.4 Thermal Information....................................................5 6.5 Electrical Characteristics.............................................6 6.6 Switching Characteristics: VCCA = 1.8 V ±0.15 V........7 6.7 Switching Characteristics: VCCA = 2.5 V ±0.2 V..........7 6.8 Switching Characteristics: VCCA = 3.3 V ±0.3 V..........8 6.9 Switching Characteristics: VCCA = 5 V ±0.5 V.............8 6.10 Typical Characteristics.............................................. 9 7 Detailed Description......................................................13 7.1 Overview................................................................... 13 7.2 Functional Block Diagram......................................... 13 7.3 Feature Description...................................................13 7.4 Device Functional Modes..........................................13 8 Power Supply Recommendations................................16 9 Layout.............................................................................17 9.1 Layout Guidelines..................................................... 17 9.2 Layout Example........................................................ 17 10 Device and Documentation Support..........................18 10.1 Documentation Support.......................................... 18 10.2 Receiving Notification of Documentation Updates..18 10.3 Support Resources................................................. 18 10.4 Trademarks............................................................. 18 10.5 Electrostatic Discharge Caution..............................18 10.6 Glossary..................................................................18 11 Mechanical, Packaging, and Orderable Information.................................................................... 18 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (July 2017) to Revision E (December 2022) Page • Updated the numbering format for tables, figures, and cross-references throughout the document..................1 • Updated the thermals in the Thermal Information section.................................................................................. 5 • Updated the Switching Characterisitcs sections: extended some minimum specifications for lower delays......7 Changes from Revision C (September 2016) to Revision D (July 2017) Page • Added Junction temperature, TJ in Absolute Maximum Ratings ....................................................................... 4 • Added revised steps for power-up sequence in Power Supply Recommendations ........................................ 16 Changes from Revision B (September 2012) to Revision C (September 2016) Page • Changed data sheet title From: SN74LVC1T45-Q1 Single-Bit Dual-Supply Bus Transceiver With Configurable Voltage Translation and 3-State Outputs To: SN74LVC1T45-Q1 1.65-V to 5.5-V Single-Bit Dual-Supply Level Shifter................................................................................................................................................................. 1 • Added Device Information table, ESD Ratings table, Feature Description section, Device Functional Modes section, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section 1 • Deleted Ordering Information table; see POA the end of the data sheet........................................................... 1 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVC1T45-Q1 SN74LVC1T45-Q1 www.ti.com SCES677E – SEPTEMBER 2006 – REVISED DECEMBER 2022 5 Pin Configuration and Functions VCCA 1 6 VCCB GND 2 5 DIR A 3 4 B Not to scale See mechanical drawings for dimensions. Figure 5-1. DCK Package, 6-Pin SC70 (Top View) Table 5-1. Pin Functions PIN NAME NO. TYPE(1) DESCRIPTION A 3 I/O Output level depends on VCC1 voltage B 4 I/O Input threshold value depends on VCC2 voltage DIR 5 I GND (low level) determines B-port to A-port direction GND 2 G Device GND VCCA 1 P SYSTEM-1 supply voltage (1.65 V to 5.5 V) VCCB 6 P SYSTEM-2 supply voltage (1.65 V to 5.5 V) (1) G = Ground, I = Input, O = Output, P = Power Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVC1T45-Q1 3 SN74LVC1T45-Q1 www.ti.com SCES677E – SEPTEMBER 2006 – REVISED DECEMBER 2022 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT –0.5 6.5 V –0.5 6.5 V –0.5 6.5 V A port –0.5 VCCA + 0.5 B port –0.5 VCCB + 0.5 Supply voltage, VCCA, VCCB Input voltage, VI (2) Voltage applied to any output in the high-impedance or power-off state, VO (2) Voltage applied to any output in the high or low state, VO (2) (3) V Input clamp current, IIK (VI < 0) –50 mA Output clamp current, IOK (VO < 0) –50 mA Continuous output current, IO ±50 mA Continuous current through VCC or GND ±100 mA Junction temperature, TJ 150 °C 150 °C Storage temperature, Tstg (1) (2) (3) –65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. The value of VCC is provided in Recommended Operating Conditions. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) UNIT ±2000 Charged-device model (CDM), per JEDEC specification JESD22-C101(2) V ±750 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions See(1) (2) (3) VCCA Supply voltage VCCB Supply voltage VCCI = 1.65 V to 1.95 V VIH High-level input voltage, data inputs(4) VCCI = 2.3 V to 2.7 V VCCI = 3 V to 3.6 V VCCI = 4.5 V to 5.5 V MIN MAX 1.65 5.5 V 1.65 5.5 V VCCI × 0.65 1.7 Low-level input voltage, data inputs(4) VCCI × 0.7 VCCI × 0.35 VCCI = 2.3 V to 2.7 V 0.7 VCCI = 3 V to 3.6 V 0.8 VCCI = 4.5 V to 5.5 V VCCI = 1.65 V to 1.95 V VIH High-level input voltage, DIR (referenced to VCCA)(5) VCCI = 2.3 V to 2.7 V VCCI = 3 V to 3.6 V VCCI = 4.5 V to 5.5 V 4 V 2 VCCI = 1.65 V to 1.95 V VIL Submit Document Feedback UNIT V VCCI × 0.3 VCCA × 0.65 1.7 2 V VCCA × 0.7 Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVC1T45-Q1 SN74LVC1T45-Q1 www.ti.com SCES677E – SEPTEMBER 2006 – REVISED DECEMBER 2022 6.3 Recommended Operating Conditions (continued) See(1) (2) (3) MIN VCCI = 1.65 V to 1.95 V VIL Low-level input voltage, DIR (referenced to VCCA)(5) VI Input voltage VO Output voltage MAX VCCI = 2.3 V to 2.7 V 0.7 VCCI = 3 V to 3.6 V 0.8 VCCI = 4.5 V to 5.5 V VCCA × 0.3 5.5 V 0 VCCO V –4 VCCO = 2.3 V to 2.7 V High-level output current –8 VCCO = 3 V to 3.6 V –24 VCCO = 4.5 V to 5.5 V –32 VCCO = 1.65 V to 1.95 V IOL Δt/Δv Input transition rise or fall rate Data inputs 8 VCCO = 3 V to 3.6 V 24 VCCO = 4.5 V to 5.5 V 32 VCCI = 1.65 V to 1.95 V 20 VCCI = 2.3 V to 2.7 V 20 VCCI = 3 V to 3.6 V 10 VCCI = 4.5 V to 5.5 V (1) (2) (3) (4) (5) Operating free-air temperature mA ns/V 5 Control inputs, VCCI = 1.65 V to 5.5 V TA mA 4 VCCO = 2.3 V to 2.7 V Low-level output current V 0 VCCO = 1.65 V to 1.95 V IOH UNIT VCCA × 0.35 5 –40 125 °C VCCI is the VCC associated with the input port. VCCO is the VCC associated with the output port. All unused data inputs of the device must be held at VCCI or GND to assure proper device operation. See Implications of Slow or Floating CMOS Inputs (SCBA004). For VCCI values not specified in the data sheet, VIH min = VCCI × 0.7 V, VIL max = VCCI × 0.3 V. For VCCI values not specified in the data sheet, VIH min = VCCA × 0.7 V, VIL max = VCCA × 0.3 V. 6.4 Thermal Information SN74LVC1T45-Q1 THERMAL METRIC(1) DCK (SC70) UNIT 6 PINS RθJA Junction-to-ambient thermal resistance 210.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 139.2 °C/W RθJB Junction-to-board thermal resistance 72 °C/W ψJT Junction-to-top characterization parameter 54.9 °C/W ψJB Junction-to-board characterization parameter 71.7 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance — °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVC1T45-Q1 5 SN74LVC1T45-Q1 www.ti.com SCES677E – SEPTEMBER 2006 – REVISED DECEMBER 2022 6.5 Electrical Characteristics over operating free-air temperature range with all limits at TA = –40°C to 125°C (unless otherwise noted)(1) (2) PARAMETER TEST CONDITIONS MIN IOH = –100 µA, VCCA = 1.65 V to 4.5 V, VCCB = 1.65 V to 4.5 V VOH VI = VIH TYP VI = VIL IOH = –4 mA, VCCA = 1.65 V, VCCB = 1.65 V 1.2 IOH = –8 mA, VCCA = 2.3 V, VCCB = 2.3 V 1.9 IOH = –24 mA, VCCA = 3 V, VCCB = 3 V 2.3 IOH = –32 mA, VCCA = 4.5 V, VCCB = 4.5 V 3.8 V Ioff VI or VO = 0 to 5.5 V 0.45 IOL = 8 mA, VCCA = 2.3 V, VCCB = 2.3 V 0.4 IOL = 24 mA, VCCA = 3 V, VCCB = 3 V 0.65 IOL = 32 mA, VCCA = 4.5 V, VCCB = 4.5 V 0.65 TA = 25°C ±1 TA = –40°C to 125°C ±4 A port at VCCA = 0 V, VCCB = 0 to 5.5 V TA = 25°C ±1 B port at VCCA = 0 to 5.5 V, VCCB = 0 V TA = 25°C A or B port at VO = VCCO or GND, VCCA = 1.65 V to 5.5 V, VCCB = 1.65 V to 5.5 V IOZ 0.1 IOL = 4 mA, VCCA = 1.65 V, VCCB = 1.65 V DIR at VI = VCCA or GND, VCCA = 1.65 V to 5.5 V, VCCB = 1.65 V to 5.5 V II TA = –40°C to 125°C ±10 ±1 TA = –40°C to 125°C VI = VCCI or GND, IO = 0 ±1 TA = –40°C to 125°C ±10 4 VCCA = 0 V, VCCB = 5.5 V –10 VCCA = 1.65 V to 5.5 V, VCCB = 1.65 V to 5.5 V VI = VCCI or GND, IO = 0 ICCA + ICCB VI = VCCI or GND, IO = 0, VCCA = 1.65 V to 5.5 V, VCCB = 1.65 V to 5.5 V ΔICCA VCCA = 3 V to 5.5 V, VCCB = 3 V to 5.5 V –10 VCCA = 0 V, VCCB = 5.5 V 4 A port at VCCA – 0.6 V, DIR at VCCA, B port = open 50 DIR at VCCA – 0.6 V, B port = open, A port at VCCA or GND 50 Ci DIR at VI = VCCA or GND, TA = 25°C, VCCA = 3.3 V, VCCB = 3.3 V Cio A or B port at VO = VCCA/B or GND, TA = 25°C, VCCA = 3.3 V, VCCB = 3.3 V A-port input, B-port output CpdA (3) CL = 0 pF, f = 10 MHz, tr = tf = 1 ns B-port input, A-port output 6 20 B port at VCCB – 0.6 V, DIR at GND, A port = open, VCCA = 3 V to 5.5 V, VCCB = 3 V to 5.5 V µA µA µA µA µA 50 µA 2.5 pF 6 pF VCCA = VCCB = 1.8 V 3 VCCA = VCCB = 2.5 V 4 VCCA = VCCB = 3.3 V 4 VCCA = VCCB = 5 V 4 VCCA = VCCB = 1.8 V 18 VCCA = VCCB = 2.5 V 19 VCCA = VCCB = 3.3 V 20 VCCA = VCCB = 5 V 21 Submit Document Feedback µA 10 VCCA = 5.5 V, VCCB = 0 V ΔICCB µA 10 VCCA = 5.5 V, VCCB = 0 V ICCB V ±10 TA = 25°C VCCA = 1.65 V to 5.5 V, VCCB = 1.65 V to 5.5 V ICCA UNIT VCCO – 0.1 IOL = 100 µA, VCCA = 1.65 V to 4.5 V, VCCB = 1.65 V to 4.5 V VOL MAX pF Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVC1T45-Q1 SN74LVC1T45-Q1 www.ti.com SCES677E – SEPTEMBER 2006 – REVISED DECEMBER 2022 6.5 Electrical Characteristics (continued) over operating free-air temperature range with all limits at TA = –40°C to 125°C (unless otherwise noted)(1) (2) PARAMETER TEST CONDITIONS MIN A-port input, B-port output CL = 0 pF, f = 10 MHz, tr = tf = 1 ns CpdB (3) B-port input, A-port output (1) (2) (3) TYP VCCA = VCCB = 1.8 V 18 VCCA = VCCB = 2.5 V 19 VCCA = VCCB = 3.3 V 20 VCCA = VCCB = 5 V 21 VCCA = VCCB = 1.8 V 3 VCCA = VCCB = 2.5 V 4 VCCA = VCCB = 3.3 V 4 VCCA = VCCB = 5 V 4 MAX UNIT pF VCCO is the VCC associated with the output port. VCCI is the VCC associated with the input port. Power dissipation capacitance per transceiver 6.6 Switching Characteristics: VCCA = 1.8 V ±0.15 V over operating free-air temperature range (unless otherwise noted; see Figure 7-1) PARAMETER tPLH tPHL tPLH tPHL tPHZ tPLZ tPHZ tPLZ tPZH (1) tPZL (1) tPZH (1) tPZL (1) (1) FROM (INPUT) TO (OUTPUT) A B B A DIR A DIR B DIR A DIR B VCCB = 1.8 V ±0.15 V VCCB = 2.5 V ±0.2 V VCCB = 3.3 V ±0.3 V VCCB = 5 V ±0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX 3 20.7 2.2 13.3 1.7 11.3 1.4 10.2 2.8 17.3 2.2 11.5 1.8 10.1 1.7 10 3 20.7 2.3 19 2.1 18.5 1.9 18.1 2.8 17.3 2.1 15.9 2 15.6 1.8 15.2 5.2 22.7 4.8 21.5 4.7 21.4 5.1 20.1 2.3 13.5 2.1 13.5 2.4 13.7 3.1 13.9 5.2 27.9 4.9 14.5 3.6 13.3 2.3 11.2 4.2 19 2.2 12.2 2.3 11.4 2 9.4 39.7 31.2 29.9 27.5 45.2 30.4 28.9 26.4 34.2 26.8 25 24.1 40.7 33 31.5 30.1 ns ns ns ns ns ns The enable time is a calculated value, derived using the formula shown in Section 8.1.1. 6.7 Switching Characteristics: VCCA = 2.5 V ±0.2 V over operating free-air temperature range (unless otherwise noted; see Figure 7-1) PARAMETER tPLH tPHL tPLH tPHL tPHZ tPLZ tPHZ tPLZ FROM (INPUT) TO (OUTPUT) A B B A DIR A DIR B VCCB = 1.8 V ±0.15 V VCCB = 2.5 V ±0.2 V VCCB = 3.3 V ±0.3 V VCCB = 5 V ±0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX 2.3 19 1.5 11.5 1.3 9.4 1.1 8.1 2.1 15.9 1.4 10.5 1.3 8.4 0.9 7.6 2.2 13.3 1.5 11.5 1.4 11 1 10.5 2.2 11.5 1.4 10.7 1.3 10 0.9 9.2 3 11.1 3.1 11.1 2.8 11.1 3.2 11.1 1.3 8.9 1.3 8.9 1.3 8.9 1 8.8 5.2 26.7 4.1 14.4 3.9 13.2 2.4 10.1 3.9 21.9 3.2 12.6 2.8 11.4 1.8 8.3 ns ns ns ns Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVC1T45-Q1 7 SN74LVC1T45-Q1 www.ti.com SCES677E – SEPTEMBER 2006 – REVISED DECEMBER 2022 6.7 Switching Characteristics: VCCA = 2.5 V ±0.2 V (continued) over operating free-air temperature range (unless otherwise noted; see Figure 7-1) PARAMETER tPZH (1) tPZL (1) tPZH (1) tPZL (1) FROM (INPUT) TO (OUTPUT) DIR A DIR B VCCB = 1.8 V ±0.15 V MIN MAX VCCB = 2.5 V ±0.2 V MIN VCCB = 3.3 V ±0.3 V MAX MIN VCCB = 5 V ±0.5 V MAX MIN UNIT MAX 35.2 24.1 22.4 18.8 38.2 24.9 23.2 19.3 27.9 20.4 18.3 16.9 27 21.6 19.5 18.7 ns ns 6.8 Switching Characteristics: VCCA = 3.3 V ±0.3 V over operating free-air temperature range (unless otherwise noted; see Figure 7-1) PARAMETER tPLH tPHL tPLH tPHL tPHZ tPLZ tPHZ tPLZ tPZH (1) tPZL (1) tPZH (1) tPZL (1) FROM (INPUT) TO (OUTPUT) A B B A DIR A DIR B DIR A DIR B VCCB = 1.8 V ±0.15 V MIN VCCB = 2.5 V ±0.2 V MAX MIN 2.1 18.5 2 15.6 VCCB = 3.3 V ±0.3 V VCCB = 5 V ±0.5 V UNIT MAX MIN MAX MIN MAX 1.4 11 0.7 8.8 0.7 7.4 1.3 10 0.8 8 0.7 7 1.7 11.3 1.3 9.4 0.7 8.8 0.6 8.4 1.8 10.1 1.3 8.4 0.8 8 0.7 7.5 2.9 10.3 3 10.3 2.8 10.3 3.4 10.3 1.8 8.6 1.6 8.6 2.2 8.7 2.2 8.7 5.4 27.5 3.9 13.1 2.9 11.8 2.4 9.8 3.3 17.5 2.9 10.8 2.4 10.1 1.7 7.9 26.8 20.2 18.9 16.3 37.6 21.5 19.8 17.3 27.1 19.6 17.5 16.1 25.9 20.3 18.3 17.3 ns ns ns ns ns ns 6.9 Switching Characteristics: VCCA = 5 V ±0.5 V over operating free-air temperature range (unless otherwise noted; see Figure 7-1) PARAMETER tPLH tPHL tPLH tPHL tPHZ tPLZ tPHZ tPLZ tPZH (1) tPZL (1) tPZH (1) tPZL (1) 8 FROM (INPUT) TO (OUTPUT) A B B A DIR A DIR B DIR A DIR B VCCB = 1.8 V ±0.15 V MIN MAX VCCB = 2.5 V ±0.2 V VCCB = 3.3 V ±0.3 V VCCB = 5 V ±0.5 V UNIT MIN MAX MIN MAX MIN MAX 1.9 18.1 1 10.5 0.6 8.4 0.5 6.9 1.8 15.2 0.9 9.2 0.7 7.5 0.5 6.5 1.4 10.2 1 8.1 0.7 7.4 0.5 6.9 1.7 10 0.9 7.6 0.7 7 0.5 6.5 2.1 8.4 2.2 8.4 2.2 8.5 2.2 8.4 0.9 6.8 1 6.8 0.7 6.7 0.7 6.7 4.8 26.2 2.5 14.8 1 11.5 2.5 9.5 3.2 17.8 2.5 10.4 2.5 10 1.6 7.5 28 18.5 17.4 14.4 36.2 22.4 18.5 16 24.9 17.3 15.1 13.6 23.6 17.6 16 14.9 Submit Document Feedback ns ns ns ns ns ns Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVC1T45-Q1 SN74LVC1T45-Q1 www.ti.com SCES677E – SEPTEMBER 2006 – REVISED DECEMBER 2022 6.10 Typical Characteristics 10 10 9 9 8 8 VCCB = 1.8 V VCCB = 1.8 V 7 6 t PLH − ns t PHL − ns 7 VCCB = 2.5 V 5 4 6 VCCB = 2.5 V 5 VCCB = 3.3 V 4 VCCB = 5 V VCCB = 3.3 V 3 3 VCCB = 5 V 2 2 1 1 0 0 0 5 10 20 15 25 30 35 0 10 5 15 20 25 30 35 CL − pF CL − pF TA = 25°C, VCCA = 1.8 V Figure 6-1. Typical Propagation Delay (A to B) vs Load Capacitance TA = 25°C, VCCA = 1.8 V Figure 6-2. Typical Propagation Delay (A to B) vs Load Capacitance 10 10 9 9 VCCB = 1.8 V 8 8 VCCB = 2.5 V 7 6 6 t PLH − ns t PHL − ns VCCB = 1.8 V 7 5 VCCB = 2.5 V 4 VCCB = 3.3 V VCCB = 3.3 V VCCB = 5 V 5 4 VCCB = 5 V 3 3 2 2 1 1 0 0 5 10 15 20 25 30 0 35 0 5 10 CL − pF TA = 25°C, VCCA = 1.8 V Figure 6-3. Typical Propagation Delay (B to A) vs Load Capacitance 10 9 9 8 8 t PLH − ns t PHL − ns 30 35 VCCB = 1.8 V 7 VCCB = 1.8 V 6 6 5 VCCB = 2.5 V 4 4 VCCB = 3.3 V 3 3 VCCB = 5 V 5 VCCB = 2.5 V VCCB = 3.3 V 2 25 TA = 25°C, VCCA = 1.8 V Figure 6-4. Typical Propagation Delay (B to A) vs Load Capacitance 10 7 15 20 CL − pF 2 VCCB = 5 V 1 1 0 0 0 5 10 15 20 25 30 35 0 5 10 15 20 25 30 35 CL − pF CL − pF TA = 25°C, VCCA = 2.5 V Figure 6-5. Typical Propagation Delay (A to B) vs Load Capacitance TA = 25°C, VCCA = 2.5 V Figure 6-6. Typical Propagation Delay (A to B) vs Load Capacitance Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVC1T45-Q1 9 SN74LVC1T45-Q1 www.ti.com SCES677E – SEPTEMBER 2006 – REVISED DECEMBER 2022 6.10 Typical Characteristics (continued) 9 8 8 7 7 t PLH − ns 10 9 t PHL − ns 10 6 VCCB = 1.8 V 5 6 VCCB = 1.8 V 5 4 4 3 VCCB = 3.3 V VCCB = 5 V 2 VCCB = 2.5 V VCCB = 3.3 V 3 VCCB = 2.5 V VCCB = 5 V 2 1 1 0 0 5 10 15 20 CL − pF 25 30 0 35 0 5 10 15 20 25 30 35 CL − pF TA = 25°C, VCCA = 2.5 V Figure 6-7. Typical Propagation Delay (B to A) vs Load Capacitance TA = 25°C, VCCA = 2.5 V Figure 6-8. Typical Propagation Delay (B to A) vs Load Capacitance 10 10 9 9 8 8 7 7 VCCB = 1.8 V VCCB = 1.8 V 6 t PLH − ns t PHL − ns 6 5 4 VCCB = 2.5 V 5 VCCB = 2.5 V 4 VCCB = 3.3 V 3 3 2 VCCB = 5 V 2 VCCB = 3.3 V VCCB = 5 V 1 0 0 10 5 1 15 20 25 30 0 0 35 5 10 TA = 25°C, VCCA = 3.3 V Figure 6-9. Typical Propagation Delay (A to B) vs Load Capacitance 20 25 30 35 TA = 25°C, VCCA = 3.3 V Figure 6-10. Typical Propagation Delay (A to B) vs Load Capacitance 10 10 9 9 8 8 7 7 6 6 t PLH − ns t PHL − ns 15 CL − pF CL − pF 5 VCCB = 1.8 V 4 5 VCCB = 1.8 V 4 VCCB = 2.5 V VCCB = 2.5 V 3 3 2 VCCB = 5 V VCCB = 5 V 1 VCCB = 3.3 V 2 VCCB = 3.3 V 1 0 0 0 5 10 15 20 25 30 35 0 TA = 25°C, VCCA = 3.3 V Figure 6-11. Typical Propagation Delay (B to A) vs Load Capacitance 10 5 10 15 20 25 30 35 CL − pF CL − pF TA = 25°C, VCCA = 3.3 V Figure 6-12. Typical Propagation Delay (B to A) vs Load Capacitance Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVC1T45-Q1 SN74LVC1T45-Q1 www.ti.com SCES677E – SEPTEMBER 2006 – REVISED DECEMBER 2022 6.10 Typical Characteristics (continued) 10 10 9 9 8 8 7 7 VCCB = 1.8 V VCCB = 1.8 V t PLH − ns t PHL − ns 6 5 4 VCCB = 2.5 V 3 6 5 VCCB = 2.5 V 4 VCCB = 3.3 V 3 2 2 VCCB = 5 V VCCB = 3.3 V 1 1 VCCB = 5 V 0 0 0 5 10 15 20 25 30 0 35 5 10 10 10 9 9 8 8 7 7 6 6 5 VCCB = 1.8 V 3 VCCB = 2.5 V 30 35 5 VCCB = 1.8 V 4 VCCB = 2.5 V 3 2 2 VCCB = 3.3 V VCCB = 5 V VCCB = 3.3 V 1 0 25 TA = 25°C, VCCA = 5 V Figure 6-14. Typical Propagation Delay (A to B) vs Load Capacitance t PLH − ns t PHL− ns TA = 25°C, VCCA = 5 V Figure 6-13. Typical Propagation Delay (A to B) vs Load Capacitance 4 20 15 CL − pF CL − pF 1 VCCB = 5 V 0 5 10 15 20 25 30 35 0 0 CL − pF 5 10 15 20 25 30 35 CL − pF TA = 25°C, VCCA = 5 V Figure 6-15. Typical Propagation Delay (B to A) vs Load Capacitance TA = 25°C, VCCA = 5 V Figure 6-16. Typical Propagation Delay (B to A) vs Load Capacitance Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVC1T45-Q1 11 SN74LVC1T45-Q1 www.ti.com SCES677E – SEPTEMBER 2006 – REVISED DECEMBER 2022 Parameter Measurement Information 2 × VCCO S1 RL From Output Under Test Open GND CL (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCCO GND RL tw LOAD CIRCUIT VCCI VCCI/2 Input VCCO CL RL VTP 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V 15 pF 15 pF 15 pF 15 pF 2 kW 2 kW 2 kW 2 kW 0.15 V 0.15 V 0.3 V 0.3 V VCCI/2 0V VOLTAGE WAVEFORMS PULSE DURATION VCCA Output Control (low-level enabling) VCCA/2 VCCA/2 0V tPLZ tPZL VCCI Input VCCI/2 VCCI/2 0V tPLH tPHL Output VOH VCCO/2 VOL VCCO/2 VCCO Output Waveform 1 S1 at 2 × VCCO (see Note B) VCCO/2 VOL + VTP VOL tPHZ tPZH Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCCO/2 VOH − VTP VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W, dv/dt ≥ 1 V/ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. t PZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. VCCI is the VCC associated with the input port. I. VCCO is the VCC associated with the output port. J. All parameters and waveforms are not applicable to all devices. Figure 7-1. Load Circuit and Voltage Waveforms 12 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVC1T45-Q1 SN74LVC1T45-Q1 www.ti.com SCES677E – SEPTEMBER 2006 – REVISED DECEMBER 2022 7 Detailed Description 7.1 Overview The SN74LVC1T45-Q1 is single-bit, dual-supply, non-inverting voltage level translation. Pin A and that direction control pin (DIR) are supported by VCCA and pin B is supported by VCCB. The A port is able to accept I/O voltages ranging from 1.65 V to 5.5 V, while the B port can accept I/O voltages from 1.65 V to 5.5 V. The high on the DIR allows data transmissions from A to B and a low on the DIR allows data transmissions from B to A. 7.2 Functional Block Diagram DIR A 5 3 4 VCCA B VCCB Copyright © 2016, Texas Instruments Incorporated Figure 7-1. Logic Diagram (Positive Logic) 7.3 Feature Description The SN74LVC1T45-Q1 has a fully configurable dual-rail design that allows each port to operate over the full 1.65-V to 5.5-V power-supply range. Both VCCA and VCCB can be supplied at any voltage between 1.65 V and 5.5 V, making the device suitable for translating between any of the voltage nodes (1.8-V, 2.5-V, 3.3-V, and 5-V). SN74LVC1T45-Q1 can support high data rate applications. The translated signal data rate can be up to 420 Mbps when the signal is translated from 3.3 V to 5 V. Ioff prevents backflow current by disabling I/O output circuits when device is in partial-power-down mode. 7.4 Device Functional Modes Table 7-1 lists the operational modes of SN74LVC1T45-Q1. Table 7-1. Function Table(1) (1) INPUT DIR OPERATION L B data to A bus H A data to B bus Input circuits of the data I/Os always are active. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVC1T45-Q1 13 SN74LVC1T45-Q1 www.ti.com SCES677E – SEPTEMBER 2006 – REVISED DECEMBER 2022 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The SN74LVC1T45-Q1 device can be used in level-translation applications for interfacing devices or systems operating at different interface voltages with one another. The max data rate can be up to 420 Mbps when device translates signals from 3.3 V to 5 V. 8.1.1 Enable Times Calculate the enable times for the SN74LVC1T45-Q1 using the following formulas: • • • • tPZH (DIR to A) = tPLZ (DIR to B) + tPLH (B to A) tPZL (DIR to A) = tPHZ (DIR to B) + tPHL (B to A) tPZH (DIR to B) = tPLZ (DIR to A) + tPLH (A to B) tPZL (DIR to B) = tPHZ (DIR to A) + tPHL (A to B) In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is switched until an output is expected. For example, if the SN74LVC1T45-Q1 initially is transmitting from A to B, then the DIR bit is switched; the B port of the device must be disabled before presenting it with an input. After the B port has been disabled, an input signal applied to it appears on the corresponding A port after the specified propagation delay. 8.2 Typical Applications 8.2.1 Unidirectional Logic Level-Shifting Application Figure 8-1 shows an example of the SN74LVC1T45-Q1 being used in a unidirectional logic level-shifting application. VCC1 VCC1 VCC2 1 6 2 5 3 4 SYSTEM-1 VCC2 SYSTEM-2 Copyright © 2016, Texas Instruments Incorporated Figure 8-1. Unidirectional Logic Level-Shifting Application 8.2.1.1 Design Requirements For this design example, use the parameters listed in Table 8-1. Table 8-1. Design Parameters 14 PARAMETER VALUE Input voltage 1.65 V to 5.5 V Output voltage 1.65 V to 5.5 V Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVC1T45-Q1 SN74LVC1T45-Q1 www.ti.com SCES677E – SEPTEMBER 2006 – REVISED DECEMBER 2022 8.2.1.2 Detailed Design Procedure To begin the design process, determine the following: • • Input voltage range – Use the supply voltage of the device that is driving the SN74LVC1T45-Q1 device to determine the input voltage range. For a valid logic high the value must exceed the VIH of the input port. For a valid logic low the value must be less than the VIL of the input port. Output voltage range – Use the supply voltage of the device that the SN74LVC1T45-Q1 device is driving to determine the output voltage range. 8.2.1.3 Application Curves Figure 8-2. Translation Up (1.8 V to 5 V) at 2.5 MHz 8.2.2 Bidirectional Logic Level-Shifting Application Figure 8-3 shows the SN74LVC1T45-Q1 being used in a bidirectional logic level-shifting application. Because the SN74LVC1T45-Q1 does not have an output-enable (OE) pin, the system designer should take precautions to avoid bus contention between SYSTEM-1 and SYSTEM-2 when changing directions. VCC1 VCC1 VCC2 VCC2 I/O-1 Pullup/Down (1) or Bus Hold Pullup/Down (1) or Bus Hold 1 6 2 5 3 4 I/O-2 DIR CTRL SYSTEM-1 SYSTEM-2 Copyright © 2016, Texas Instruments Incorporated Figure 8-3. Bidirectional Logic Level-Shifting Application Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVC1T45-Q1 15 SN74LVC1T45-Q1 www.ti.com SCES677E – SEPTEMBER 2006 – REVISED DECEMBER 2022 8.2.2.1 Detailed Design Procedure Table 8-2 shows data transmission from SYSTEM-1 to SYSTEM-2 and then from SYSTEM-2 to SYSTEM-1. Table 8-2. Data Transmission STATE DIR CTRL I/O-1 I/O-2 1 H Out In 2 H Hi-Z Hi-Z SYSTEM-2 is getting ready to send data to SYSTEM-1. I/O-1 and I/O-2 are disabled. The bus-line state depends on pullup or pulldown.(1) 3 L Hi-Z Hi-Z DIR bit is flipped. I/O-1 and I/O-2 still are disabled. The bus-line state depends on pullup or pulldown.(1) 4 L Out In (1) DESCRIPTION SYSTEM-1 data to SYSTEM-2 SYSTEM-2 data to SYSTEM-1 SYSTEM-1 and SYSTEM-2 must use the same conditions, that is, both pullup or both pulldown. 8.2.2.2 Application Curves Figure 8-4. Translation Down (5 V to 1.8 V) at 2.5 MHz 8 Power Supply Recommendations The SN74LVC1T45-Q1 device uses two separate configurable power-supply rails, VCCA and VCCB. VCCA accepts any supply voltage from 1.65 V to 5.5 V, and VCCB accepts any supply voltage from 1.65 V to 5.5 V. The A port and B port are designed to track VCCA and VCCB, respectively allowing for low-voltage bidirectional translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes. Each VCC pin should have a good bypass capacitor to prevent power disturbance. For multiple VCC pins then 0.01-µF or 0.022-µF capacitor is recommended for each power pin. It is ok to parallel multiple bypass capacitors to reject different frequencies of noise. 0.1-µF and 1-µF capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as possible for best results. A proper power-up sequence is advisable as listed in the following: 1. Connect ground before any supply voltage is applied. 2. Power up VCCB. 3. VCCA can be ramped up along with VCCB. TI recommends that the inputs are grounded during power up. Take care to assure that any state changes do not affect system level operation. 16 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVC1T45-Q1 www.ti.com SN74LVC1T45-Q1 SCES677E – SEPTEMBER 2006 – REVISED DECEMBER 2022 9 Layout 9.1 Layout Guidelines To assure reliability of the device, the following common printed-circuit board layout guidelines are recommended: • • • Bypass capacitors must be used on power supplies. Short trace lengths must be used to avoid excessive loading. Placing pads on the signal paths for loading capacitors or pullup resistors to help adjust rise and fall times of signals depends on the system requirements. 9.2 Layout Example Figure 9-1. Layout Schematic Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVC1T45-Q1 17 SN74LVC1T45-Q1 www.ti.com SCES677E – SEPTEMBER 2006 – REVISED DECEMBER 2022 10 Device and Documentation Support 10.1 Documentation Support 10.1.1 Related Documentation For related documentation see the following: • Texas Instruments, Implications of Slow or Floating CMOS Inputs application note 10.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 10.3 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 10.4 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 10.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 10.6 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 11 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 18 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVC1T45-Q1 PACKAGE OPTION ADDENDUM www.ti.com 8-Sep-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) SN74LVC1T45QDCKRQ1 ACTIVE SC70 DCK 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 5TR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of