SN54LVC574A, SN74LVC574A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS301R − JANUARY 1993 − REVISED MARCH 2005
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
CLK
All Ports (5-V Input/Output Voltage With
3.3-V VCC)
Ioff Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
1D
2D
3D
4D
5D
6D
7D
8D
20
19 1Q
3
18 2Q
4
17 3Q
16 4Q
15 5Q
5
6
8
14 6Q
13 7Q
9
12 8Q
7
10
11
3D
4D
5D
6D
7D
1Q
1
2
SN54LVC574A . . . FK PACKAGE
(TOP VIEW)
2D
1D
OE
VCC
SN74LVC574A . . . RGY PACKAGE
(TOP VIEW)
VCC
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
D
CLK
SN54LVC574A . . . J OR W PACKAGE
SN74LVC574A . . . DB, DGV, DW, N, NS,
OR PW PACKAGE
(TOP VIEW)
D
OE
D
D
−40°C to 125°C, and −55°C to 125°C
Max tpd of 7 ns at 3.3 V
Typical VOLP (Output Ground Bounce)
2 V at VCC = 3.3 V, TA = 25°C
GND
D
D
D Support Mixed-Mode Signal Operation on
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
2Q
3Q
4Q
5Q
6Q
8D
GND
CLK
8Q
7Q
D Operate From 1.65 V to 3.6 V
D Inputs Accept Voltages to 5.5 V
D Specified From −40°C to 85°C,
description/ordering information
The SN54LVC574A octal edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V VCC operation, and the
SN74LVC574A octal edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V VCC operation.
These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively
low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers.
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus
lines without interface or pullup components.
OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the device when it is powered down.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2005, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN54LVC574A, SN74LVC574A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS301R − JANUARY 1993 − REVISED MARCH 2005
description/ordering information (continued)
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
ORDERING INFORMATION
QFN − RGY
Reel of 1000
PDIP − N
Reel of 1000
SN74LVC574AN
Tube of 25
SN74LVC574ADW
Reel of 2000
SN74LVC574ADWR
SOP − NS
Reel of 2000
SN74LVC574ANSR
LVC574A
SSOP − DB
Reel of 2000
SN74LVC574ADBR
LC574A
Tube of 70
SN74LVC574APW
Reel of 2000
SN74LVC574APWR
Reel of 250
SN74LVC574APWT
TVSOP − DGV
Reel of 2000
SN74LVC574ADGVR
LC574A
CDIP − J
Tube of 20
SNJ54LVC574AJ
SNJ54LVC574AJ
CFP − W
Tube of 85
SNJ54LVC574AW
SNJ54LVC574AW
LCCC − FK
Tube of 55
SNJ54LVC574AFK
SNJ54LVC574AFK
TSSOP − PW
SN74LVC574AN
LVC574A
LC574A
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
GQN OR ZQN PACKAGE
(TOP VIEW)
1
2
3
terminal assignments
4
1
2
3
4
A
A
1D
OE
VCC
1Q
B
B
3D
3Q
2D
2Q
C
C
5D
4D
5Q
4Q
D
D
7D
7Q
6D
6Q
E
E
GND
8D
CLK
8Q
FUNCTION TABLE
(each flip-flop)
INPUTS
2
LC574A
SN74LVC574AZQNR
Tube of 20
SOIC − DW
−55°C to 125°C
LC574A
SN74LVC574AGQNR
VFBGA − ZQN (Pb-free)
−40°C
40 C to 125
125°C
C
TOP-SIDE
MARKING
SN74LVC574ARGYR
VFBGA − GQN
−40°C
40 C to 85°C
85 C
†
ORDERABLE
PART NUMBER
PACKAGE†
TA
OE
CLK
D
OUTPUT
Q
L
↑
H
H
L
↑
L
L
L
L
X
Q0
H
X
X
Z
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54LVC574A, SN74LVC574A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS301R − JANUARY 1993 − REVISED MARCH 2005
logic diagram (positive logic)
OE
CLK
1
11
C1
1D
2
19
1Q
1D
To Seven Other Channels
Pin numbers shown are for the DB, DGV, DW, FK, J, N, NS, PW, RGY, and W packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
Voltage range applied to any output in the high or low state, VO
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
(see Note 3): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92°C/W
(see Note 3): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
(see Note 3): GQN/ZQN package . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W
(see Note 3): N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
(see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
(see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
(see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Power dissipation, Ptot (TA = −40°C to 125°C) (see Notes 5 and 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mW
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of VCC is provided in the recommended operating conditions table.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4. The package thermal impedance is calculated in accordance with JESD 51-5.
5. For the DW package: above 70°C the value of Ptot derates linearly with 8 mW/K.
6. For the DB, DGV, N, NS, and PW packages: above 60°C the value of Ptot derates linearly with 5.5 mW/K.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN54LVC574A, SN74LVC574A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS301R − JANUARY 1993 − REVISED MARCH 2005
recommended operating conditions (see Note 7)
SN54LVC574A
−55 TO 125°C
MIN
MAX
2
3.6
Operating
VCC
Supply voltage
VIH
High-level input voltage
VCC = 2.7 V to 3.6 V
VIL
Low-level input voltage
VCC = 2.7 V to 3.6 V
VI
Input voltage
Data retention only
VO
Output voltage
IOH
High level output current
High-level
IOL
O
Low level output current
Low-level
Δt/Δv
Input transition rise or fall rate
UNIT
V
1.5
2
V
0.8
V
V
0
5.5
High or low state
0
VCC
3−state
0
5.5
VCC = 2.7 V
−12
VCC = 3 V
−24
VCC = 2.7 V
12
VCC = 3 V
24
6
V
mA
mA
ns/V
NOTE 7: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
recommended operating conditions (see Note 7)
SN74LVC574A
TA = 25°C
Operating
VCC
Supply voltage
VIH
High-level
Hi
hl
l input
i
t
voltage
VIL
Low-level
L
l
l input
i
t
voltage
VI
Input voltage
Data retention only
IOH
Output voltage
High level
High-level
output current
−40 TO 125°C
MIN
MAX
MIN
MAX
MIN
MAX
1.65
3.6
1.65
3.6
1.65
3.6
1.5
1.5
1.5
0.65 × VCC
0.65 × VCC
0.65 × VCC
VCC = 2.3 V to 2.7 V
1.7
1.7
1.7
VCC = 2.7 V to 3.6 V
2
2
2
VCC = 1.65 V to 1.95 V
VCC = 1.65 V to 1.95 V
V
0.35 × VCC
0.35 × VCC
0.7
0.7
0.7
0.8
0.8
5.5
0
5.5
0
5.5
High or low state
0
VCC
0
VCC
0
VCC
3−state
0
5.5
0
5.5
0
5.5
VCC = 1.65 V
−4
−4
−4
VCC = 2.3 V
−8
−8
−8
VCC = 2.7 V
−12
−12
−12
VCC = 3 V
−24
−24
−24
4
4
4
VCC = 2.3 V
8
8
8
VCC = 2.7 V
12
12
12
VCC = 3 V
24
24
24
6
6
6
IOL
Low level
Low-level
output current
Δt/Δv
Input transition rise or fall rate
V
0.8
0
VCC = 1.65 V
UNIT
V
0.35 × VCC
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VO
−40 TO 85°C
V
V
mA
mA
ns/V
NOTE 7: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54LVC574A, SN74LVC574A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS301R − JANUARY 1993 − REVISED MARCH 2005
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LVC574A
PARAMETER
TEST CONDITIONS
VCC
−55 TO 125°C
MIN
IOH = −100 μA
VOH
2.7 V to 3.6 V
2.2
3V
2.4
3V
2.2
IOH = −24 mA
IOL = 100 μA
VOL
‡
MAX
V
2.7 V to 3.6 V
0.2
IOL = 12 mA
2.7 V
0.4
IOL = 24 mA
3V
0.55
V
II
VI = 5.5 V or GND
3.6 V
±5
μA
IOZ
VO = 0 to 5.5 V
3.6 V
±15
μA
ICC
†
UNIT
VCC − 0.2
2.7 V
12 mA
IOH = −12
TYP†
VI = VCC or GND
10
IO = 0
3.6 V ≤ VI ≤ 5.5 V‡
36V
3.6
10
μA
A
ΔICC
One input atVCC − 0.6 V, Other inputs at VCC or GND
Ci
VI = VCC or GND
3.3 V
4
pF
Co
VO = VCC or GND
3.3 V
5.5
pF
2.7 V to 3.6 V
500
μA
TA = 25°C
This applies in the disabled state only.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SN54LVC574A, SN74LVC574A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS301R − JANUARY 1993 − REVISED MARCH 2005
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN74LVC574A
PARAMETER
TEST CONDITIONS
TA = 25°C
VCC
MIN
IOH = −100 μA
VOH
1.65 V to 3.6 V
MAX
MIN
VCC − 0.2
VCC − 0.2
1.29
1.2
1.2
IOH = −8 mA
2.3 V
1.9
1.7
1.7
2.7 V
2.2
2.2
2.2
3V
2.4
2.4
2.4
3V
2.3
IOL = 100 μA
2.2
V
2.2
0.1
0.2
0.2
IOL = 4 mA
1.65 V
0.24
0.45
0.45
IOL = 8 mA
2.3 V
0.3
0.7
0.7
IOL = 12 mA
2.7 V
0.4
0.4
0.4
0.55
II
VI = 5.5 V or GND
Ioff
VI or VO = 5.5 V
IOZ
VI = 0 to 5.5 V
VI = VCC or GND
3.6 V ≤ VI ≤ 5.5 V†
V
3V
0.55
0.55
3.6 V
±1
±5
±5
μA
0
±4
±10
±10
μA
μA
3.6 V
IO = 0
UNIT
MAX
1.65 V to 3.6 V
IOL = 24 mA
†
MIN
VCC − 0.2
1.65 V
IOH = −24 mA
ICC
MAX
−40 TO 125°C
IOH = −4 mA
IOH = −12
12 mA
VOL
TYP
−40 TO 85°C
36V
3.6
±1
±10
±10
1.5
10
10
1.5
10
10
500
500
500
μA
A
ΔICC
One input at VCC − 0.6 V,
Other inputs at VCC or
GND
Ci
VI = VCC or GND
3.3 V
4
pF
Co
VO = VCC or GND
3.3 V
5.5
pF
2.7 V to 3.6 V
μA
This applies in the disabled state only.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
SN54LVC574A
VCC
−55 TO 125°C
MIN
6
fclock
Clock frequency
tw
duration CLK high or low
Pulse duration,
tsu
Setup time
time, data before CLK↑
th
Hold time,
time data after CLK↑
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2.7 V
150
3.3 V ± 0.3 V
150
2.7 V
3.3
3.3 V ± 0.3 V
3.3
2.7 V
2
3.3 V ± 0.3 V
2
2.7 V
2
3.3 V ± 0.3 V
2
UNIT
MAX
MHz
ns
ns
ns
SN54LVC574A, SN74LVC574A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS301R − JANUARY 1993 − REVISED MARCH 2005
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
SN54LVC574A
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
−55 TO 125°C
VCC
MIN
fmax
2.7 V
150
3.3 V ± 0.3 V
150
CLK
Q
ten
OE
Q
tdis
OE
Q
MAX
MHz
8
2.7 V
tpd
UNIT
3.3 V ± 0.3 V
1
7
1
7.5
0.5
6.4
ns
9
2.7 V
3.3 V ± 0.3 V
7
2.7 V
3.3 V ± 0.3 V
ns
ns
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
SN74LVC574A
TA = 25°C
VCC
MIN
fclock
tw
tsu
th
Clock frequency
duration CLK high or low
Pulse duration,
Setup time
time, data before CLK↑
Hold time,
time data after CLK↑
TYP
−40 TO 85°C
MAX
MIN
MAX
−40 TO 125°C
MIN
1.8 V ± 0.15 V
55
55
40
2.5 V ± 0.2 V
95
95
80
2.7 V
150
150
150
3.3 V ± 0.3 V
150
150
150
1.8 V ± 0.15 V
9
9
2.5 V ± 0.2 V
4
4
4
2.7 V
3.3
3.3
3.3
3.3 V ± 0.3 V
3.3
3.3
3.3
6
6
6
2.5 V ± 0.2 V
4
4
4
2.7 V
2
2
2
3.3 V ± 0.3 V
2
2
2
1.8 V ± 0.15 V
4
4
4
2.5 V ± 0.2 V
2
2
2
2.7 V
1.5
1.5
1.5
3.3 V ± 0.3 V
1.5
1.5
1.5
• DALLAS, TEXAS 75265
MHz
9
1.8 V ± 0.15 V
POST OFFICE BOX 655303
UNIT
MAX
ns
ns
ns
7
SN54LVC574A, SN74LVC574A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS301R − JANUARY 1993 − REVISED MARCH 2005
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
SN74LVC574A
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TA = 25°C
VCC
MIN
1.8 V ± 0.15 V
fmax
tpd
CLK
ten
OE
tdis
OE
Q
Q
Q
TYP
−40 TO 85°C
MAX
55
MIN
MAX
55
MIN
UNIT
MAX
40
2.5 V ± 02 V
95
95
80
2.7 V
150
150
150
3.3 V ± 0.3 V
150
150
150
1.8 V ± 0.15 V
1.0
7.1
21.5
1
21.6
1.0
21.6
2.5 V ± 0.2 V
1.0
4.9
10.0
1
10.5
1.0
10.5
2.7 V
1.0
5.0
7.8
1
8
1.0
8.0
3.3 V ± 0.3 V
2.2
4.6
6.8
2.2
7
2.2
7.0
1.8 V ± 0.15 V
1.0
6.6
19.0
1
19.5
1.0
19.5
2.5 V ± 0.2 V
1.0
4.8
10.0
1
10.5
1.0
10.5
2.7 V
1.0
5.5
8.3
1
8.5
1.0
8.5
MHz
3.3 V ± 0.3 V
1.5
4.4
7.3
1.5
7.5
1.5
7.5
1.8 V ± 0.15 V
1.0
5.4
18.3
1
18.8
1.0
18.8
2.5 V ± 0.2 V
1.0
3.0
7.3
1
7.8
1.0
7.8
2.7 V
1.0
4.0
6.8
1
7
1.0
7.3
3.3 V ± 0.3 V
1.7
3.9
6.2
1.7
6.4
1.7
6.6
3.3 V ± 0.3 V
tsk(o)
−40 TO 125°C
1
1
ns
ns
ns
ns
operating characteristics, TA = 25°C
TEST
CONDITIONS
PARAMETER
Outputs
p
enabled
Cpdd
Power dissipation capacitance per flip−flop
flip flop
f = 10 MHz
Outputs
p
disabled
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
VCC
TYP
1.8 V
25
2.5 V
29
3.3 V
30
1.8 V
9
2.5 V
9
3.3 V
11
UNIT
pF
SN54LVC574A, SN74LVC574A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS301R − JANUARY 1993 − REVISED MARCH 2005
PARAMETER MEASUREMENT INFORMATION
VLOAD
RL
From Output
Under Test
CL
(see Note A)
S1
Open
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
3.3 V ± 0.3 V
VI
tr/tf
VCC
VCC
2.7 V
2.7 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
VΔ
VCC/2
VCC/2
1.5 V
1.5 V
2 × VCC
2 × VCC
6V
6V
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VM
VM
VOL
tPHL
VM
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VM
tPZL
tPHL
VOH
Output
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + VΔ
VOL
tPHZ
VM
VOH − VΔ
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
SN54LVC574A, SN74LVC574A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS301R − JANUARY 1993 − REVISED MARCH 2005
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
5962-9757601QRA
ACTIVE
CDIP
J
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9757601QR
A
SNJ54LVC574AJ
5962-9757601QSA
ACTIVE
CFP
W
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9757601QS
A
SNJ54LVC574AW
SN74LVC574ADBR
ACTIVE
SSOP
DB
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC574A
Samples
SN74LVC574ADGVR
ACTIVE
TVSOP
DGV
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC574A
Samples
SN74LVC574ADGVRE4
ACTIVE
TVSOP
DGV
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC574A
Samples
SN74LVC574ADW
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC574A
Samples
SN74LVC574ADWE4
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC574A
Samples
SN74LVC574ADWR
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC574A
Samples
SN74LVC574AN
ACTIVE
PDIP
N
20
20
RoHS &
Non-Green
NIPDAU
N / A for Pkg Type
-40 to 125
SN74LVC574AN
Samples
SN74LVC574ANSR
ACTIVE
SO
NS
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC574A
Samples
SN74LVC574APW
ACTIVE
TSSOP
PW
20
70
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
LC574A
Samples
SN74LVC574APWG4
ACTIVE
TSSOP
PW
20
70
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC574A
Samples
SN74LVC574APWR
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
LC574A
Samples
SN74LVC574APWRG4
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC574A
Samples
SN74LVC574APWT
ACTIVE
TSSOP
PW
20
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC574A
Samples
SN74LVC574ARGYR
ACTIVE
VQFN
RGY
20
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LC574A
Samples
SNJ54LVC574AJ
ACTIVE
CDIP
J
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9757601QR
A
SNJ54LVC574AJ
Addendum-Page 1
Samples
Samples
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
14-Oct-2022
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
Samples
(4/5)
(6)
SNJ54LVC574AW
ACTIVE
CFP
W
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9757601QS
A
SNJ54LVC574AW
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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