SN75LVCP600DRFR

Order Now Product Folder Technical Documents Support & Community Tools & Software SN75LVCP600 SLLSE63A – DECEMBER 2010 – REVISED MAY 2016 SN75LVCP600 6-Gbps SATA PCB and Cable Equalizer 1 Features 3 Description • • • • • The SN75LVCP600 is a versatile single channel, SATA Express signal conditioner supporting data rates up to 6 Gbps. The device supports SATA Gen 1, 2, and 3 specifications as well as PCIe 1.0, 2.0, and 3.0. The SN75LVCP600 operates from a single 3.3-V supply and has 100-Ω line termination with selfbiasing feature, making the device suitable for AC coupling. The inputs incorporate an out-of-band (OOB) detector, which automatically squelches the output when the input differential voltage falls below threshold while maintaining a stable common-mode voltage. The device is also designed to handle spread spectrum clocking (SSC) transmission per SATA standard. 1 • • • • • • • SATA Express Support Selectable Equalization and De-Emphasis Hot Plug Capable Receiver Detect and OOB Support Multirate Operation: 1.5 Gbps, 3 Gbps, and 6 Gbps Suitable to Receive 6-Gbps Data Over Up to 40 Inches (1 Meter) of FR4 Compensates Up to 14-dB Loss on the Receive Side and 1.2-dB Loss on the Transmit Side at 3 GHz Integrated Output Squelch Auto Low Power Feature Lowers Power by > 90% – < 100 mW (Active Mode, Typical) – < 11 mW (Auto Low Power Mode, Typical) Single 3.3-V Supply High Protection Against ESD Transient – HBM: 6 kV – CDM: 1.5 kV Ultra-Small Footprint: 2 mm × 2 mm WSON Package The SN75LVCP600 handles interconnect losses at its input with selectable equalization settings that can be programmed to match the loss in the channel. For data rates of 3 Gbps and lower the SN75LVCP600 equalizes signals for a span of up to 50 inches of FR4 board material. For data rates of 8 Gbps the device compensates up to 40 in of FR4 material. The equalization level is controlled by the setting of the signal control pin EQ. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) 2 Applications SN75LVCP600 • • • • • (1) For all available packages, see the orderable addendum at the end of the data sheet. Notebooks Desktops Docking Stations Servers Workstations Typical Application WSON (8) 2.00 mm × 2.00 mm Data Flow Block Diagram Vcc[1] GND[5] VBB = 1.7 V TYP LVCP600 RT RX+ [2] SATA Sink RT RX- [3] HDD TX- [6] OOB Detect EQ Driver EQ TX+ [7] Equalizer SATA Host EQ CTRL SATA Host SAS Cable EQ [4] Copyright © 2016, Texas Instruments Incorporated DE [8] Copyright © 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN75LVCP600 SLLSE63A – DECEMBER 2010 – REVISED MAY 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 9 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Description (continued)......................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 4 7.1 7.2 7.3 7.4 7.5 7.6 7.7 4 4 4 4 4 6 8 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Timing Requirements ................................................ Typical Characteristics .............................................. Parameter Measurement Information .................. 9 Detailed Description ............................................ 10 9.1 Overview ................................................................. 10 9.2 Functional Block Diagram ....................................... 10 9.3 Feature Description................................................. 10 9.4 Device Functional Modes........................................ 11 10 Application and Implementation........................ 12 10.1 Application Information.......................................... 12 10.2 Typical Application ............................................... 12 11 Power Supply Recommendations ..................... 15 12 Layout................................................................... 16 12.1 Layout Guidelines ................................................. 16 12.2 Layout Example .................................................... 18 13 Device and Documentation Support ................. 20 13.1 13.2 13.3 13.4 13.5 13.6 Device Support...................................................... Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 20 20 20 20 20 20 14 Mechanical, Packaging, and Orderable Information ........................................................... 20 4 Revision History Changes from Original (December 2010) to Revision A Page • Added Device Information table, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. .................................... 1 • Changed RX+ from I, VML to I, CML in Pin Functions table.................................................................................................. 3 • Changed Noninverting and inverting VML differential inputs to Noninverting and inverting CML differential inputs in the Pin Functions table Description ........................................................................................................................................ 3 • Changed RX- from I, VML to I, CML in Pin Functions table................................................................................................... 3 • Changed TX+ from I, VML to O, VML in Pin Functions table ................................................................................................ 3 • Changed TX- from I, VML to O, VML in Pin Functions table ................................................................................................. 3 • Added Parameter Measurement Information section ............................................................................................................. 9 • Changed RX to Rx0. in Figure 7 ............................................................................................................................................ 9 2 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: SN75LVCP600 SN75LVCP600 www.ti.com SLLSE63A – DECEMBER 2010 – REVISED MAY 2016 5 Description (continued) Two de-emphasis levels can be selected on the transmit side to provide 0 dB or 1.2 dB of additional highfrequency loss compensation at the output. The device is hot-plug capable(1) preventing device damage under device hot-insertion such as async signal plug and removal, unpowered plug and removal, powered plug and removal, or surprise plug and removal. (1) Requires use of AC coupling capacitors at differential inputs and outputs. 6 Pin Configuration and Functions DRF Package 8-Pin WSON Top View VCC 1 8 DE 7 TX+ LVCP600 2 RX- 3 6 TX- EQ 4 5 GND 1 RX+ Package Thermal Pad Pin Functions PIN NAME NO. TYPE (1) DESCRIPTION HIGH SPEED DIFFERENTIAL I/O RX+ 2 I RX– 3 I TX+ 7 O TX– 6 O Noninverting and inverting VML differential outputs. These pins are tied to an internal voltage bias by dual termination resistor circuit. Noninverting and inverting CML differential inputs. These pins are tied to an internal voltage bias by dual termination resistor circuit. CONTROL PINS EQ 4 I Selects equalization settings per Table 1. Internally tied to GND. DE 8 I Selects de-emphasis settings per Table 1. Internally tied to GND. POWER VCC 1 P Positive supply must be 3.3 V ±10% GND 5 G Supply ground (1) G = Ground, I = Input, O = Output, P = Power Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: SN75LVCP600 3 SN75LVCP600 SLLSE63A – DECEMBER 2010 – REVISED MAY 2016 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) Supply voltage, VCC (2) Voltage (2) MAX UNIT 4 V V Differential I/O –0.5 4 Control I/O –0.5 VCC + 0.5 –65 150 Storage temperature, Tstg (1) MIN –0.5 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential voltages, are with respect to network ground pin. 7.2 ESD Ratings VALUE Electrostatic discharge V(ESD) (1) (2) Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) UNIT ±6000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) V ±1500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions typical values for all parameters are at VCC = 3.3 V and TA = 25°C; all temperature limits are specified by design VCC Supply voltage Coupling capacitor TA Operating free-air temperature MIN TYP MAX 3 3.3 3.6 V 75 100 200 nF 85 °C 0 UNIT 7.4 Thermal Information SN75LVCP600 THERMAL METRIC (1) DRF (WSON) UNIT 8 PINS RθJA Junction-to-ambient thermal resistance 97.8 °C/W RθJCtop Junction-to-case (top) thermal resistance 81.9 °C/W RθJB Junction-to-board thermal resistance 65.6 °C/W ψJT Junction-to-top characterization parameter 1.3 °C/W ψJB Junction-to-board characterization parameter 65.6 °C/W RθJCbot Junction-to-case (bottom) thermal resistance 19.1 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 7.5 Electrical Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DEVICE PARAMETERS ICCMax-s Active mode supply current EQ/DE = NC, K28.5 pattern at 6 Gbps, VID = 700 mVpp 29 40 ICCPS Auto power save mode ICC When auto low power conditions are met 3.3 5.9 Maximum data rate 4 6 Submit Documentation Feedback mA mA Gbps Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: SN75LVCP600 SN75LVCP600 www.ti.com SLLSE63A – DECEMBER 2010 – REVISED MAY 2016 Electrical Characteristics (continued) over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OOB VOOB Input OOB threshold 90 mVpp DVdiffOOB OOB differential delta F = 750 MHz 50 70 25 mV DVCMOOB OOB common-mode delta 50 mV CONTROL LOGIC VIH High-level input voltage VIL Low-level input voltage For all control pins 1.4 V VINHYS Input hysteresis IIH High-level input current VIH = VCC (DE/EQ) 20 μA IIL Low-level input current VIL = 0 V (DE/EQ) 10 μA 115 Ω 0.5 V 115 mV RECEIVER AC/DC ZDIFFRX Differential input impedance 85 ZSERX Single-ended input impedance 40 VCMRX Common-mode voltage RLDiffRX RXDiffRLSlope RLCMRX VdiffRX IBRX Common-mode return loss Differential input voltage PP Impedance balance Ω 1.7 f = 150 MHz to 300 MHz 18 26 f = 300 MHz to 600 MHz 14 22 10 17 f = 1.2 GHz to 2.4 GHz 8 12 f = 2.4 GHz to 3 GHz 3 Differential mode return loss (RL) f = 600 MHz to 1.2 GHz Differential mode RL slope 100 f = 300 MHz to 6 GHz (see Figure 7) V dB 11 –13 f = 150 MHz to 300 MHz 5 9.4 f = 300 MHz to 600 MHz 5 17 f = 600 MHz to 1.2 GHz 2 18 f = 1.2 GHz to 2.4 GHz 1 9.9 f = 2.4 GHz to 3 GHz 1 8.6 f = 1.5 GHz and 3 GHz 120 dB/dec dB 1600 f = 150 MHz to 300 MHz 30 41 f = 300 MHz to 600 MHz 30 41 f = 600 MHz to 1.2 GHz 20 34 f = 1.2 GHz to 2.4 GHz 10 24 f = 2.4 GHz to 3 GHz 10 26 f = 3 GHz to 5 GHz 4 18 f = 5 GHz to 6.5 GHz 4 18 100 mVpp dB TRANSMITTER AC/DC ZdiffTX Pair differential impedance 85 ZSETX Single-ended input impedance 40 VTXtrans RLDiffTX TXDiffRLSlope Sequencing transient voltage Differential mode return loss Differential mode RL slope Transient voltages on the serial data bus during power sequencing (lab load) Ω –1.2 0.3 f = 150 MHz to 300 MHz 13 22 f = 300 MHz to 600 MHz 8 21 f = 600 MHz to 1.2 GHz 6 19 f = 1.2 GHz to 2.4 GHz 6 14 f = 2.4 GHz to 3 GHz 3 f = 300 MHz to 3 GHz (see Figure 7) Ω 122 1.2 V dB 14 –13 dB/dec Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: SN75LVCP600 5 SN75LVCP600 SLLSE63A – DECEMBER 2010 – REVISED MAY 2016 www.ti.com Electrical Characteristics (continued) over recommended operating conditions (unless otherwise noted) PARAMETER RLCMTX IBTX Common-mode return loss Impedance balance DiffVppTX Differential output voltage swing TEST CONDITIONS MIN VCMTX TX AC CM voltage UNIT f = 150 MHz to 300 MHz 5 20 f = 300 MHz to 600 MHz 5 16 f = 600 MHz to 1.2 GHz 2 13 f = 1.2 GHz to 2.4 GHz 1 8 f = 2.4 GHz to 3 GHz 1 8 f = 150 MHz to 300 MHz 30 38 f = 300 MHz to 600 MHz 30 38 f = 600 MHz to 1.2 GHz 20 33 f = 1.2 GHz to 2.4 GHz 10 25 f = 2.4 GHz to 3 GHz 10 25 f = 3 GHz to 5 GHz 4 21 f = 5 GHz to 6.5 GHz 4 21 400 650 900 15 50 mVpp f = 3 GHz (under no interconnect loss) At 1.5 GHz VCMAC_TX TYP MAX dB dB mVpp At 3 GHz 10 26 dBmV (rms) At 6 GHz 12 30 dBmV (rms) Common-mode voltage 1.7 V TRANSMITTER JITTER (1) DJTX Residual deterministic jitter VID = 500 mVpp, UI = 333 ps, K28.5 control character, see Figure 8 0.12 0.19 RJTX Random jitter VID = 500 mVpp, UI = 333 ps, K28.7 control character, see Figure 8 1 2 DJTX Residual deterministic jitter VID = 500 mVpp, UI = 167 ps, K28.5 control character, see Figure 8 0.12 0.34 RJTX Random jitter VID = 500 mVpp, UI = 167 ps, K28.7 control character, see Figure 8 0.95 2 (1) UIpp ps-rms UIpp ps-rms TJ = (14.1×RJSD + DJ) where RJSD is one standard deviation value of RJ Gaussian distribution. Jitter measurement is at the SATA connector and includes jitter generated at the package connection on the printed-circuit board, and at the board interconnect as shown in Figure 8. 7.6 Timing Requirements MIN TYP MAX UNIT DEVICE PARAMETERS tPDelay Propagation delay Measured using K28.5 pattern (see Figure 1) AutoLPENTRY Auto low power entry time Electrical idle at input (see Figure 3) 275 11 350 ps AutoLPEXIT Auto low power exit time After first signal activity (see Figure 3) 33 50 ns tOOB1 OOB mode enter tOOB2 OOB mode exit See Figure 2 1 5 ns See Figure 2 1 5 ns 75 ps 30 ps μs OOB RECEIVER AC/DC t20-80RX Rise and fall time Rise times and fall times measured between 20% and 80% of the signal. SATA 3 Gbps speed measured 1" from device pin. tskewRX Differential skew Difference between the single-ended mid-point of the RX+ signal rising and falling edge, and the single-ended midpoint of the RX– signal falling and rising edge. 62 TRANSMITTER AC/DC 6 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: SN75LVCP600 SN75LVCP600 www.ti.com SLLSE63A – DECEMBER 2010 – REVISED MAY 2016 Timing Requirements (continued) MIN t20-80TX Rise and fall time Rise times and fall times measured between 20% and 80% of the signal. At 3 Gbps under no load conditions measured at the pin. tskewTX Differential skew Difference between the single-ended mid-point of the TX+ signal rising edge and falling edge, and the single-ended mid-point of the TX– signal falling edge and rising edge, D1, D0 = VCC txR/Flmb TX rise and fall imbalance At 3 Gbps txAmplmb TX amplitude imbalance 44 TYP MAX UNIT 58 85 ps 2 15 ps 6% 20% 1% 10% 47.5 % 48.3 % 1.5% 3% TRANSMITTER JITTER 46.5 % Rise and Fall time Rise and Fall mismatch IN tPDelay tPDelay OUT Figure 1. Propagation Delay Timing Diagram IN+ Vcm 50 mV INtOOB2 tOOB1 OUT+ Vcm OUT- Figure 2. OOB Enter and Exit Timing RX1, 2P VCMRX RX1, 2N tOOB1 AutoLPEXIT TX1,2P VCMTX TX1,2N AutoLPENTRY Power Saving Mode Figure 3. Auto Low Power Mode Entry and Exit Timing Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: SN75LVCP600 7 SN75LVCP600 SLLSE63A – DECEMBER 2010 – REVISED MAY 2016 www.ti.com 7.7 Typical Characteristics 50 30 A function of input trace length on 4mil FR-4 45 1.5 Gbps 25 35 Deterministic Jitter - psPP Deterministic Jitter - psPP 40 42” EQ=1, DE=1 30 32” EQ=1, DE=1 25 20 24” EQ=1, DE=0 15 10 20 3 Gbps 15 6 Gbps 10 5 Function of data rate after equalizing for 32” of input FR-4 trace, EQ = 1, DE = 1 5 16” EQ=1, DE=0 0 1.5 8” EQ=1, DE=0 3.0 Data Rate - Gbps 6.0 Figure 4. Deterministic Jitter vs Data Rate 0 400 500 600 700 Launch Amplitude - mVPP 800 Figure 5. Deterministic Jitter vs Launch Amplitude 0.41 3 Gbps VOD Output Amplitude - VPP 0.40 0.39 1.5 Gbps 0.38 0.37 6 Gbps 0.36 0.35 0.34 0.33 VID = 500 mVPP, EQ = 1, DE = 1 0.32 8 16 24 32 Trace Length on 4 mil FR-4 - Inches 40 Figure 6. VOD Output Amplitude vs Trace Length 8 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: SN75LVCP600 SN75LVCP600 www.ti.com SLLSE63A – DECEMBER 2010 – REVISED MAY 2016 8 Parameter Measurement Information -RL dB Rx0. TX 0.3 4 Log Frequency - GHz 6 Figure 7. TX, RX Differential Return Loss Limits Jitter Measurement CP 40" 4mil Stripline AWG 4" 4 mil Stripline Figure 8. Jitter Measurement Test Condition Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: SN75LVCP600 9 SN75LVCP600 SLLSE63A – DECEMBER 2010 – REVISED MAY 2016 www.ti.com 9 Detailed Description 9.1 Overview The SN75LVCP600 is a single-channel, SATA Express, and PCIe signal conditioner supporting data rates up to 6 Gbps. The device supports SATA Gen 1, 2, and 3 specifications as well as PCIe 1, 2, and 3. The SN75LVCP600 operates from a single 3.3-V supply and has 100-Ω line termination with self-biasing feature, making the device suitable for AC coupling. The inputs incorporate an out-of-band (OOB) detector, which automatically squelches the output when the input differential voltage falls below threshold while maintaining a stable common-mode voltage. The device is also designed to handle spread spectrum clocking (SSC) transmission per SATA standard. The SN75LVCP600 handles interconnect losses at its input with selectable equalization settings that are programmable to match the loss in the channel. For data rates of 3 Gbps and lower the SN75LVCP600 equalizes signals for a span of up to 50 inches of FR4. For data rates of 8 Gbps the device compensates up to 40 inches of FR4. The device is hot-plug capable preventing device damage under device hot-insertion such as async signal plug or removal, unpowered plug or removal, powered plug or removal, or surprise plug or removal. 9.2 Functional Block Diagram Vcc[1] GND[5] VBB = 1.7 V TYP LVCP600 RT RX+ [2] TX+ [7] Driver Equalizer RT RX- [3] TX- [6] OOB Detect CTRL EQ [4] DE [8] Copyright © 2016, Texas Instruments Incorporated 9.3 Feature Description 9.3.1 Input Equalization The SN75LVCP600 supports programmable equalization in its front stage; Table 1 lists the equalization settings. The input equalizer is designed to recover a signal even when no eye is present at the receiver and effectively supports FR4 trace at the input anywhere from 4" to 40" at SATA 6G speed. Table 1. EQ and DE Settings EQUALIZATION (at 6 Gbps) DE 0 (default) 7 dB 0 (default) 0 dB 1 14 dB 1 –1.2 dB EQ 10 Submit Documentation Feedback DE-EMPHASIS (at 6 Gbps) Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: SN75LVCP600 SN75LVCP600 www.ti.com SLLSE63A – DECEMBER 2010 – REVISED MAY 2016 Mid Plane / Back Plane SATA Host SATA Device 10 µs. The device enters and exits Low Power Mode by actively monitoring input signal (VIDpp) level. When the input signal is in the electrical idle state, that is, VIDpp < 50 mV and stays in this state for > 10 µs, the device automatically enters the low power state. In this state the output is driven to VCM and the device selectively shuts off internal circuitry to lower power by > 90% of its normal operating power. While in ALP mode the device continues actively to monitor input signal levels. When the input signal exceeds the SATA OOB upper threshold level, the device reverts to the active state. Exit time from Auto Low Power Mode is < 50 ns (maximum). See Auto Low Power. 9.3.3 Out-of-Band (OOB) Support The squelch detector circuit within the device enables full detection of OOB signaling as specified in the SATA spec. When differential signal amplitude at the receiver input is 50 mVpp or less, the output is squelched. Differential signal amplitude of 90 mVpp or more is detected as an activity and therefore passed to the output indicating activity. Squelch circuit ON/OFF time is 5 ns (maximum). While in squelch mode outputs are held to VCM. 9.4 Device Functional Modes 9.4.1 Active Active mode is the normal operating mode. When power is applied to the device, and the differential input signal to the receiver is greater than 90 mVpp, the device is in active mode and meets all the specifications in the data sheet. 9.4.2 Squelch When the device is powered, and the differential input signal to the receiver is less than 50 mVpp, the device is in squelch mode. In squelch mode the transmitter outputs are both set to VCMTX or 1.7 V. 9.4.3 Auto Low Power When the device is powered and the differential input signal to the receiver has been less than 50 mVpp for greater than 10 ns, the device transitions to Auto Low Power (ALP) mode. In ALP, the transmitter outputs are both set to VCMTX. In addition, while in ALP, the device shuts off internal circuitry to lower power to less than 10% of the power in the Active mode. Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: SN75LVCP600 11 SN75LVCP600 SLLSE63A – DECEMBER 2010 – REVISED MAY 2016 www.ti.com 10 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 10.1 Application Information The SN75LVCP600 is a single-channel SATA redriver and signal conditioner supporting data rates up to 6 Gbps. The inputs incorporate an out-of-band (OOB) detector, which automatically squelches the output while maintaining a stable common-mode voltage compliant to the SATA link. 10.2 Typical Application 3.3 V 8 7 3 6 4 10 nF 6 3 1 5 4 7 2 8 1 10 nF 5 LVCP600 3.3 V 10 nF 10 nF 10 nF 0.01 mF 0.1 mF 1 mF LVCP600 10 nF SATA Sink SATA Host 1 1 2 0.01 mF 0.1 mF 1 mF 10 nF Note: 1) Place supply caps close to device pin 2) EQ and DE selection at 7 dB and 0dB respectively 3) Actual EQ /DE settings will depend on device placement relative to host and SATA connector Copyright © 2016, Texas Instruments Incorporated Figure 10. Typical Device Implementation 10.2.1 Design Requirements This design requires layout flexibility to place 0-Ω resistors. If a redriver is needed, go to step 3 in Detailed Design Procedure. Table 2. Design Parameters DESIGN PARAMETER 12 VALUE VCC 3.3 V ICC 29 mA Input voltage 120 mVpp to 1.6 Vpp Output voltage 400 mVpp to 900 mVpp Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: SN75LVCP600 SN75LVCP600 www.ti.com SLLSE63A – DECEMBER 2010 – REVISED MAY 2016 10.2.2 Detailed Design Procedure The LVCP600 allows the user to take the guess work of using a signal conditioning device in a SATA link. With the SN75LVCP600, the user has the option to use or remove the device based on signal conditioning needs. See Figure 11.