Product
Folder
Sample &
Buy
Support &
Community
Tools &
Software
Technical
Documents
SN75LVCP600S
SLLSE81A – MARCH 2011 – REVISED MARCH 2016
SN75LVCP600S 1.5-, 3.0-, and 6.0-Gbps SATA/SAS Redriver
1 Features
•
•
1
•
•
•
•
•
•
Single 3.3-V Supply
Suitable to Receive 6-Gbps Data Over up to >40
Inches (1 m) of FR4 PCB
Two-Level RX and TX Equalization
– RX→ 7, 15 dB
– TX→ 0, –1.3 dB
Pin-Selectable SATA/SAS Signaling
Programmable Squelch Threshold for Long
Channels
Low Power in Active, Partial, and Slumber States
– 106 mW Typical (Active Mode at 6 Gbps)
– 40 inches (1 m) of FR4
material. Rx/Tx equalization level is controlled by the
setting of signal control pins EQ and DE.
The device is hot-plug capable (requires use of ACcoupling capacitors at differential inputs and outputs),
preventing device damage during device hot-insertion
such as async signal plug/removal, unpowered
plug/removal, powered plug/removal, or surprise
plug/removal.
Device Information(1)
PART NUMBER
SN75LVCP600S
PACKAGE
SON (10)
BODY SIZE (NOM)
2.50 mm x 2.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
2 Applications
•
•
•
•
•
Notebook and Desktop PCs
Docking Stations
Active Cable
Servers
Workstations
3 Description
The SN75LVCP600S is a single-channel SATA/SAS
signal conditioner supporting data rates up to 6 Gbps.
The device complies with SATA physical spec rev 3.0
and SAS electrical spec 2.0. The SN75LVCP600S
operates from a single 3.3-V supply and has 100-Ω
line termination with a self-biasing feature, making the
device suitable for AC coupling. The inputs
incorporate an out-of-band (OOB) detector, which
automatically squelches the output while maintaining
a stable common-mode voltage compliant to the
SATA/SAS link.
SAS
Host
EQ
EQ
SATA /
SAS
Sink
~ 40 " ( 4 mil FR -4 )
EQ = LVCP600S
EQ
HDD
SAS /SATA Host
SAS
Cable
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN75LVCP600S
SLLSE81A – MARCH 2011 – REVISED MARCH 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
7
8
1
1
1
2
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 4
Electrical Characteristics........................................... 5
Timing Requirements ................................................ 7
Typical Characteristics ............................................ 10
Parameter Measurement Information ................ 11
Detailed Description ............................................ 12
8.1 Overview ................................................................. 12
8.2 Functional Block Diagram ....................................... 12
8.3 Feature Description................................................. 13
8.4 Device Functional Modes........................................ 14
9
Application and Implementation ........................ 15
9.1 Application Information............................................ 15
9.2 Typical Application ................................................. 15
9.3 System Examples ................................................... 19
10 Power Supply Recommendations ..................... 19
11 Layout................................................................... 20
11.1 Layout Guidelines ................................................. 20
11.2 Layout Example .................................................... 20
12 Device and Documentation Support ................. 21
12.1
12.2
12.3
12.4
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
21
21
21
21
13 Mechanical, Packaging, and Orderable
Information ........................................................... 21
4 Revision History
Changes from Original (March 2011) to Revision A
Page
•
Added Device Information table, ESD Ratings table, Timing Requirements table, Parameter Measurement
Information section, Detailed Description section, Application and Implementation section, Power Supply
Recommendations section, Layout section, Device and Documentation Support, Mechanical, Packaging, and
Orderable Information............................................................................................................................................................. 1
•
Changed pins TX+ and TX- I/O Type From: I, CML To: O, VML ........................................................................................... 3
•
Changed pins TX+ and TX- Description From: "Non-inverting and inverting CML differential outputs." To:
"Noninverting and inverting VML differential outputs." ........................................................................................................... 3
•
Deleted last bullet list item "The control pin pullup and pulldown resistors..." from the Layout Guidelines section ............ 20
2
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: SN75LVCP600S
SN75LVCP600S
www.ti.com
SLLSE81A – MARCH 2011 – REVISED MARCH 2016
5 Pin Configuration and Functions
DSK Package
10-Pin (SON)
Top View
1
10
SQ_TH
Vcc
2
9
DE
RX+
3
8
TX+
RX-
4
7
TX-
EQ
5
6
GND
1
MODE
Package Thermal Pad
TI recommends soldering the package thermal pad to the ground plane for maximum thermal performance.
Pin Functions
PIN
NO.
NAME
I/O TYPE
DESCRIPTION
HIGH SPEED DIFFERENTIAL I/O
3
RX+
I, CML
4
RX–
I, CML
8
TX+
O, VML
7
TX–
O, VML
Noninverting and inverting CML differential inputs. These pins are tied to an internal voltage bias by
dual termination-resistor circuit.
Noninverting and inverting VML differential outputs. These pins are tied to an internal voltage bias
by dual termination-resistor circuit.
CONTROL PINS
5
EQ
I, LVCMOS
Selects equalization settings per Table 1. Internally tied to GND
9
DE
I, LVCMOS
Selects de-emphasis settings per Table 1. Internally tied to GND
1
MODE
I, LVCMOS
Selects SATA or SAS output levels per Table 1. Internally tied to GND
10
SQ_TH
I, LVCMOS
Selects squelch threshold settings per Table 1. Internally tied to GND
POWER
2
VCC
Power
Positive supply must be 3.3 V ±10%
6
GND
Power
Supply ground
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: SN75LVCP600S
3
SN75LVCP600S
SLLSE81A – MARCH 2011 – REVISED MARCH 2016
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage
(2)
Voltage
MIN
MAX
UNIT
VCC
–0.5
4
V
Differential I/O
–0.5
4
V
Control I/O
–0.5
VCC + 0.5
V
Continuous power dissipation
See Thermal Information
Table
Storage temperature, TA
(1)
(2)
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential voltages, are with respect to the network ground terminal.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±9000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1500
Machine model (MM)
±200
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
typical values for all parameters are at VCC = 3.3 V and TA = 25°C; all temperature limits are specified by design
PARAMETER
VCC
Supply voltage
CCOUPLING
Coupling capacitor
TA
Operating free-air temperature
MIN
NOM
MAX
3
3.3
3.6
12
–40
UNITS
V
nF
85
°C
6.4 Thermal Information
SN75LVCP600S
THERMAL METRIC (1)
DSK (SON)
UNIT
10 PINS
RθJA
Junction-to-ambient thermal resistance
55.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
61.9
°C/W
RθJB
Junction-to-board thermal resistance
29.2
°C/W
ψJT
Junction-to-top characterization parameter
1.0
°C/W
ψJB
Junction-to-board characterization parameter
29.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
9.4
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: SN75LVCP600S
SN75LVCP600S
www.ti.com
SLLSE81A – MARCH 2011 – REVISED MARCH 2016
6.5 Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
DEVICE PARAMETERS
ICCMax
Active mode supply current
ICCPS
Auto power-save mode ICC
MODE/EQ/DE/SQ_TH = NC, K28.5 pattern at 6 Gbps,
VID = 700 mVpp, (SATA mode)
29
41
MODE/EQ/DE/SQ_TH = VCC, K28.5 pattern at 6 Gbps,
VID = 700 mVpp, (SAS mode)
32
45
When auto low-power conditions are met
3.3
5
mA
6
Gbps
Maximum data rate
mA
OOB
VOOB_SAS
VOOB_SATA
Input OOB threshold (output
squelched below this level)
Input OOB threshold (output
squelched below this level)
f = 750MHz; SQ_TH=0, MODE = 1,
measured at receiver pin
88
112
131
f = 750MHz; SQ_TH=1, MODE = 1,
measured at receiver pin
67
85
100
f = 750MHz; SQ_TH=0, MODE = 0,
measured at receiver pin
40
66
86
f = 750MHz; SQ_TH=1, MODE = 0,
measured at receiver pin
35
56
72
mVpp
DVdiffOOB
OOB differential delta
25
mV
DVCMOOB
OOB common-mode delta
50
mV
CONTROL LOGIC
VIH
High-level input voltage
VIL
Low-level input voltage
VINHYS
Input hysteresis
IIH
IIL
High-level input current
Low-level input current
For all control pins
1.4
V
0.5
V
115
MODE, SQ_TH = VCC
mV
30
EQ, DE = VCC
20
MODE, SQ_TH = GND
–30
EQ, DE = GND
–10
μA
RECEIVER AC/DC
ZDIFFRX
Differential input impedance
85
ZSERX
Single-ended input impedance
40
VCMRX
Common-mode voltage
RLDiffRX
RXDiffRLSlope
RLCMRX
VdiffRX
Differential mode return loss
(RL)
Differential mode RL slope
Common-mode return loss
Differential input voltage PP
100
Ω
115
Ω
1.7
f = 150 MHz–300 MHz
18
26
f = 300 MHz–600 MHz
14
23
f = 600 MHz–1.2 GHz
10
17
f = 1.2 GHz–2.4 GHz
8
14
f = 2.4 GHz–3 GHz
3
13
f = 300 MHz–6 GHz
V
dB
–13
f = 150 MHz–300 MHz
5
10
f = 300 MHz–600 MHz
5
18
f = 600 MHz–1.2 GHz
2
16
f = 1.2 GHz–2.4 GHz
1
12
f = 2.4 GHz–3 GHz
1
12
dB/dec
dB
MODE = 1, f = 1.5 GHz and 3 GHz
275
1600
MODE = 0, f = 1.5 GHz and 3 GHz
225
1600
mVpp
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: SN75LVCP600S
5
SN75LVCP600S
SLLSE81A – MARCH 2011 – REVISED MARCH 2016
www.ti.com
Electrical Characteristics (continued)
over recommended operating conditions (unless otherwise noted)
PARAMETER
IBRX
Impedance balance
TEST CONDITIONS
MIN
TYP MAX
f = 150 MHz–300 MHz
30
47
f = 300 MHz–600 MHz
30
40
f = 600 MHz–1.2 GHz
20
34
f = 1.2 GHz–2.4 GHz
10
28
f = 2.4 GHz–3. GHz
10
24
f = 3 GHz–5 GHz
4
22
f = 5 GHz–6.5 GHz
4
22
100
UNIT
dB
TRANSMITTER AC/DC
ZdiffTX
Pair differential impedance
85
ZSETX
Single-ended input impedance
40
VTXtrans
Sequencing transient voltage
RLDiffTX
Differential mode return loss
TXDiffRLSlope
RLCMTX
Differential-mode RL slope
Common-mode return loss
Transient voltages on the serial data bus during power
sequencing (lab load)
0
f = 150 MHz–300 MHz
13
22
f = 300 MHz–600 MHz
8
21
f = 600 MHz–1.2 GHz
6
20
f = 1.2 GHz–2.4 GHz
6
17
f = 2.4 GHz–3 GHz
3
17
IBTX
Impedance balance
DiffVppTX
DE
Differential output-voltage
swing
De-emphasis level
VCMAC_TX
TX AC CM voltage
VCMTX
Common-mode voltage
TxR/Flmb
TX rise/fall imbalance
TxAmplmb
TX amplitude imbalance
6
1.2
5
19
f = 300 MHz–600 MHz
5
16
f = 600 MHz–1.2 GHz
2
11
f = 1.2 GHz–2.4 GHz
1
9
1
10
f = 150 MHz–300 MHz
30
43
f = 300 MHz–600 MHz
30
40
f = 600 MHz–1.2 GHz
20
32
f = 1.2 GHz–2.4 GHz
10
25
f = 2.4 GHz–3 GHz
10
27
f = 3 GHz–5 GHz
4
25
f = 5. GHz–6.5 GHz
4
26
V
dB
–13
f = 150 MHz–300 MHz
f = 2.4 GHz–3 GHz
Ω
Ω
–1.2
f = 300 MHz–3 GHz
122
dB/dec
dB
dB
DE = 1, MODE = 1→(SAS), f = 3 GHz
(under no interconnect loss)
385
850 1300
DE = 0, MODE = 0→(SATA), f = 3 GHz
(under no interconnect loss)
400
600
mVpp
DE = 1
–1.3
DE = 0
0
800
dB
At 1.5 GHz
20
50
mVpp
At 3 GHz
11
26
At 6 GHz
13
30
dBmv
(rms)
At 3 Gbps
3%
18%
1.5%
10%
1.7
Submit Documentation Feedback
V
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: SN75LVCP600S
SN75LVCP600S
www.ti.com
SLLSE81A – MARCH 2011 – REVISED MARCH 2016
Electrical Characteristics (continued)
over recommended operating conditions (unless otherwise noted)
PARAMETER
TRANSMITTER JITTER AT CP
TEST CONDITIONS
MIN
TYP MAX
UNIT
0.26
0.38
UIpp
(1)
3-Gbps SATA Mode
TJTX
Total jitter (1)
DJTX
Deterministic jitter
VID = 500 mVpp, UI = 333 ps, K28.5 control character,
EQ/DE = 1
0.13
0.24
UIpp
RJTX
Residual random jitter
VID = 500 mVpp, UI = 333 ps, K28.7 control character,
EQ/DE = 1
1.16
1.95
ps-rms
6-Gbps SATA Mode
TJTX
Total jitter (1)
DJTX
Deterministic jitter
VID = 500 mVpp, UI = 167 ps, K28.5 control character,
EQ/DE = 1
RJTX
Residual random jitter
VID = 500 mVpp, UI = 167 ps, K28.7 control character,
EQ/DE = 1
0.37
0.61
UIpp
0.12
0.32
UIpp
1.15
2.2
ps-rms
3-Gbps SAS Mode
TJTX
Total jitter (1)
DJTX
Deterministic jitter
VID = 500 mVpp, UI = 333 ps, K28.5 control character,
EQ/DE = 1
RJTX
Residual random jitter
VID = 500 mVpp, UI = 333 ps, K28.7 control character,
EQ/DE = 1
0.25
0.37
UIpp
0.12
0.23
UIpp
1.11
2
0.35
0.57
UIpp
ps-rms
6-Gbps SAS Mode
TJTX
Total jitter (1)
DJTX
Deterministic jitter
VID = 500 mVpp, UI = 167 ps, K28.5 control character,
EQ/DE = 1
0.10
0.29
UIpp
RJTX
Residual random jitter
VID = 500 mVpp, UI = 167 ps, K28.7 control character,
EQ/DE = 1
1.1
2.14
ps-rms
(1)
TJ = (14.1 × RJSD + DJ), where RJSD is one standard deviation value of RJ Gaussian distribution. Jitter measurement is at the CP
connector and includes jitter generated at the package connection on the printed circuit board, and at the board interconnect as shown
in Figure 1.
6.6 Timing Requirements
MIN
NOM
MAX
UNIT
DEVICE PARAMETERS
tPDelay
Propagation delay
Measured using K28.5 pattern, See Figure 3
280
330
ps
AutoLPENTRY
Auto low power entry time
Electrical idle at input, See Figure 5
11
20
μs
AutoLPEXIT
Auto low power exit time
After first signal activity, See Figure 5
30
40
ns
tOOB1
OOB mode enter
See Figure 4
3
8
ns
tOOB2
OOB mode exit
See Figure 4
3
8
ns
75
ps
30
ps
50
76
ps
4
14
ps
OOB
RECEIVER AC/DC
t20-80RX
Rise and fall time
Rise times and fall times measured between 20% and 80%
of the signal. SATA/SAS 6 Gbps speed measured 1 inch
(2.54 cm) from device pin
tskewRX
Differential skew
Difference between the single-ended mid-point of the RX+
signal rising/falling edge, and the single-ended mid-point of
the RX– signal falling/rising edge
62
TRANSMITTER AC/DC
t20-80TX
Rise and fall time
Rise times and fall times measured between 20% and 80%
of the signal. At 6 Gbps SATA or SAS, under no load,
measured at the pin
tskewTX
Differential skew
Difference between the single-ended mid-point of the TX+
signal rising/falling edge, and the single-ended mid-point of
the TX– signal falling/rising edge, SATA or SAS mode
33
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: SN75LVCP600S
7
SN75LVCP600S
SLLSE81A – MARCH 2011 – REVISED MARCH 2016
www.ti.com
Jitter
Measurement
CP
40" 4mil
Stripline
AWG
4" 4 mil Stripline
Figure 1. Jitter Measurement Test Condition
-RL
dB
TX
0.30
RX
3
Log Frequency - GHz
6
Figure 2. TX, RX Differential Return Loss Limits
IN
tPDelay
tPDelay
OUT
Figure 3. Propagation Delay Timing Diagram
8
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: SN75LVCP600S
SN75LVCP600S
www.ti.com
SLLSE81A – MARCH 2011 – REVISED MARCH 2016
IN+
Vcm
50mV
INtOOB
tOOB
OUT+
Vcm
OUT-
Figure 4. OOB Enter and Exit Timing
RXP
VCMRX
RXN
tOOB
AutoLPEXIT
TXP
VCMTX
TXN
AutoLPENTRY
Power Saving
Mode
Figure 5. Auto Low-Power Mode Entry and Exit Timing
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: SN75LVCP600S
9
SN75LVCP600S
SLLSE81A – MARCH 2011 – REVISED MARCH 2016
www.ti.com
6.7 Typical Characteristics
30
50
45
25
Deterministic Jitter (psP−P)
40
Deterministic Jitter (psP−P)
As a function of data rate after equalizing
for 32 in. of input FR−4 trace EQ = 1, DE = 1
8 in., EQ =1, DE = 0
16 in., EQ =1, DE = 0
24 in., EQ =1, DE = 0
32 in., EQ =1, DE = 1
40 in., EQ =1, DE = 1
35
30
25
20
15
10
20
15
10
5
1.5 Gbps
3 Gbps
6 Gbps
5
As a function of input trace length on 4mil FR−4
0
1
1.5
2
2.5
3 3.5
4 4.5
Data Rate (Gbps)
5
5.5
6
0
300
6.5
500
600
700
800
900
Launch Amplitude (mVP−P)
Figure 6. SATA-Mode Deterministic Jitter vs Data Rate
Figure 7. SATA-Mode Deterministic Jitter vs Launch
Amplitude
40
50
As a function of data rate after equalizing
for 32 in. of input FR−4 trace EQ = 1, DE = 0
8 in., EQ =1, DE = 0
16 in., EQ =1, DE = 0
24 in., EQ =1, DE = 0
32 in., EQ =1, DE = 0
40 in., EQ =1, DE = 1
45
35
30
Deterministic Jitter (psP−P)
40
Deterministic Jitter (psP−P)
400
35
30
25
20
15
25
20
15
10
10
1.5 Gbps
3 Gbps
6 Gbps
5
5
As a function of trace length on FR−4
0
1
1.5
2
2.5
3 3.5
4 4.5
Data Rate (Gbps)
5
5.5
6
6.5
400
500
600
700
800
900
Launch Amplitude (mVP−P)
Figure 8. SAS-Mode Deterministic Jitter vs Data Rate
10
0
300
Figure 9. SAS-Mode Deterministic Jitter vs Launch
Amplitude
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: SN75LVCP600S
SN75LVCP600S
www.ti.com
SLLSE81A – MARCH 2011 – REVISED MARCH 2016
7 Parameter Measurement Information
LVCP600S
LVCP600S Output
Input (variable )
4 mil
Pattern
generator
A.
Output
EQ
DE
= 2 " ( fixed )
Oscilloscope
LVCP600S Input
VCC = 3.3 V; INPUT = K28.5 pattern at 1.5 Gbps, 3 Gbps, and 6 Gbps; VID = 1000 mVpp; TEMP = 25°C; TRACE
WIDTH = 4 mil (0.1 mm)
Figure 10. Eye Diagram Measurement Setup for LVCP600S
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: SN75LVCP600S
11
SN75LVCP600S
SLLSE81A – MARCH 2011 – REVISED MARCH 2016
www.ti.com
8 Detailed Description
8.1 Overview
The SN75LVCP600S is a single-channel SATA/SAS signal conditioner supporting data rates up to 6 Gbps with
an extended temperature range from –40°C to 85°C. The device complies with SATA physical spec rev 3.0 and
SAS electrical spec 2.0. The SN75LVCP600S operates from a single 3.3-V supply and has 100-Ω line
termination with a self-biasing feature, making the device suitable for AC coupling. The inputs incorporate an outof-band (OOB) detector, which automatically squelches the output while maintaining a stable common-mode
voltage compliant to the SATA/SAS link.
The SN75LVCP600S handles interconnect losses at its input with selectable equalization settings that can be
programmed to the match loss in the channel. For data rates of 3 Gbps and lower, the LVCP600S equalizes
signals for a span of up to 50 inches of FR4 board material. For data rates of 6 Gbps, the device compensates
>40 inches (1 m) of FR4 material. Rx/Tx equalization level is controlled by the setting of signal control pins EQ
and DE.
The device is hot-plug capable, preventing device damage during device hot-insertion such as async signal
plug/removal, unpowered plug/removal, powered plug/removal, or surprise plug/removal.
8.2 Functional Block Diagram
Vcc[2]
GND[6]
VBB = 1.7 V TYP
LVCP600S
RT
RX+ [3]
TX+ [8]
Driver
Equalizer
RT
RX- [4]
TX- [7]
OOB
Detect
CTRL
MODE DE EQ SQ_TH
[1] [9] [5] [10]
Copyright © 2016, Texas Instruments Incorporated
12
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: SN75LVCP600S
SN75LVCP600S
www.ti.com
SLLSE81A – MARCH 2011 – REVISED MARCH 2016
8.3 Feature Description
8.3.1 Input Equalization
The SN75LVCP600S supports programmable equalization in its front stage; the equalization settings are shown
in Table 1. The input equalizer is designed to recover a signal even when no eye is present at the receiver and
effectively supports FR4 trace at the input anywhere from 4 inches (0.1 m) to 40 (1 m) at SATA 6-Gbps speed. In
SAS mode, the device meets compliance point IR in a TX/RX connection.
SAS Drive Plug
LVCP600S
IR
SAS Mode
Transmitter Device
Compliance Point (IR)
signal going to receiver device
as measured at this point
Main Board/Backplane
SAS Receptacle
Figure 11. Compliance Point In SAS Mode
8.3.2 Auto Low-Power (ALP) Mode (see Figure 5)
As a redriver, the SN75LVCP600S does not participate in SATA or SAS link power management (PM) states.
However, the redriver tracks link-power management mode (partial and slumber) by relying on the link differential
voltage, VIDp-p. The SATA/SAS link is continuously sending and receiving data even in long periods of disk
inactivity by sending SYNC primitives (logical idle), except when the link enters partial or slumber mode. In these
modes, the link is in an electrical-idle state (EID). The device input squelch detector tracks EID status. When the
input signal is in the electrical idle state, that is, VIDp-p 10
µS, the device automatically enters the low power state. In this state, the output is driven to VCM and the device
selectively shuts off internal circuitry to lower power consumption by approximately 90% of its normal operating
power. While in ALP mode, the device continues to monitor input signal levels actively; when the input signal
exceeds the SATA/SAS OOB upper threshold level, the device reverts to the active state. Exit time from auto
low-power mode is
工商网监
湘ICP备2023018690号
