SN74HC05, SN54HC05
SN54HC05
SCLS080F – MARCHSN74HC05,
1984 – REVISED
APRIL 2021
SCLS080F – MARCH 1984 – REVISED APRIL 2021
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SNx4HC05 Hex Inverters with Open-Drain Outputs
1 Features
3 Description
•
•
•
This device contains six independent inverters with
open-drain outputs. Each gate performs the Boolean
function Y = A in positive logic.
•
•
Buffered inputs
Wide operating voltage range: 2 V to 6 V
Wide operating temperature range:
–40°C to +85°C
Supports fanout up to 10 LSTTL loads
Significant power reduction compared to LSTTL
logic ICs
2 Applications
•
•
Synchronize inverted clock inputs
Invert a digital signal
Device Information(1)
PART NUMBER
SOIC (14)
8.70 mm × 3.90 mm
SN74HC05NR
PDIP (14)
19.30 mm × 6.40 mm
SN74HC05NSR
SO (14)
10.20 mm × 5.30 mm
SN74HC05PWR
TSSOP (14)
5.00 mm × 4.40 mm
SN54HC05JR
CDIP (14)
21.30 mm × 7.60 mm
SN54HC05FKR
LCCC (20)
8.90 mm × 8.90 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
1A
1
14
1Y
2
13
6A
2A
3
4
12
11
6Y
3A
5
10
5Y
3Y
6
7
9
8
4A
GND
BODY SIZE (NOM)
SN74HC05DR
(1)
2Y
PACKAGE
VCC
5A
4Y
Functional pinout
An©IMPORTANT
NOTICEIncorporated
at the end of this data sheet addresses availability, warranty, changes, use in
safety-critical
applications,
Copyright
2021 Texas Instruments
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
Pin Functions.................................................................... 3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics - 74..................................... 5
6.6 Electrical Characteristics - 54..................................... 5
6.7 Switching Characteristics - 74.....................................6
6.8 Switching Characteristics - 54.....................................6
6.9 Operating Characteristics........................................... 7
6.10 Typical Characteristics.............................................. 7
7 Parameter Measurement Information............................ 8
8 Detailed Description........................................................9
8.1 Overview..................................................................... 9
8.2 Functional Block Diagram........................................... 9
8.3 Feature Description.....................................................9
8.4 Device Functional Modes..........................................10
9 Application and Implementation.................................. 11
9.1 Application Information..............................................11
9.2 Typical Application.................................................... 11
10 Power Supply Recommendations..............................13
11 Layout........................................................................... 13
11.1 Layout Guidelines................................................... 13
11.2 Layout Example...................................................... 13
12 Device and Documentation Support..........................14
12.1 Documentation Support.......................................... 14
12.2 Support Resources................................................. 14
12.3 Trademarks............................................................. 14
12.4 Electrostatic Discharge Caution..............................14
12.5 Glossary..................................................................14
13 Mechanical, Packaging, and Orderable
Information.................................................................... 14
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (March 2015) to Revision F (April 2021)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Updated to new data sheet standards................................................................................................................ 1
• RθJA increased for the D, NS, and PW packages and decreased for the N package......................................... 5
Changes from Revision D (August 2003) to Revision E (March 2015)
Page
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ............................................................................................................................................................... 1
2
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5 Pin Configuration and Functions
1Y 1A NC VCC 6A
1A
1
14
VCC
1Y
2
13
6A
2A
3
12
6Y
2A
4
3
2
1
20 19
18
6Y
NC
5
17
NC
5A
2Y
4
11
5A
3A
5
10
5Y
2Y
6
16
3Y
6
9
4A
NC
7
15
NC
GND
7
8
4Y
3A
8
14
9 10 11 12 13
5Y
Figure 5-1. D, N, NS, PW, or J Package
14-Pin SOIC, PDIP, SO, TSSOP, or CDIP
Top View
3Y GND NC 4Y 4A
Figure 5-2. FK Package
20-Pin LCCC
Top View
Pin Functions
PIN
I/O
D, N, NS,
PW, or J
FK
1A
1
2
Input
1Y
2
3
Output
2A
3
4
Input
2Y
4
6
Output
3A
5
8
Input
NAME
DESCRIPTION
Channel 1, Input A
Channel 1, Output Y
Channel 2, Input A
Channel 2, Output Y
Channel 3, Input A
3Y
6
9
Output
GND
7
10
—
4Y
8
12
Output
4A
9
13
Input
5Y
10
14
Output
5A
11
16
Input
6Y
12
18
Output
6A
13
19
Input
VCC
14
20
—
Positive Supply
1, 5, 7, 11, 15,
17
—
Not internally connected
NC
Channel 3, Output Y
Ground
Channel 4, Output Y
Channel 4, Input A
Channel 5, Output Y
Channel 5, Input A
Channel 6, Output Y
Channel 6, Input A
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
VCC
Supply voltage
current(2)
MIN
MAX
–0.5
7
UNIT
V
IIK
Input clamp
VI < 0 or VI > VCC
±20
mA
IOK
Output clamp current(2)
VO < 0 or VO > VCC
±20
mA
Continuous output current
VO = 0 to VCC
IO
Continuous current through VCC or GND
TJ
Junction temperature(3)
Tstg
Storage temperature
(1)
(2)
(3)
–65
±25
mA
±50
mA
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
Guaranteed by design.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Human-body model (HBM), per ANSI/ESDA/
JEDEC JS-001(1)
Electrostatic discharge
UNIT
±1000
V
Charged-device model (CDM), per JEDEC
specification JESD22-C101(2)
–
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VCC
Supply voltage
VIH
High-level input voltage
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
MIN
NOM
MAX
2
5
6
Low-level input voltage
V
4.2
0.5
VCC = 4.5 V
1.35
VCC = 6 V
V
1.8
VI
Input voltage
0
VCC
V
VO
Output voltage
0
VCC
V
VCC = 2 V
Δt/Δv
TA
4
V
1.5
3.15
VCC = 2 V
VIL
UNIT
Input transition rise and fall rate
Operating free-air temperature
1000
VCC = 4.5 V
500
VCC = 6 V
400
SN54HC05
–55
125
SN74HC05
–40
125
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°C
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6.4 Thermal Information
SN74HC05
THERMAL
METRIC(1)
D (SOIC)
N (PDIP)
NS (SOP)
PW (TSSOP)
14 PINS
14 PINS
14 PINS
14 PINS
UNIT
133.6
62.6
122.6
151.7
°C/W
RθJA
Junction-to-ambient thermal
resistance
RθJC(top)
Junction-to-case (top) thermal
resistance
89.0
50.3
81.8
79.4
°C/W
RθJB
Junction-to-board thermal
resistance
89.5
42.3
83.8
94.7
°C/W
ΨJT
Junction-to-top characterization
parameter
45.5
30.0
45.4
25.2
°C/W
ΨJB
Junction-to-board characterization
parameter
89.1
42.1
83.4
94.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal
resistance
N/A
N/A
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics - 74
over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
Operating free-air temperature (TA)
PARAMETER
TEST CONDITIONS
VCC
25°C
MIN
IOH
Output voltage
VI = VIH or
VO = VCC
VIL
6V
IOL = 20
µA
VOL
Low-level output VI = VIH or
voltage
VIL
–40°C to 85°C
TYP
MAX
0.01
0.5
MIN
TYP
–40°C to 125°C
MAX
MIN
TYP
UNIT
MAX
5
5
2V
0.002
0.1
0.1
0.1
4.5 V
0.001
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
IOL = 4 mA 4.5 V
0.17
0.26
0.33
0.33
IOL = 5.2
mA
0.15
0.26
0.33
0.33
6V
µA
V
II
Input leakage
current
VI = VCC or 0
6V
±0.1
±1
±1
µA
ICC
Supply current
VI = VCC or
IO = 0
0
6V
2
20
20
µA
Ci
Input
capacitance
10
10
10
pF
2 V to
6V
3
6.6 Electrical Characteristics - 54
over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
Operating free-air temperature (TA)
PARAMETER
TEST CONDITIONS
25°C
VCC
MIN
IOH
Output voltage
VI = VIH or
VO = VCC
VIL
6V
–40°C to 85°C
TYP
MAX
0.01
0.5
MIN
TYP
–55°C to 125°C
MAX
5
MIN
TYP
UNIT
MAX
10
µA
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over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
Operating free-air temperature (TA)
PARAMETER
TEST CONDITIONS
VCC
25°C
MIN
VOL
TYP
MAX
MIN
TYP
UNIT
TYP
MAX
0.002
0.1
0.1
0.1
4.5 V
0.001
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
IOL = 4 mA 4.5 V
0.17
0.26
0.33
0.4
IOL = 5.2
mA
0.15
0.26
0.33
0.4
6V
MIN
–55°C to 125°C
2V
IOL = 20
µA
Low-level output VI = VIH or
voltage
VIL
–40°C to 85°C
MAX
V
II
Input leakage
current
VI = VCC or 0
6V
±0.1
±1
±1
µA
ICC
Supply current
VI = VCC or
IO = 0
0
6V
2
20
40
µA
Ci
Input
capacitance
10
10
10
pF
2 V to
6V
3
6.7 Switching Characteristics - 74
over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
Operating free-air temperature (TA)
PARAMETER
FROM
TO
VCC
25°C
MIN
tPLH
tPHL
tt
Propagation delay low-tohigh
Propagation delay high-tolow
A
A
Transition-time
Y
Y
MIN
TYP
–40°C to 125°C
MAX
2V
60
115
145
160
4.5 V
13
23
29
31
6V
10
20
25
28
2V
45
85
105
120
9
17
21
23
4.5 V
Y
–40°C to 85°C
TYP
MAX
MIN
TYP
UNIT
MAX
6V
8
14
18
21
2V
38
75
95
110
4.5 V
8
15
19
22
6V
6
13
16
19
ns
ns
ns
6.8 Switching Characteristics - 54
over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
Operating free-air temperature (TA)
PARAMETER
FROM
TO
25°C
VCC
MIN
tPLH
tPHL
tt
6
Propagation delay low-tohigh
Propagation delay high-tolow
Transition-time
A
Y
A
Y
–40°C to 85°C
MIN
TYP
–55°C to 125°C
TYP
MAX
MAX
MIN
TYP
2V
60
115
145
175
4.5 V
13
23
29
35
6V
10
20
25
30
2V
45
85
105
130
4.5 V
9
17
21
26
6V
8
14
18
22
2V
38
75
95
110
4.5 V
8
15
19
22
6V
6
13
16
19
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UNIT
MAX
ns
ns
ns
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6.9 Operating Characteristics
over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
No load
per gate
VCC
MIN
2 V to 6 V
TYP
20
MAX UNIT
pF
6.10 Typical Characteristics
TA = 25°C
VOL Output Low Voltage (V)
0.3
2-V
4.5-V
6-V
0.25
0.2
0.15
0.1
0.05
0
0
1
2
3
4
IOL Output Low Current (mA)
5
6
Figure 6-1. Typical output voltage in the low state (VOL)
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7 Parameter Measurement Information
•
•
Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns.
The outputs are measured one at a time, with one input transition per measurement.
VCC
Test
Point
90%
Input
10%
10%
S1
tr(1)
RL
From Output
Under Test
0V
tf(1)
90%
CL(1)
VOH
90%
Output
10%
A.
VCC
90%
10%
tr(1)
CL= 50 pF and includes probe and jig capacitance.
A.
Figure 7-1. Load Circuit
tf(1)
VOL
tt is the greater of tr and tf.
Figure 7-2. Voltage Waveforms Transition Times
VCC
Input
50%
50%
0V
tPLZ(1)
tPZL(2)
VOH
Output
50%
10% VCC
tPZL
(2)
VOL
tPLZ
(1)
VOH
Output
50%
10%
VOL
A.
The maximum between tPLH and tPHL is used for tpd.
Figure 7-3. Voltage Waveforms Propagation Delays
8
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8 Detailed Description
8.1 Overview
This device contains six independent inverters with open-drain outputs. Each gate performs the Boolean function
Y = A in positive logic.
8.2 Functional Block Diagram
xA
xY
8.3 Feature Description
8.3.1 CMOS Open-Drain Outputs
The open-drain output allows the device to sink current to GND but not to source current from VCC. When the
output is not actively pulling the line low, it will go into a high impedance state. This allows the device to be used
for a wide variety of applications, including up-translation and down-translation, as the output voltage can be
determined by an external pull-up resistor.
The current drive capability of this device creates fast edges into light loads, so routing and load conditions
should be considered to prevent ringing. Additionally, the outputs of this device are capable of driving larger
currents than the device can sustain without being damaged. It is important for the power output of the device
to be limited to avoid thermal runaway and damage due to over-current. The electrical and thermal limits defined
the in the Absolute Maximum Ratingsmust be followed at all times.
The SN74HC05 can drive a load with a total capacitance less than or equal to the maximum load listed in
the Switching Characteristics - 74 connected to a high-impedance CMOS input while still meeting all of the
datasheet specifications. Larger capacitive loads can be applied, however it is not recommended to exceed the
provided load value. If larger capacitive loads are required, it is recommended to add a series resistor between
the output and the capacitor to limit output current to the values given in the Absolute Maximum Ratings.
8.3.2 Standard CMOS Inputs
Standard CMOS inputs are high impedance and are typically modeled as a resistor from the input to ground
in parallel with the input capacitance given in the Electrical Characteristics - 74. The worst case resistance is
calculated with the maximum input voltage, given in the Absolute Maximum Ratings, and the maximum input
leakage current, given in the Electrical Characteristics - 74, using ohm's law (R = V ÷ I).
Signals applied to the inputs need to have fast edge rates, as defined by the input transition time in the
Recommended Operating Conditions to avoid excessive current consumption and oscillations. If a slow or noisy
input signal is required, a device with a Schmitt-trigger input should be used to condition the input signal prior to
the standard CMOS input.
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8.3.3 Clamp Diode Structure
The inputs and outputs to this device have both positive and negative clamping diodes as depicted in Figure 8-1.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to
the device. The recommended input and output voltage ratings may be exceeded if the input and
output clamp-current ratings are observed.
Device
VCC
+IIK
+IOK
Logic
Input
Output
-IIK
-IOK
GND
Figure 8-1. Electrical Placement of Clamping Diodes for Each Input and Output
8.4 Device Functional Modes
Table 8-1. Function Table
10
INPUT
OUTPUT
A
Y
L
Hi-Z
H
L
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
In this application, one open-drain inverter is used as shown in Figure 9-1. The other five channels can be used
for other applications in the system, or the inputs can be grounded and the channels left unused.
This device is used to directly control an LED. The LED is on when the input is high, and off when the input is
low.
9.2 Typical Application
VCC
R1
VCC
Input
Figure 9-1. Typical application schematic
9.2.1 Design Requirements
9.2.1.1 Power Considerations
Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions. The
supply voltage sets the device's electrical characteristics as described in the Electrical Characteristics - 74.
The ground must be capable of sinking current equal to the total current to be sunk by all outputs of the
SN74HC05 plus the maximum supply current, ICC, listed in Electrical Characteristics - 74. The logic device can
only sink as much current as is provided by the external pull-up resistor or other supply source. Be sure not to
exceed the maximum total current through GND listed in the Absolute Maximum Ratings.
Total power consumption can be calculated using the information provided in CMOS Power Consumption and
Cpd Calculation.
Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear
and Logic (SLL) Packages and Devices.
CAUTION
The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings, is an
additional limitation to prevent damage to the device. Do not violate any values listed in the Absolute
Maximum Ratings. These limits are provided to prevent damage to the device.
9.2.1.2 Input Considerations
Unused inputs must be terminated to either VCC or ground. These can be directly terminated if the input is
completely unused, or they can be connected with a pull-up or pull-down resistor if the input is to be used
sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is
used for a default state of LOW. The resistor size is limited by drive current of the controller, leakage current into
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the SN74HC05, as specified in the Electrical Characteristics - 74, and the desired input transition rate. A 10-kΩ
resistor value is often used due to these factors.
The SN74HC05 has standard CMOS inputs, so input signal edge rates cannot be slow. Slow input edge
rates can cause oscillations and damaging shoot-through current. The recommended rates are defined in the
Recommended Operating Conditions.
Refer to Section 8.3 for additional information regarding the inputs for this device.
9.2.1.3 Output Considerations
The ground voltage is used to produce the output LOW voltage. Sinking current into the output will increase the
output voltage as specified by the VOL specification in the Electrical Characteristics - 74. The plot in provides a
typical relationship between output voltage and current for this device.
Open-drain outputs can be directly connected together to produce a wired-AND. This is possible because the
outputs cannot source current, and thus can never be in bus-contention.
Unused outputs can be left floating. Do not connect outputs directly to VCC or ground.
Refer to Section 8.3 for additional information regarding the outputs for this device.
9.2.2 Detailed Design Procedure
1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the
device and electrically close to both the VCC and GND pins. An example layout is shown in Section 11.
2. Ensure the capacitive load at the output is ≤ 70 pF. This is not a hard limit, however it will ensure optimal
performance. This can be accomplished by providing short, appropriately sized traces from the SN74HC05
to the receiving device.
3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum
output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load
measured in megaohms; much larger than the minimum calculated above.
4. Thermal issues are rarely a concern for logic gates, however the power consumption and thermal increase
can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd
Calculation
9.2.3 Application Curves
Input
Output
LED Status
OFF
ON
OFF
ON
Figure 9-2. Typical application timing diagram
12
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10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in
the Recommended Operating Conditions. Each VCC terminal should have a bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results, as shown in
Figure 11-1.
11 Layout
11.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of
a triple-input AND gate are used. Such unused input pins must not be left unconnected because the undefined
voltages at the outside connections result in undefined operational states. All unused inputs of digital logic
devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to
prevent them from floating. The logic level that must be applied to any particular unused input depends on the
function of the device. Generally, the inputs are tied to GND or VCC, whichever makes more sense for the logic
function or is more convenient.
11.2 Layout Example
GND
VCC
Recommend GND flood fill for
improved signal isolation, noise
reduction, and thermal dissipation
0.1 F
Unused input
tied to GND
Avoid 90°
corners for
signal lines
Bypass capacitor
placed close to
the device
1A
1
14
1Y
2
13
VCC Unused input
tied to VCC
6A
2A
3
12
6Y
2Y
4
11
5A
3A
5
10
5Y
3Y
6
9
4A
GND
7
8
4Y
Unused output
left floating
Figure 11-1. Example layout for the SN74HC05
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Product Folder Links: SN74HC05 SN54HC05
13
SN74HC05, SN54HC05
www.ti.com
SCLS080F – MARCH 1984 – REVISED APRIL 2021
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• HCMOS Design Considerations
• CMOS Power Consumption and CPD Calculation
• Designing with Logic
12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
14
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: SN74HC05 SN54HC05
PACKAGE OPTION ADDENDUM
www.ti.com
14-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
5962-88718012A
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
596288718012A
SNJ54HC
05FK
5962-8871801CA
ACTIVE
CDIP
J
14
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-8871801CA
SNJ54HC05J
SN54HC05J
ACTIVE
CDIP
J
14
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
SN54HC05J
SN74HC05D
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HC05
SN74HC05DE4
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HC05
SN74HC05DR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
HC05
SN74HC05DRG4
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HC05
SN74HC05DT
ACTIVE
SOIC
D
14
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HC05
SN74HC05DTG4
ACTIVE
SOIC
D
14
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HC05
SN74HC05N
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 125
SN74HC05N
SN74HC05NE4
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 125
SN74HC05N
SN74HC05NSR
ACTIVE
SO
NS
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HC05
SN74HC05NSRE4
ACTIVE
SO
NS
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HC05
SN74HC05PWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
HC05
SN74HC05PWRG4
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HC05
SN74HC05PWT
ACTIVE
TSSOP
PW
14
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HC05
SNJ54HC05FK
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
596288718012A
SNJ54HC
05FK
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
14-Aug-2021
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
(4/5)
(6)
SNJ54HC05J
ACTIVE
CDIP
J
14
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-8871801CA
SNJ54HC05J
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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