THS3202
DGN-8
DGK-8
D-8
www.ti.com
SLOS242F – SEPTEMBER 2002 – REVISED JANUARY 2010
2-GHz, LOW DISTORTION, DUAL CURRENT-FEEDBACK AMPLIFIERS
Check for Samples: THS3202
FEATURES
DESCRIPTION
•
•
•
•
The THS3202 is a dual current-feedback amplifier
developed with BiCOM-II technology. Designed for
low distortion with a high slew rate of 9000 V/µs, the
THS320x family is ideally suited for applications
driving loads sensitive to distortion at high
frequencies.
1
23
Unity-Gain Bandwidth: 2 GHz
High Slew Rate: 9000 V/µs
High Output Current: ±115 mA into 20 Ω RL
Power-Supply Voltage Range: 6.6 V to 15 V
APPLICATIONS
•
•
•
•
•
The
THS3202
provides
well-regulated
ac
performance characteristics with power supplies
ranging from single-supply 6.6-V operation up to a
15-V supply. The high unity-gain bandwidth of up to
2 GHz is a major contributor to the excellent distortion
performance. The THS3202 offers an output current
drive of ±115 mA and a low differential gain and
phase error that make it suitable for applications such
as video line drivers.
High-Speed Signal Processing
Test and Measurement Systems
High-Voltage ADC Preamplifier
RF and IF Amplifier Stages
Professional Video
LARGE-SIGNAL
FREQUENCY RESPONSE
14
12
The THS3202 is available in an SOIC-8, an MSOP-8,
and an MSOP-8 with PowerPAD™ packages.
VO = 4 VPP
Normalized Amplitude - dB
10
8
6
RELATED DEVICES AND DESCRIPTIONS
VO = 2 VPP
4
2
0
VO = 1 VPP
-2
-4
-6
-8
-10 G = 2
VCC = ±5
-12 RL = 100 W
-14
100 k
1M
THS3001
±15-V 420-MHz Low Distortion CFB Amplifier
THS3061/2
±15-V 300-MHz Low Distortion CFB Amplifier
THS3122
±15-V Dual CFB Amplifier With 350 mA Drive
THS4271
+15-V 1.4-GHz Low Distortion VFB Amplifier
VO = 0.25 VPP
10 M
100 M
1G
10 G
f - Frequency - Hz
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2010, Texas Instruments Incorporated
THS3202
SLOS242F – SEPTEMBER 2002 – REVISED JANUARY 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION (1)
ORDERABLE PACKAGE AND NUMBER
(1)
(2)
NUMBER OF
CHANNELS
PLASTIC SOIC-8 (2)
(D)
2
THS3202D
PLASTIC MSOP-8 (2) PowerPAD
PLASTIC MSOP-8 (2)
(DGN)
MARKING
(DGK)
MARKING
THS3202DGN
BEP
THS3202DGK
BEV
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (that is, THS3202DR).
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range, unless otherwise noted.
UNIT
Supply voltage, VS
16.5 V
Input voltage, VI
±VS
Differential input voltage, VID
±3 V
Output current, IO (2)
175 mA
Continuous power dissipation
See Package Dissipation Ratings Table
Maximum junction temperature, TJ (3)
+150°C
Maximum junction temperature, continuous operation, long-term reliability, TJ (4)
+125°C
Operating free-air temperature range, TA
–40°C to +85°C
Storage temperature range, TSTG
–65°C to +150°C
ESD ratings:
(1)
(2)
(3)
(4)
2
HBM
3000 V
CDM
1500 V
MM
200 V
The absolute maximum ratings under any condition is limited by the constraints of the silicon process. Stresses above these ratings may
cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.
The THS3202 may incorporate a PowerPAD on the underside of the chip. This acts as a heat sink and must be connected to a
thermally dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature
which could permanently damage the device. See TI technical briefs SLMA002 and SLMA004 for more information about using the
PowerPAD thermally-enhanced package.
The absolute maximum temperature under any condition is limited by the constraints of the silicon process.
The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may
result in reduced reliability and/or lifetime of the device.
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SLOS242F – SEPTEMBER 2002 – REVISED JANUARY 2010
PACKAGE DISSIPATION RATINGS
(1)
(2)
POWER RATING (2)
PACKAGE
qJC
(°C/W)
qJA (1)
(°C/W)
TA ≤ +25°C
TA = +85°C
D (8 pin)
38.3
97.5
1.32 W
410 mW
DGN (8 pin)
4.7
58.4
1.71 W
685 mW
DGK (8 pin)
54.2
260
385 mW
154 mW
These data were taken using the JEDEC standard High-K test PCB.
Power rating is determined with a junction temperature of +125°C. This is the point where distortion starts to substantially increase.
Thermal management of the final PCB should strive to keep the junction temperature at or below +125°C for best performance and
long-term reliability.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply voltage, (VS+ and VS–)
Dual supply
Single supply
Operating free-air temperature range
MIN
MAX
±3.3
±7.5
6.6
15
–40
+85
UNIT
V
°C
PIN ASSIGNMENTS
D, DGN, AND DGK PACKAGES
(TOP VIEW)
1VOUT
1
8
VS+
1VIN-
2
7
2VOUT
1VIN+
3
6
2VIN-
VS-
4
5
2VIN+
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THS3202
SLOS242F – SEPTEMBER 2002 – REVISED JANUARY 2010
www.ti.com
ELECTRICAL CHARACTERISTICS: VS = ±5 V
VS = ±5 V: RF = 500 Ω, RL = 100 Ω, and G = +2, unless otherwise noted.
THS3202
TYP
PARAMETER
TEST CONDITIONS
+25°C
OVER TEMPERATURE
+25°C
0°C to
+70°C
–40°C to
+85°C
UNIT
MIN/TYP/
MAX
AC PERFORMANCE
G = +1, RF = 500 Ω
1800
MHz
Typ
G = +2, RF = 402 Ω
975
MHz
Typ
G = +5, RF = 300 Ω
780
MHz
Typ
G = +10, RF = 200 Ω
550
MHz
Typ
Bandwidth for 0.1-dB flatness
G = +2, VO = 100 mVPP, RF = 536 Ω
380
MHz
Typ
Large-signal bandwidth
G = +2, VO = 4 VPP,RF = 536 Ω
875
MHz
Typ
G = –1, 5-V step
5100
V/µs
Typ
G = +2, 5-V step
4400
V/µs
Typ
Rise and fall time
G = +2, VO = 5-V step
0.45
ns
Typ
Settling time to 0.1%
G = –2, VO = 2-V step
19
ns
Typ
Settling time to 0.01%
G = –2, VO = 2-V step
118
ns
Typ
Harmonic distortion
G = +2, f = 16 MHz, VO = 2 VPP
RL = 100 Ω
–64
dBc
Typ
RL = 500 Ω
–67
dBc
Typ
RL = 100 Ω
–67
dBc
Typ
RL = 500 Ω
–69
dBc
Typ
3rd-order intermodulation distortion
G = +5, fC = 120 MHz, Δf = 200 kHz,
VO(envelope) = 2 VPP
–64
dBc
Typ
Input voltage noise
f > 10 MHz
1.65
nV/√Hz
Typ
Input current noise (noninverting)
f > 10 MHz
13.4
pA/√Hz
Typ
Input current noise (inverting)
f > 10 MHz
20
pA/√Hz
Typ
Crosstalk
G = +2, f = 100 MHz
–60
dB
Typ
Differential gain (NTSC, PAL)
G = +2, RL = 150 Ω
0.008
%
Typ
Differential phase (NTSC, PAL)
G = +2, RL = 150 Ω
0.03
Degrees
Typ
Small-signal bandwidth, –3 dB
(VO = 100 mVPP)
Slew rate (25% to 75% level)
2nd harmonic
3rd harmonic
DC PERFORMANCE
Open-loop transimpedance gain
VO = ±1 V, RL = 1 kΩ
300
200
140
120
kΩ
Min
Input offset voltage
VCM = 0 V
±0.7
±3
±3.8
±4
mV
Max
±10
±13
µV/°C
Typ
±13
±60
±80
±85
µA
Max
±300
±400
nA/°C
Typ
±14
±35
±45
±50
µA
Max
±300
±400
nA/°C
Typ
Average offset voltage drift
Input bias current (inverting)
Average bias current drift (–)
Input bias current (noninverting)
Average bias current drift (+)
4
VCM = 0 V
VCM = 0 V
VCM = 0 V
VCM = 0 V
VCM = 0 V
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SLOS242F – SEPTEMBER 2002 – REVISED JANUARY 2010
ELECTRICAL CHARACTERISTICS: VS = ±5 V (continued)
VS = ±5 V: RF = 500 Ω, RL = 100 Ω, and G = +2, unless otherwise noted.
THS3202
TYP
PARAMETER
TEST CONDITIONS
OVER TEMPERATURE
+25°C
+25°C
0°C to
+70°C
–40°C to
+85°C
UNIT
MIN/TYP/
MAX
Min
INPUT
Common-mode input range
Common-mode rejection ratio
Input resistance
Input capacitance
±2.6
±2.5
±2.5
±2.5
V
VCM = ±2.5 V
71
60
58
58
dB
Min
Noninverting
780
kΩ
Typ
Inverting
11
Ω
Typ
Noninverting
1
pF
Typ
V
Min
OUTPUT
Voltage output swing
RL = 1 kΩ
±3.65
±3.5
±3.45
±3.4
RL = 100 Ω
±3.45
±3.3
±3.25
±3.2
V
Min
Current output, sourcing
RL = 20 Ω
115
105
100
100
mA
Min
Current output, sinking
RL = 20 Ω
100
85
80
80
mA
Min
Closed-loop output impedance
G = +1, f = 1 MHz
0.01
Ω
Typ
POWER SUPPLY
Minimum operating voltage
Absolute minimum
±3
±3
±3
V
Min
Maximum quiescent current
Per amplifier
14
16.8
19
20
mA
Max
Power-supply rejection (+PSRR)
VS+ = 4.5 V to 5.5 V
69
63
60
60
dB
Min
Power-supply rejection (–PSRR)
VS– = –4.5 V to –5.5 V
65
58
55
55
dB
Min
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THS3202
SLOS242F – SEPTEMBER 2002 – REVISED JANUARY 2010
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ELECTRICAL CHARACTERISTICS: VS = 15 V
VS = 15 V: RF = 500 Ω, RL = 100 Ω, and G = +2, unless otherwise noted.
THS3202
TYP
PARAMETER
TEST CONDITIONS
+25°C
OVER TEMPERATURE
+25°C
0°C to
+70°C
–40°C to
+85°C
UNITS
MIN/TYP/
MAX
AC PERFORMANCE
G = +1, RF = 550 Ω
2000
MHz
Typ
G = +2, RF = 550 Ω
1100
MHz
Typ
G = +5, RF = 300 Ω
850
MHz
Typ
G = +10, RF = 200 Ω
750
MHz
Typ
Bandwidth for 0.1-dB flatness
G = +2, VO = 100 mVPP, RF = 536 Ω
500
MHz
Typ
Large-signal bandwidth
G = +2, VO = 4 VPP, RF = 536 Ω
1000
MHz
Typ
G = +5, 5-V step
7500
V/µs
Typ
G = +2, 10-V step
9000
V/µs
Typ
Rise and fall time
G = +2, VO = 10-V step
0.45
ns
Typ
Settling time to 0.1%
G = –2, VO = 2-V step
23
ns
Typ
Settling time to 0.01%
G = –2, VO = 2-V step
112
ns
Typ
Input voltage noise
f > 10 MHz
1.65
nV/√Hz
Typ
Input current noise (noninverting)
f > 10 MHz
13.4
pA/√Hz
Typ
Input current noise (inverting)
f > 10 MHz
20
pA/√Hz
Typ
Crosstalk
G = +2, f = 100 MHz
–60
dB
Typ
Differential gain (NTSC, PAL)
G = +2, RL = 150 Ω
0.004
%
Typ
Differential phase (NTSC, PAL)
G = +2, RL = 150 Ω
0.006
Degrees
Typ
Small-signal bandwidth, –3 dB
(VO = 100 mVPP)
Slew rate (25% to 75% level)
DC PERFORMANCE
Open-loop transimpedance gain
VO = 6.5 V to 8.5 V, RL = 1 kΩ
300
200
140
120
kΩ
Min
Input offset voltage
VCM = 7.5 V
±1.3
±4
±4.8
±5
mV
Max
±10
±13
µV/°C
Typ
Max
Average offset voltage drift
Input bias current (inverting)
Average bias current drift (–)
Input bias current (noninverting)
Average bias current drift (+)
VCM = 7.5 V
VCM = 7.5 V
±16
±60
VCM = 7.5 V
VCM = 7.5 V
±14
±35
VCM = 7.5 V
±80
±85
µA
±300
±400
nA/°C
Typ
±45
±50
µA
Max
±300
±400
nA/°C
Typ
V
Min
INPUT
2.4 to
12.6
2.5 to
12.5
2.5 to
12.5
2.5 to
12.5
VCM = 5 V to 10 V
69
60
58
58
Noninverting
780
Inverting
Noninverting
Common-mode input range
Common-mode rejection ratio
Input resistance
Input capacitance
dB
Min
kΩ
Typ
11
Ω
Typ
1
pF
Typ
OUTPUT
RL = 1 kΩ
1.5 to
13.5
1.6 to
13.4
1.7 to
13.3
1.7 to
13.3
V
Min
RL = 100 Ω
1.7 to
13.3
1.8 to
13.2
2.0 to
13.0
2.0 to
13.0
V
Min
Current output, sourcing
RL = 20 Ω
120
105
100
100
mA
Min
Current output, sinking
RL = 20 Ω
115
95
90
90
mA
Min
Closed-loop output impedance
G = +1, f = 1 MHz
0.01
Ω
Typ
Voltage output swing
POWER SUPPLY
Maximum quiescent current/channel
Per amplifier
15
18
21
21
mA
Max
Power-supply rejection (+PSRR)
VS+ = 14.50 V to 15.50 V
69
63
60
60
dB
Min
Power-supply rejection (–PSRR)
VS– = –0.5 V to +0.5 V
65
58
55
55
dB
Min
6
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SLOS242F – SEPTEMBER 2002 – REVISED JANUARY 2010
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
Small-signal frequency response
Figure 1-Figure 14
Large-signal frequency response
Figure 15-Figure 18
Harmonic distortion
vs Frequency
Harmonic distortion
vs Output voltage
Figure 25-Figure 32
IMD3
vs Frequency
Figure 33, Figure 34
OIP3
vs Frequency
Figure 35, Figure 36
S-parameter
vs Frequency
Figure 38-Figure 41
Input current noise density
vs Frequency
Figure 42
Voltage noise density
vs Frequency
Figure 43
Transimpedance
vs Frequency
Figure 44
Output impedance
vs Frequency
Figure 45
Test circuit for IMD3/OIP3
Figure 19-Figure 24
Figure 37
Impedance of inverting input
Figure 46
Supply current/channel
vs Supply voltage
Figure 47
Input offset voltage
vs Free-air temperature
Figure 48
Offset voltage
vs Common-mode input voltage range
Figure 49
vs Free-air temperature
Figure 50
vs Input common-mode range
Figure 51
Positive power-supply rejection ratio
vs Positive power supply
Figure 52
Negative power-supply rejection ratio
vs Negative power supply
Positive output voltage swing
vs Free-air temperature
Figure 54, Figure 55
Negative output voltage swing
vs Free-air temperature
Figure 56, Figure 57
Output current sinking
vs Power supply
Output current sourcing
vs Power supply
Input bias current
Overdrive recovery time
Slew rate
Figure 53
Figure 58
Figure 59
Figure 60, Figure 61
vs Output voltage
Output voltage transient response
Figure 62-Figure 64
Figure 65
Settling time
Figure 66, Figure 67
DC common-mode rejection ratio high
vs Input common-mode range
Figure 68
Power-supply rejection ratio
vs Frequency
Differential gain error
vs 150-Ω loads
Figure 71, Figure 72, Figure 75
Differential phase error
vs 150-Ω loads
Figure 73, Figure 74, Figure 76
Figure 69, Figure 70
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TYPICAL CHARACTERISTICS
SMALL-SIGNAL FREQUENCY
RESPONSE
SMALL-SIGNAL FREQUENCY
RESPONSE
44
3
Rf = 500 Ω
6
Rf = 500 Ω
2
00
Rf = 619 Ω
−1
−1
−2
−2
G=1
RL = 100 Ω
VCC = ±5 V
VO = 100 mVPP
−4
−4
−5
−5
0.1 M
1M
1
0
100 M
1G
Rf = 619 Ω
−1
−2
−3
−4
10 M
G=1
RL = 100 Ω
VCC = 15 V
VO = 100 mVPP
−5
0.1 M
10G
1M
f − Frequency − Hz
10 M
3
2
Rf = 619 Ω
1
0
−1
Rf = 750 Ω
−2
−3
100 M
1G
−4
0.1 M
10 G
1M
10 M
100 M
1G
f − Frequency − Hz
f − Frequency − Hz
Figure 1.
Figure 2.
Figure 3.
SMALL-SIGNAL FREQUENCY
RESPONSE
SMALL-SIGNAL FREQUENCY
RESPONSE
SMALL-SIGNAL FREQUENCY
RESPONSE
9
9
8
8
7
6
5
Rf = 536 Ω
4
Rf = 650 Ω
3
2
1
0
0.1 M
G=2
RL = 100 Ω
VCC = 15 V
VO = 100 mVPP
1M
100 M
1G
5
Rf = 536 Ω
4
Rf = 650 Ω
3
0
0.1 M
10 G
10
6
1
10 M
11
Rf = 402 Ω
7
2
G=2
RL = 100 Ω
VCC = ±5 V
VO = 100 mVPP
1M
10 M
9
G=2
RL = 500 Ω
VCC = 15 V
VO = 100 mVPP
8
Rf = 536 Ω
7
6
5
4
Rf = 649 Ω
3
2
1
100 M
1G
0
0.1 M
10 G
1M
10 M
100 M
1G
f − Frequency − Hz
f − Frequency − Hz
f − Frequency − Hz
Figure 4.
Figure 5.
Figure 6.
SMALL-SIGNAL FREQUENCY
RESPONSE
SMALL-SIGNAL FREQUENCY
RESPONSE
SMALL-SIGNAL FREQUENCY
RESPONSE
16
9
5
Rf = 649 Ω
4
3
2
1
0
0.1 M
G=2
RL = 500 Ω
VCC = ±5 V
VO = 100 mVPP
1M
10 M
14
1G
10 G
Rf = 402 Ω
13
12
11
100 M
Small Signal Gain − dB
Small Signal Gain − dB
6
10
0.1 M
Rf = 500 Ω
G=5
RL = 100 Ω
VCC = 15 V
VO = 100 mVPP
1M
10 M
14
13
1G
10 G
Rf = 402 Ω
12
Rf = 500 Ω
11
10
9
100 M
Rf = 300 Ω
15
15
Rf = 536 Ω
10 G
16
Rf = 300 Ω
8
7
10 G
12
Small Signal Gain − dB
Rf = 402 Ω
Small Signal Gain − dB
Small Signal Gain − dB
Small Signal Gain − dB
11
−3
−3
Small Signal Gain − dB
G=1
RL = 500 Ω
VCC = ±5 V
VO = 100 mVPP
5
4
22
Small Signal Gain − dB
Small Signal Gain − dB
33
8
SMALL-SIGNAL FREQUENCY
RESPONSE
8
0.1 M
G=5
RL = 100 Ω
VCC = ±5 V
VO = 100 mVPP
1M
10 M
100 M
f − Frequency − Hz
f − Frequency − Hz
f − Frequency − Hz
Figure 7.
Figure 8.
Figure 9.
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10 G
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TYPICAL CHARACTERISTICS (continued)
SMALL-SIGNAL FREQUENCY
RESPONSE
SMALL-SIGNAL FREQUENCY
RESPONSE
17
17
16
Small Signal Gain − dB
14
14
Rf = 420 Ω
11
11
10
10
0.1 M
G=5
RL = 500 Ω
VCC = 15 V
VO = 100 mVPP
1M
Rf = 500 Ω
14
13
Rf = 420 Ω
12
Rf = 500 Ω
11
10
9
10 M
100 M
1G
8
0.1 M
10 G
G=5
RL = 500 Ω
VCC = ±5 V
VO = 100 mVPP
1M
f − Frequency − Hz
−4
−5
10 M
100 M
1G
−6
0.1 M
10 G
G = −1
RL = 100 Ω
VCC = 15 V
VO = 100 mVPP
1M
Rf = 550 Ω
10 M
100 M
1G
SMALL-SIGNAL FREQUENCY
RESPONSE
LARGE-SIGNAL FREQUENCY
RESPONSE
3
0
Rf = 450 Ω
−3
−4
−6
0.1 M
G = −1
RL = 100 Ω
VCC = ±5 V
VO = 100 mVPP
1M
Rf = 550 Ω
10 M
10
2
−1
−2
12
VCC = 15 V
1
0
−1
VCC = ±5 V
−2
−3
−4
100 M
1G
−5
0.1 M
10 G
Normalized Amplitude − dB
Rf = 340 Ω
f − Frequency − Hz
G=1
RL = 500 Ω
Rf = 450 Ω
VO = 100 mVPP
1M
10 M
100 M
1G
8
G = 1,
VCC = ±5 V
RL = 100 Ω
4
VO = 1 VPP
2
0
−2
VO = 0.5 VPP
−4
−6
−8
−10
−12
100 K
10 G
VO = 2 VPP
6
1M
f − Frequency − Hz
10 M
100 M
f − Frequency − Hz
1G
Figure 13.
Figure 14.
Figure 15.
LARGE-SIGNAL FREQUENCY
RESPONSE
LARGE-SIGNAL FREQUENCY
RESPONSE
LARGE-SIGNAL FREQUENCY
RESPONSE
12
14
10
12
10
Normalized Amplitude − dB
VO = 2 VPP
6
4
VO = 1 VPP
0
−2
VO = 0.5 VPP
−6
−8
VCC = 15 V, G = 1, RL = 100 Ω
−10
−12
100 K 1 M
10 M
100 M
1G
10 G
f − Frequency − Hz
Figure 16.
VO = 4 VPP
VO = 2 VPP
2
0
−2
VO = 1 VPP
−4
−6
−8
10 G
14
12
8
6
4
10 G
f − Frequency − Hz
SMALL-SIGNAL FREQUENCY
RESPONSE
Small Signal Gain − dB
Small Signal Gain − dB
−3
Figure 12.
−5
Normalized Amplitude − dB
Rf = 450 Ω
−2
Figure 11.
1
−4
0
−1
Figure 10.
2
2
1
f − Frequency − Hz
3
8
Rf = 340 Ω
2
Normalized Amplitude − dB
Small Signal Gain − dB
15
15
15
13
13
3
Rf = 340 Ω
Small Signal Gain − dB
Rf = 340 Ω
16
16
12
12
SMALL-SIGNAL FREQUENCY
RESPONSE
VO = 0.5 VPP
−10
VCC = 15 V, G = 2, RL = 100 Ω
−12
100 K
1M
10 M 100 M
1G
f − Frequency − Hz
Figure 17.
VO = 2 VPP
VO = 1 VPP
VO = 0.25 VPP
−8
−10
−12
−14
10 G
VO = 4 VPP
10
8
6
4
2
0
−2
−4
−6
G = 2, VCC = ±5, RL = 100 Ω
100 K
1M
10 M
100 M
1G
Figure 18.
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10 G
f − Frequency − Hz
9
THS3202
SLOS242F – SEPTEMBER 2002 – REVISED JANUARY 2010
www.ti.com
TYPICAL CHARACTERISTICS (continued)
HARMONIC DISTORTION
vs
FREQUENCY
HARMONIC DISTORTION
vs
FREQUENCY
−50
−60
−70
2nd Harmonic
3rd Harmonic
−80
−90
−100
−60
−70
10 M
2nd Harmonic
3rd
Harmonic
−80
−90
−60
−65
−70
2nd Harmonic
−75
−80
3rd Harmonic
−85
−90
−95
1M
100 M
10 M
−100
0.1 M
100 M
1M
10 M
100 M
f − Frequency − Hz
f − Frequency − Hz
f − Frequency − Hz
Figure 19.
Figure 20.
Figure 21.
HARMONIC DISTORTION
vs
FREQUENCY
HARMONIC DISTORTION
vs
FREQUENCY
HARMONIC DISTORTION
vs
FREQUENCY
−50
−50
−60
2nd Harmonic
−70
−80
3rd Harmonic
−90
−100
0.1 M
1M
10 M
100 M
G=5
RL = 100 Ω
VCC = ±5 V
Rf = 420 Ω
VO = 2V PP
−60
HD − Harmonic Distortion − dB
G=2
RL = 500 Ω
VCC = ±5 V
Rf = 536 Ω
VO = 2V PP
HD − Harmonic Distortion − dB
−50
−70
−80
2nd Harmonic
3rd Harmonic
−90
−100
0.1 M
1M
10 M
100 M
G=5
RL = 500 Ω
VCC = ±5 V
Rf = 500 Ω
VO = 2V PP
−60
−70
3rd Harmonic
−80
2nd Harmonic
−90
−100
0.1 M
1M
10 M
100 M
f − Frequency − Hz
f − Frequency − Hz
f − Frequency − MHz
Figure 22.
Figure 23.
Figure 24.
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
−70
−70
−50
−85
−55
HD − Harmonic Distortion − dB
−80
G=5
RL = 500 Ω
VCC = ±5 V
Rf = 420 Ω
f = 10 MHz
−90
−95
2nd Harmonic
−100
3rd Harmonic
−105
−60
−65
HD − Harmonic Distortion − dB
G=5
RL = 500 Ω
VCC = ±5 V
Rf = 420 Ω
f = 1 MHz
−75
HD − Harmonic Distortion − dB
G=2
RL = 100 Ω
VCC = ±5 V
Rf = 500 Ω
VO = 2V PP
−55
−100
1M
HD − Harmonic Distortion − dB
−50
G = −1
RL = 500 Ω
VCC = ±5 V
Rf = 450 Ω
VO = 2V PP
HD − Harmonic Distortion − dB
G = −1
RL = 100 Ω
VCC = ±5 V
Rf = 450 Ω
VO = 2V PP
HD − Harmonic Distortion − dB
HD − Harmonic Distortion − dB
−50
HARMONIC DISTORTION
vs
FREQUENCY
−70
−75
−80
2nd Harmonic
−85
−90
3rd Harmonic
G=5
RL = 100 Ω
VCC = ±5 V
Rf = 500 Ω
f = 1 MHz
−80
2nd Harmonic
−90
−95
3rd Harmonic
−110
−100
0
1
2
3
4
5
VO − Output Voltage − VPP
Figure 25.
10
6
−100
0
1
2
3
4
VO − Output Voltage − VPP
Figure 26.
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5
0
1
2
3
4
5
VO − Output Voltage − VPP
Figure 27.
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Product Folder Link(s): THS3202
THS3202
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SLOS242F – SEPTEMBER 2002 – REVISED JANUARY 2010
TYPICAL CHARACTERISTICS (continued)
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
−70
−65
2nd Harmonic
−70
−75
−80
−85
−90
3rd
Harmonic
−75
−80
2nd
Harmonic
−85
−90
−95
−95
−60
2nd
Harmonic
−70
−80
3rd Harmonic
−90
−100
−100
0
1
2
3
4
5
0
VO − Output Voltage − VPP
1
2
3
4
0
5
2
3
Figure 29.
Figure 30.
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
THS3202
IMD3
vs
FREQUENCY
−55
−50
−85
2nd
Harmonic
−90
−95
3rd Harmonic
−60
−65
−60
−70
−75
2nd Harmonic
−80
1
2
3
4
−75
VCC = ±6 V
−80
VCC = ±7 V
−85
−90
VCC = ±7.5 V
3rd Harmonic
−90
Test Instrument Measurement Limit
−100
0
VCC = ±5 V
−70
−85
−95
−100
−95
0
5
1
2
3
4
10
5
60
VO − Output Voltage − VPP
VO − Output Voltage − VPP
110
160
210
fc − Frequency − MHz
Figure 31.
Figure 32.
Figure 33.
THS3202
IMD3
vs
FREQUENCY
THS3202
OIP3
vs
FREQUENCY
THS3202
OIP3
vs
FREQUENCY
−70
50
48
46
−75
44
OIP 3 − dBm
G=2
−80
G=5
−85
VCC = ±5 V
RL = 100 Ω,
Rf = 536 Ω,
∆f = 200 kHz
VO = 2VPP_Envelope
−90
−95
20
40
60
80
fc − Frequency − MHz
Figure 34.
5
RL = 100 Ω, G = 5,
Rf = 536 Ω,
VO = 2VPP_Envelope
∆f = 200 kHz
−65
IMD 3 − dBc
−80
HD − Harmonic Distortion − dB
−75
G=2
RL = 100 Ω
VCC = ±5 V
Rf = 500 Ω
f = 10 MHz
−55
4
VO − Output Voltage − VPP
Figure 28.
G=2
RL = 100 Ω
VCC = ±5 V
Rf = 500 Ω
f = 1 MHz
0
1
VO − Output Voltage − VPP
−70
HD − Harmonic Distortion − dB
G=2
RL = 500 Ω
VCC = ±5 V
Rf = 536 Ω
f = 10 MHz
3rd Harmonic
−100
260
47
Test Instrument Measurement Limit
45
G=5
VCC = ±7.5 V
42
OIP 3 − dBm
HD − Harmonic Distortion − dB
−60
−50
G=2
RL = 500 Ω
VCC = ±5 V
Rf = 536 Ω
f = 1 MHz
HD − Harmonic Distortion − dB
G=5
RL = 100 Ω
VCC = ±5 V
Rf = 500 Ω
f = 10 MHz
−55
HD − Harmonic Distortion − dB
−50
IMD 3 − dBc
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
VCC = ±7 V
40
VCC = ±6 V
38
36
34 RL = 100 Ω,
32 G = 5,
Rf = 536 Ω,
30 VO = 2VPP_Envelope
28 ∆f = 200 kHz
VCC = ±5 V
26
10
60
110
160
210
fc − Frequency − MHz
Figure 35.
43
41
VCC = ±5 V
RL = 100 Ω,
Rf = 536 Ω,
∆f = 200 kHz
VO = 2VPP_Envelope
G=2
39
37
35
260
0
20
40
60
Figure 36.
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80
fc − Frequency − MHz
11
THS3202
SLOS242F – SEPTEMBER 2002 – REVISED JANUARY 2010
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TYPICAL CHARACTERISTICS (continued)
S-PARAMETER
vs
FREQUENCY
TEST CIRCUIT FOR
IMD3/OIP3
20
S Parameter − dB
0
Output Power
Spectrum Analyzer
_
G=5
50 Ω
50 Ω
−20
20
VCC = ±5 V
C = 0 pF
RL = 100 Ω
G = 10
−20
−40
−60
S12
S11
C
−80
+
_
100 M
1G
−140
0.1 M
10 G
1M
10 M
100 M
1G
S-PARAMETER
vs
FREQUENCY
INPUT CURRENT NOISE DENSITY
vs
FREQUENCY
50
−60
S12
S11
−80
C
+
_
−20
VCC = ±5 V
C = 3 pF
RL = 100 Ω
G = 10
Input Current Noise Density − pA Hz
0
S22
−40
S22
−40
−60
S12
S11
C
−80
+
_
−100
1M
10 M
100 M
1G
−120
0.1 M
10 G
1M
10 M
100 M
f − Frequency − Hz
1G
VCC = ±5 V and 15 V
TA = 25°C
45
40
35
30
Inverting
Noise Current
25
20
Noninverting
Current Noise
15
10
100 K
10 G
1M
10 M
f − Frequency − Hz
Figure 40.
Figure 41.
Figure 42.
VOLTAGE NOISE DENSITY
vs
FREQUENCY
TRANSIMPEDANCE
vs
FREQUENCY
OUTPUT IMPEDANCE
vs
FREQUENCY
4.5
3
2.5
2
1.5
100 K
10 M
1M
f − Frequency − Hz
100 M
Figure 43.
VCC = 15 V,
VCC = ±5 V
100
G=2
RL = 100 Ω
ZO− Output Impedance −Ω
Transimpedance Gain −dBΩ
3.5
80
60
40
20
0
0.1 M
100 M
100
120
VCC = ±5 V and 15 V
TA = 25°C
4
10 G
f − Frequency − Hz
S-PARAMETER
vs
FREQUENCY
f − Frequency − Hz
Hz
10 M
Figure 39.
−120
Voltage Noise Density − nV/
C
+
_
Figure 38.
−100
12
S12
S11
−80
f − Frequency − Hz
S Parameter − dB
S Parameter − dB
1M
20
−140
0.1 M
−60
Figure 37.
VCC = 15 V
C = 3 pF
RL = 100 Ω
G = 10
−20
−40
−120
−120
0.1 M
20
0
S22
−100
−100
This circuit applies to figures 46
through 49
VCC = 15 V
C = 0 pF
RL = 100 Ω
G = 10
0
S22
S Parameter − dB
TEST CIRCUIT FOR
IMD3 / OIP3
+
S-PARAMETER
vs
FREQUENCY
10 Ω
_
+
V
Gain W +
+
_
O
10
1
VCC = ±5 V
0.1
I IB
0.01
1M
10 M
100 M
f − Frequency − Hz
Figure 44.
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1G
0.1 M
VCC = 15 V
1M
10 M
100 M
1G
f − Frequency − Hz
Figure 45.
Copyright © 2002–2010, Texas Instruments Incorporated
Product Folder Link(s): THS3202
THS3202
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SLOS242F – SEPTEMBER 2002 – REVISED JANUARY 2010
TYPICAL CHARACTERISTICS (continued)
SUPPLY CURRENT/CHANNEL
vs
SUPPLY VOLTAGE
THS3202
IMPEDANCE OF INVERTING INPUT
16
14
13
12
11
21
TA = 85°C
19
17
TA = 25°C
15
13
11
TA = −40°C
9
7
10
5
100 k
1M
10 M
100 M
1G
−1.0
VCC = ±5 V
−1.5
−2.0
−2.5
VCC = 15 V
−3.0
−3.5
−4.0
−45−35−25−15 −5 5 15 25 35 45 55 65 75 85
3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5
10 G
±VCC − Supply Voltage − V
f − Frequency − Hz
TA − Free-Air Temperature − °C
Figure 46.
Figure 47.
Figure 48.
OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
RANGE
INPUT BIAS CURRENT
vs
FREE-AIR TEMPERATURE
INPUT BIAS CURRENT
vs
INPUT COMMON-MODE RANGE
50
4
45
2
TA = −40°C
0
TA = 25°C
−2
−4
TA = 85°C
−6
40
35
VCC = 15 V
30
25
VCC = ±5 V
20
RL = 100 Ω
VCC = ±7.5 V
−8
−10
0
1
2
3
4
5
TA = −40°C to 85°C
VCC = ±5 V
−20
−30
15
−40−30−20−10 0 10 20 30 40 50 60 70 80
−10
−5 −4 −3 −2 −1
I IB − Input Bias Current − µ A
6
IIB − Input Bias Current − µA
−3
TA − Free-Air Temperature − °C
VICR − Common-Mode Input Voltage Range − V
−2
−1
0
1
2
Input Common Mode Range − V
3
Figure 50.
Figure 51.
POSITIVE POWER-SUPPLY
REJECTION RATIO
vs POSITIVE POWER SUPPLY
NEGATIVE POWER-SUPPLY
REJECTION RATIO
vs NEGATIVE POWER SUPPLY
POSITIVE OUTPUT VOLTAGE SWING
vs
FREE-AIR TEMPERATURE
75
TA = −40°C
70
TA = 25°C
65
TA = 85°C
60
55
50
RL = 100 Ω
45
3
3.5
4 4.5 5 5.5
6 6.5
Positive Power Supply − V
7
7.5
−PSSR − Negative Power Supply Rejection Ratio − dB
Figure 49.
Figure 52.
13.7
VO − Positive Output Voltage Swing − V
VOS − Offset Voltage − mV
VIO − Input Offset Voltage − mV
ICC − Supply Current /Channel− mA
15
ZO − Impedance − Ω
−0.5
23
VCC = +5 V
+PSSR − Positive Power Supply Rejection Ratio − dB
INPUT OFFSET VOLTAGE
vs
FREE-AIR TEMPERATURE
70
TA = −40°C
65
TA = 25°C
TA = 85°C
60
55
50
3
3.5
4 4.5 5 5.5 6 6.5
Negative Power Supply − V
7
Figure 53.
RL = 1 kΩ
13.5
13.4
13.3
RL = 100 Ω
13.2
13.1
−50
RL = 100 Ω
45
VCC = 15 V
13.6
7.5
−30
−10
10
30
50
70
Figure 54.
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90
TA − Free-Air Temperature − °C
13
THS3202
SLOS242F – SEPTEMBER 2002 – REVISED JANUARY 2010
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TYPICAL CHARACTERISTICS (continued)
POSITIVE OUTPUT VOLTAGE SWING
vs
FREE-AIR TEMPERATURE
NEGATIVE OUTPUT VOLTAGE SWING
vs
FREE-AIR TEMPERATURE
VCC = 15 V
1.7
RL = 100 Ω
1.6
1.5
1.4
RL = 1 kΩ
1.3
1.2
−50
−30
−10
10
30
50
70
VCC = ±5 V
3.70
3.65
RL = 1 kΩ
3.60
3.55
3.50
3.45
RL = 100 Ω
3.40
3.35
3.30
−45
90
−25
−5
15
35
55
75
VCC = ±5 V
−3.50
Figure 55.
Figure 56.
OUTPUT CURRENT SINKING
vs
POWER SUPPLY
OUTPUT CURRENT SOURCING
vs
POWER SUPPLY
−3.60
−3.65
−3.70
−3.80
−50
95
I O − Output Current Sourcing − mA
RL = 10 Ω
120
TA = 85°C
100
TA = 25°C
TA = −40°C
80
70
−30
−10
10
30
50
OVERDRIVE RECOVERY TIME
10
RL = 10 Ω
140
VI
8
TA = −40°C
6
120
TA = 25°C
100
TA = 85°C
80
4
2
0
−2
VO
−4
−6
60
RL = 100 Ω
VCC = 15 V
−8
40
3 3.5 4.0
4 4.5 5.0
5 5.5 6.0
6 6.5
6.5 7.0
7 7.5
3.0
±Power Supply − V
±Power Supply − V
−10
0.0
0.2
0.4
0.6
0.8
Figure 59.
Figure 60.
OVERDRIVE RECOVERY TIME
SLEW RATE
vs
OUTPUT VOLTAGE
SLEW RATE
vs
OUTPUT VOLTAGE
10 k
10 k
VI
4
2
0
VO
−2
−4
VCC = ±5 V
RL = 100 Ω
G = −1
RL = 100 Ω
VCC = 15 V,
VCC = ±5 V
SR − Slew Rate − V/ µ s
SR − Slew Rate − V/ µ s
6
1.0
1
t − Time − µs
Figure 58.
8
90
Figure 57.
3.0
3 3.5 4.0
4 4.5 5.0
5 5.5 6.0
6 6.5 7.0
7 7.5
7.5
10
70
TA − Free-Air Temperature − °C
160
90
RL = 1 kΩ
−3.75
V − Voltage − V
130
110
RL = 100 Ω
−3.55
TA − Free-Air Temperature − °C
TA − Free-Air Temperature − °C
I O − Output Current Sinking − mA
VO − Negative Output Voltage Swing − V
VO − Positive Output Voltage Swing − V
VO − Negative Output Voltage Swing − V
−3.45
3.75
1.8
V − Voltage − V
NEGATIVE OUTPUT VOLTAGE SWING
vs
FREE-AIR TEMPERATURE
1k
1k
−6
RL = 100 Ω
VCC = ±5 V
−8
−10
0.0
0.2
0.6
0.8
t − Time − µs
Figure 61.
14
100
100
0.4
1
1.0
0
1
2
3
4
5
0
1
2
3
4
VO − Output Voltage − V
VO − Output Voltage − V
Figure 62.
Figure 63.
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6
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THS3202
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SLOS242F – SEPTEMBER 2002 – REVISED JANUARY 2010
TYPICAL CHARACTERISTICS (continued)
SLEW RATE
vs
OUTPUT VOLTAGE
OUTPUT VOLTAGE
TRANSIENT
RESPONSE
100 k
1.05
2.5
1.04
2.0
10 k
1k
1.0
G = −1
RL = 500 Ω
VCC = ±5 V
Rf = 250 Ω
VO = 5 VPP
0.5
0.0
−0.5
−1.0
−1.5
−2.0
1.02
1.01
1
0.99
0.98
0.97
−2.5
0.96
−3.0
0
2
4
6
8
10
12
0
10
20
VO − Output Voltage − V
0.95
60
10
30
50
70
90
110
130
SETTLING TIME
DC COMMON-MODE REJECTION
RATIO HIGH
vs
INPUT COMMON-MODE RANGE
POWER-SUPPLY REJECTION RATIO
vs
FREQUENCY
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
10 20 30 40 50 60 70 80 90 100
Settling Time − ns
DC_CMRR − Common Mode Rejection Ratio High − dB
Figure 66.
VCC = 15 V,
VO = 2 VPP,
G = −2,
Rf = 450 Ω
70
60
50
RL = 100 Ω
40
30
20
10
0
−7.5 −5.5 −3.5 −1.5 0.5 2.5 4.5 6.5
Input Common Mode Range − V
−20
VCC = ±5 V
−25
−30
−35
VCC
−40
−45
VEE
−50
−55
−60
0.1 M
1M
10 M
100 M
Figure 68.
Figure 69.
POWER-SUPPLY REJECTION RATIO
vs
FREQUENCY
DIFFERENTIAL GAIN ERROR
vs
150-Ω LOADS
DIFFERENTIAL GAIN ERROR
vs
150-Ω LOADS
0.35
0.035
0.30
0.030
Differential Gain Erroe − %
−20
−25
−30
−35
VCC
−40
−45
VEE
−50
−55
−60
0.1 M
0.030
0.30
NTSC
G=2
VCC = 15 V
0.25
0.025
0.20
0.020
0.15
0.015
VCC = ±5 V
0.10
0.010
VCC = 15 V
10 M
100 M
1G
f − Frequency − Hz
Figure 70.
0.020
0.20
VCC = ±5 V
0.015
0.15
VCC = 15 V
0.010
0.10
0.005
0.05
0.05
0.005
0.00
0.000
1M
NTSC
G = −2
0.025
0.25
Differential Gain Error− %
−10
1G
f − Frequency − Hz
Figure 67.
−15
150
Settling Time − ns
Figure 65.
1.3
VO − Output Voltage − V
50
Figure 64.
1.4
PSSR − Power Supply Rejection Ratio − dB
40
ts − Settling Time − ns
1.5
0
30
PSSR − Power Supply Rejection Ratio − dB
100
VCC = 15 V,
VO = 2 VPP,
G = −2,
Rf = 450 Ω
1.03
1.5
VO − Output Voltage − V
VO − Output Voltage − V
SR − Slew Rate − V/ µ s
VCC = 15 V
RL = 100 Ω
SETTLING TIME
3.0
0.000
0.00
1
2
3
4
5
150-Ω Loads
Figure 71.
6
1
2
3
Figure 72.
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TYPICAL CHARACTERISTICS (continued)
DIFFERENTIAL PHASE ERROR
vs
150-Ω LOADS
DIFFERENTIAL PHASE ERROR
vs
150-Ω LOADS
0.035
0.07
NTSC
G=2
0.030
0.06
Differential Phase Error− °
0.05
VCC = ±5 V
0.04
0.03
0.02
VCC = 15 V
0.015
0.03
0.000
0.00
3
4
5
VCC = 15 V
0.010
0.02
0.00
2
VCC = ±5 V
0.020
0.04
0.005
0.01
0.030
0.30
0.025
0.25
VCC = ±5 V
0.020
0.20
0.15
0.015
VCC = 15 V
0.010
0.10
0.05
0.005
0.00
0.000
1
6
PAL
G=2
0.035
0.35
0.025
0.05
0.01
1
0.004
0.40
NTSC
G = −2
Differential Gain Error − %
0.06
Differential Phase Error − °
DIFFERENTIAL GAIN ERROR
vs
150-Ω LOADS
2
150-Ω Loads
3
4
150-Ω Loads
Figure 73.
1
2
3
4
5
6
150-Ω Loads
Figure 74.
Figure 75.
DIFFERENTIAL PHASE ERROR
vs
150-Ω LOADS
0.07
Differential Phase Error − °
0.06
VCC = ±5 V
0.05
0.04
0.03
VCC = 15 V
0.02
0.01
PAL
G=2
0.00
1
2
3
4
5
6
150-Ω Loads
Figure 76.
16
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APPLICATION INFORMATION
INTRODUCTION
The THS3202 is a high-speed, operational amplifier configured in a current-feedback architecture. The device is
built using Texas Instruments BiCOM-II process, a 15-V, dielectrically isolated, complementary bipolar process
with NPN and PNP transistors possessing fTs of several GHz. This configuration implements an exceptionally
high-performance amplifier that has a wide bandwidth, high slew rate, fast settling time, and low distortion.
RECOMMENDED FEEDBACK AND GAIN RESISTOR VALUES
As with all current-feedback amplifiers, the bandwidth of the THS3202 is an inversely proportional function of the
value of the feedback resistor. The recommended resistors for the optimum frequency response are shown in
Table 1. These should be used as a starting point and once optimum values are found, 1% tolerance resistors
should be used to maintain frequency response characteristics. For most applications, a feedback resistor value
of 750 Ω is recommended—a good compromise between bandwidth and phase margin that yields a very stable
amplifier.
Table 1. Recommended Resistor Values for Optimum Frequency Response
THS3202 RF FOR AC WHEN RLOAD = 100 Ω
GAIN
1
2
5
10
–1
VSUP
PEAKING
RF VALUE
15
Optimum
619
±5
Optimum
619
15
Optimum
536
±5
Optimum
536
15
Optimum
402
±5
Optimum
402
15
Optimum
200
±5
Optimum
200
15
Optimum
450
±5
Optimum
450
As shown in Table 1, to maintain the highest bandwidth with an increasing gain, the feedback resistor is reduced.
The advantage of dropping the feedback resistor (and the gain resistor) is that the noise of the system is also
reduced compared to no reduction of these resistor values (see the Noise Calculations section). Thus, keeping
the bandwidth as high as possible maintains very good distortion performance of the amplifier by keeping the
excess loop gain as high as possible.
Care must be taken to not drop these values too low. The amplifier output must drive the feedback resistance
(and gain resistance) and may place a burden on the amplifier. The end result is that distortion may actually
increase due to the low impedance load presented to the amplifier. Careful management of the amplifier
bandwidth and the associated loading effects must be examined by the designer for optimum performance.
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The THS3202 amplifier exhibits very good distortion performance and bandwidth with the capability of utilizing up
to 15-V supplies. Their excellent current drive capability of up to 115 mA driving into a 20-Ω load allows for many
versatile applications. One application is driving a twisted pair line (for example, a telephone line). Figure 77
shows a simple circuit for driving a twisted pair differentially.
+6 V
THS3202(a)
0.1 µF
+
10 µF
RS
+
_
VI+
RLine
2n2
499 Ω
1:n
0.1 µF
Telephone Line
210 Ω
RLine
THS3202(b)
RS
+
_
VI−
RLine
2n2
499 Ω
0.1 µF
10 µF
+
−6 V
Figure 77. Simple Line Driver With THS3202
Due to the large power-supply voltages and the large current drive capability, power dissipation of the amplifier
must not be neglected. To have as much power dissipation as possible in a small package, the THS3202 is
available in an MSOP-8 package (DGK), an MSOP-8 PowerPAD package (DGN), and an SOIC-8 package (D).
Again, power dissipation of the amplifier must be carefully examined or else the amplifiers could become too hot
and performance can be severely degraded. See the Power Dissipation and Thermal Considerations section for
more information on thermal management.
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NOISE CALCULATIONS
Noise can cause errors on very small signals. This is especially true for amplifying small signals coming over a
transmission line or an antenna. The noise model for current-feedback amplifiers (CFB) is the same as for
voltage feedback amplifiers (VFB). The only difference between the two is that CFB amplifiers generally specify
different current-noise parameters for each input, while VFB amplifiers usually only specify one noise-current
parameter. The noise model is shown in Figure 78. This model includes all of the noise sources as follows:
• en = Amplifier internal voltage noise (nV/√Hz)
• IN+ = Noninverting current noise (pA/√Hz)
• IN− = Inverting current noise (pA/√Hz)
• eRx = Thermal voltage noise associated with each resistor (eRx = 4 kTRx )
eRs
RS
en
Noiseless
+
_
eni
IN+
eno
eRf
Rf
eRg
IN−
Rg
Figure 78. Noise Model
The total equivalent input noise density (eni) is calculated by using the following equation:
e
ni
Ǹǒ
2
e nǓ ) IN )
+
ǒ
R
Ǔ
S
2
ǒ
) IN *
ǒR f ø RgǓǓ
2
ǒ
Ǔ
) 4 kTR s ) 4 kT R ø R g
f
where:
k = Boltzmann’s constant = 1.380658 × 10−23
T = Temperature in degrees Kelvin (273 +°C)
Rf || Rg = Parallel resistance of Rf and Rg
To get the equivalent output noise of the amplifier, multiply the equivalent input noise density (eni) by the overall
amplifier gain (AV).
e no + e
ǒ
Ǔ
R
A + e
1) f
ni V
ni
Rg
(Noninverting Case)
As the previous equations show, to keep noise at a minimum, small value resistors should be used. As the
closed-loop gain is increased (by reducing RF and RG), the input noise is reduced considerably because of the
parallel resistance term. This leads to the general conclusion that the most dominant noise sources are the
source resistor (RS) and the internal amplifier noise voltage (en). Because noise is summed in a
root-mean-squares method, noise sources smaller than 25% of the largest noise source can be effectively
ignored. This can greatly simplify the formula and make noise calculations much easier.
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This brings up another noise measurement usually preferred in RF applications, the noise figure (NF). Noise
figure is a measure of noise degradation caused by the amplifier. The value of the source resistance must be
defined and is typically 50 Ω in RF applications.
ȱ
ȧ
Ȳ
e 2
NF + 10log e ni
Rs2
ȳ
ȧ
ȴ
Because the dominant noise components are generally the source resistance and the internal amplifier noise
voltage, we can approximate the noise figure as:
NF +
ȱ ȡǒ Ǔ2 ǒ
ȧ en ) IN )
ȧ
ȧ Ȣ
10logȧ1 )
4 kTR
ȧ
S
ȧ
Ȳ
Ǔ ȣȳ
S ȧȧ
Ȥȧ
ȧ
ȧ
ȧ
ȴ
2
R
PRINTED-CIRCUIT BOARD LAYOUT TECHNIQUES FOR OPTIMAL PERFORMANCE
Achieving optimum performance with high-frequency amplifier-like devices in the THS320x family requires careful
attention to board layout parasitic and external component types.
Recommendations that optimize performance include:
• Minimize parasitic capacitance to any ac ground for all of the signal I/O pins. Parasitic capacitance on the
output and input pins can cause instability. To reduce unwanted capacitance, a window around the signal I/O
pins should be opened in all of the ground and power planes around those pins. Otherwise, ground and
power planes should be unbroken elsewhere on the board.
• Minimize the distance (< 0.25” or < 6,35 mm) from the power-supply pins to high-frequency 0.1-µF and 100
pF decoupling capacitors. At the device pins, the ground and power-plane layout should not be in close
proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the
pins and the decoupling capacitors. The power-supply connections should always be decoupled with these
capacitors. Larger (6.8 µF or more) tantalum decoupling capacitors, effective at lower frequency, should also
be used on the main supply pins. These may be placed somewhat farther from the device and may be shared
among several devices in the same area of the printed circuit board (PCB). The primary goal is to minimize
the impedance seen in the differential-current return paths. For driving differential loads with the THS3202,
adding a capacitor between the power-supply pins improves 2nd order harmonic distortion performance. This
also minimizes the current loop formed by the differential drive.
• Careful selection and placement of external components preserve the high-frequency performance of the
THS320x family. Resistors should be a very low reactance type. Surface-mount resistors work best and allow
a tighter overall layout. Again, keep their leads and PCB trace length as short as possible. Never use
wirewound type resistors in a high-frequency application. Because the output pin and inverting input pins are
the most sensitive to parasitic capacitance, always position the feedback and series output resistors, if any,
as close as possible to the inverting input pins and output pins. Other network components, such as input
termination resistors, should be placed close to the gain-setting resistors. Even with a low parasitic
capacitance shunting the external resistors, excessively high resistor values can create significant time
constants that can degrade performance. Good axial metal-film or surface-mount resistors have
approximately 0.2 pF in shunt with the resistor. For resistor values greater than 2.0 kΩ, this parasitic
capacitance can add a pole and/or a zero that can affect circuit operation. Keep resistor values as low as
possible, consistent with load driving considerations.
• Connections to other wideband devices on the board may be made with short direct traces or through
onboard transmission lines. For short connections, consider the trace and the input to the next device as a
lumped capacitive load. Relatively wide traces (50 mils to 100 mils or 1,27 mm to 2,54 mm) should be used,
preferably with ground and power planes opened up around them. Estimate the total capacitive load and
determine if isolation resistors on the outputs are necessary. Low parasitic capacitive loads (less than 4 pF)
may not need an RS because the THS320x family is nominally compensated to operate with a 2-pF parasitic
load. Higher parasitic capacitive loads without an RS are allowed as the signal gain increases (increasing the
unloaded phase margin). If a long trace is required, and the 6-dB signal loss intrinsic to a doubly-terminated
20
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•
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transmission line is acceptable, implement a matched impedance transmission line using microstrip or
stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques).
A 50-Ω environment is not necessary onboard, and in fact, a higher impedance environment improves
distortion as shown in the distortion versus load plots. With a characteristic board trace impedance based on
board material and trace dimensions, a matching series resistor into the trace from the output of the THS320x
is used as well as a terminating shunt resistor at the input of the destination device.
Remember also that the terminating impedance is the parallel combination of the shunt resistor and the input
impedance of the destination device: this total effective impedance should be set to match the trace
impedance. If the 6-dB attenuation of a doubly-terminated transmission line is unacceptable, a long trace can
be series-terminated at the source end only. Treat the trace as a capacitive load in this case. This does not
preserve signal integrity as well as a doubly-terminated line. If the input impedance of the destination device
is low, there is some signal attenuation due to the voltage divider formed by the series output into the
terminating impedance.
Socketing a high-speed part like the THS320x family is not recommended. The additional lead length and
pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network which
can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by
soldering the THS320x family devices directly onto the board.
PowerPAD DESIGN CONSIDERATIONS
The THS320x family is available in a thermally-enhanced PowerPAD family of packages. These packages are
constructed using a downset leadframe upon which the die is mounted [see Figure 79(a) and Figure 79(b)]. This
arrangement results in the lead frame being exposed as a thermal pad on the underside of the package [see
Figure 79(c)]. Because this thermal pad has direct thermal contact with the die, excellent thermal performance
can be achieved by providing a good thermal path away from the thermal pad.
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat dissipating device.
The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of
surface mount with the, heretofore, awkward mechanical methods of heatsinking.
DIE
Side View (a)
Thermal
Pad
DIE
End View (b)
Bottom View (c)
Figure 79. Views of Thermally-Enhanced Package
Although there are many ways to properly heatsink the PowerPAD package, the following steps illustrate the
recommended approach.
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ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
PowerPAD PCB LAYOUT CONSIDERATIONS
1. Prepare the PCB with a top side etch pattern as shown in Figure 80. There should be etch for the leads as
well as etch for the thermal pad.
68 Mils x 70 Mils
(Via diameter = 10 mils)
Figure 80. DGN PowerPAD PCB Etch and Via Pattern
2. Place five holes in the area of the thermal pad. These holes should be 10 mils (0,254 mm) in diameter. Keep
them small so that solder wicking through the holes is not a problem during reflow.
3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps
dissipate the heat generated by the THS320x family IC. These additional vias may be larger than the 10-mil
diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad
area to be soldered so that wicking is not a problem.
4. Connect all holes to the internal ground plane.
5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection
methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat
transfer during soldering operations. This makes the soldering of vias that have plane connections easier. In
this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the
holes under the THS320x family PowerPAD package should make their connection to the internal ground
plane with a complete connection around the entire circumference of the plated-through hole.
6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five
holes exposed. The bottom-side solder mask should cover the five holes of the thermal pad area. This
prevents solder from being pulled away from the thermal pad area during the reflow process.
7. Apply solder paste to the exposed thermal pad area and all of the IC terminals.
8. With these preparatory steps in place, the IC is simply placed in position and run through the solder reflow
operation as any standard surface-mount component. This results in a part that is properly installed.
POWER DISSIPATION AND THERMAL CONSIDERATIONS
To maintain maximum output capabilities, the THS3202 does not incorporate automatic thermal shutoff
protection. The designer must take care to ensure that the design does not violate the absolute maximum
junction temperature of the device. Failure may result if the absolute maximum junction temperature of +150°C is
exceeded. For best performance, design for a maximum junction temperature of +125°C. Between +125°C and
+150°C, damage does not occur, but the performance of the amplifier begins to degrade.
The thermal characteristics of the device are dictated by the package and the PCB. Maximum power dissipation
for a given package can be calculated using the following formula.
Tmax * T A
P Dmax +
q JA
where:
PDmax is the maximum power dissipation in the amplifier (W).
Tmax is the absolute maximum junction temperature (°C).
TA is the ambient temperature (°C).
θJA = θJC + θCA
θJC is the thermal coefficient from the silicon junctions to the case (°C/W).
θCA is the thermal coefficient from the case to ambient air (°C/W).
22
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For systems where heat dissipation is more critical, the THS320x family of devices is offered in an MSOP-8 with
PowerPAD. The thermal coefficient for the PowerPAD packages are substantially improved over the traditional
SOIC. Maximum power dissipation levels are depicted in the graph for the available packages. The data for the
PowerPAD packages assume a board layout that follows the PowerPAD layout guidelines referenced above and
detailed in the PowerPAD application note number SLMA002. The following graph also illustrates the effect of
not soldering the PowerPAD to a PCB. The thermal impedance increases substantially which may cause serious
heat and performance issues. Be sure to always solder the PowerPAD to the PCB for optimum performance.
PD − Maximum Power Dissipation − W
4.0
TJ = 125°C
3.5
3.0
θJA = 58.4°C/W
2.5
θJA = 98°C/W
2.0
1.5
1.0
0.5
θJA = 158°C/W
0.0
−40
−20
0
20
40
60
80
100
TA − Free-Air Temperature − °C
Results are With No Air Flow and PCB Size = 3”x3”
θJA = 58.4°C/W for 8-Pin MSOP w/PowerPad (DGN)
θJA = 98°C/W for 8-Pin SOIC High Test PCB (D)
θJA = 158°C/W for 8-Pin MSOP w/PowerPad w/o Solder
Figure 81. Maximum Power Dissipation vs Ambient Temperature
When determining whether or not the device satisfies the maximum power dissipation requirement, it is important
to not only consider quiescent power dissipation, but also dynamic power dissipation. Often times, this is difficult
to quantify because the signal pattern is inconsistent, but an estimate of the RMS power dissipation can provide
visibility into a possible problem.
DRIVING A CAPACITIVE LOAD
Driving capacitive loads with high-performance amplifiers is not a problem as long as certain precautions are
taken. The first is to realize that the THS3202 has been internally compensated to maximize its bandwidth and
slew-rate performance. When the amplifier is compensated in this manner, capacitive loading directly on the
output decreases the device's phase margin leading to high-frequency ringing or oscillations. Therefore, for
capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series with the output of
the amplifier, as shown in Figure 82. A minimum value of 10 Ω should work well for most applications. For
example, in 75-Ω transmission systems, setting the series resistor value to 75 Ω both isolates any capacitance
loading and provides the proper line impedance matching at the source end.
Rg
Rf
Input
_
10 Ω
Output
THS3202
+
CLOAD
Figure 82. Driving a Capacitive Load
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GENERAL CONFIGURATIONS
A common error for the first-time CFB user is creating a unity-gain buffer amplifier by shorting the output directly
to the inverting input. A CFB amplifier in this configuration oscillates and is not recommended. The THS3202, like
all CFB amplifiers, must have a feedback resistor for stable operation. Additionally, placing capacitors directly
from the output to the inverting input is not recommended. This is because, at high frequencies, a capacitor has
a very low impedance. This results in an unstable amplifier and should not be considered when using a
current-feedback amplifier. Because of this, integrators and simple low-pass filters, which are easily implemented
on a VFB amplifier, have to be designed slightly differently. If filtering is required, simply place an RC-filter at the
noninverting terminal of the operational amplifier, as shown in Figure 83.
RG
RF
f–3dB =
VO
VO
+
VI
R1
VI
1
2pR1C1
= 1+
RF
RG
1
1 + sR1C1
C1
Figure 83. Single-Pole Low-Pass Filter
If a multiple-pole filter is required, the use of a Sallen-Key filter can work very well with CFB amplifiers. This is
because the filtering elements are not in the negative feedback loop and stability is not compromised. Because of
their high slew-rates and high bandwidths, CFB amplifiers can create very accurate signals and help minimize
distortion. An example is shown in Figure 84.
C1
+
_
VI
R1
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
R2
f
C2
Rg
–3dB
Rg =
Rf
+
(
1
2pRC
Rf
1
2−
Q
)
Figure 84. 2-Pole Low-Pass Sallen-Key Filter
There are two simple ways to create an integrator with a CFB amplifier. The first, shown in Figure 85, adds a
resistor in series with the capacitor. This is acceptable because at high frequencies, the resistor is dominant and
the feedback impedance never drops below the resistor value. The second, shown in Figure 86, uses positive
feedback to create the integration. Caution is advised because oscillations can occur due to the positive
feedback.
C1
Rf
V
Rg
VI
−
+
VO
O +
VI
ǒ
R
ȡS ) Rf1C1ȣ
Ǔȧ S ȧ
Ȣ
Ȥ
f
Rg
THS3202
Figure 85. Inverting CFB Integrator
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Rg
Rf
For Stable Operation:
−
THS320x
VO
+
R2
R1 || RA
≥
(
1+
VO ≅ VI
R1
R2
Rf
Rg
Rf
Rg
sR1C1
)
VI
C1
RA
Figure 86. Noninverting CFB Integrator
The THS3202 may also be employed as a very good video distribution amplifier. One characteristic of distribution
amplifiers is the fact that the differential phase (DP) and the differential gain (DG) are compromised as the
number of lines increase and the closed-loop gain increases. Be sure to use termination resistors throughout the
distribution system to minimize reflections and capacitive loading.
Rg
Rf
75 Ω
−
75-Ω Transmission Line
VO1
+
VI
75 Ω
75 Ω
THS3202
N Lines
75 Ω
VON
75 Ω
Figure 87. Video Distribution Amplifier Application
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REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (April 2009) to Revision F
Page
•
Updated document format to current standards ................................................................................................................... 1
•
Deleted lead temperature specification from Absolute Maximum Ratings table .................................................................. 2
•
Changed first sentence of third paragraph of Power Dissipation and Thermal Considerations section ............................ 23
Changes from Revision D (January 2009) to Revision E
Page
•
Deleted feature bullets relating to IMD3 and OIP3 at VCC = 15 V ........................................................................................ 1
•
Replaced figures ................................................................................................................................................................... 1
•
Changed text in first sentence of Description section ........................................................................................................... 1
•
Deleted harmonic distortion specifications in AC Performance subsection for VCC = 15 V .................................................. 6
•
Deleted harmonic distortion graphs for VCC = 15 V ............................................................................................................ 10
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PACKAGE OPTION ADDENDUM
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14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
THS3202D
NRND
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
3202
THS3202DGK
NRND
VSSOP
DGK
8
80
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
BEV
THS3202DGN
NRND
HVSSOP
DGN
8
80
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
BEP
THS3202DGNG4
NRND
HVSSOP
DGN
8
80
RoHS & Green
Level-1-260C-UNLIM
-40 to 85
BEP
THS3202DGNR
NRND
HVSSOP
DGN
8
2500
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
BEP
THS3202DGNRG4
NRND
HVSSOP
DGN
8
2500
RoHS & Green
Level-1-260C-UNLIM
-40 to 85
BEP
NIPDAU
NIPDAU
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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