TLC59284
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SBVS208A – OCTOBER 2012 – REVISED OCTOBER 2012
16-Channel, Constant-Current LED Driver with Switching Delay
Check for Samples: TLC59284
FEATURES
APPLICATIONS
•
•
•
1
2
•
•
•
•
•
•
•
•
•
16-Channel, Constant-Current Sink Output
with On and Off Control
Constant-Current Sink Capability:
– 35 mA (VCC ≤ 3.6 V)
– 45 mA (VCC > 3.6 V)
LED Power-Supply Voltage: Up to 10 V
VCC: 3 V to 5.5 V
Constant-Current Accuracy:
– Channel-to-Channel:
±1.4% (typ), ±3% (max)
– Device-to-Device: ±2% (typ), ±4% (max)
CMOS Logic Level I/O
Data Transfer Rate: 35 MHz
BLANK Pulse Width: 50 ns
Switching Delay for Noise Reduction
Operating Temperature: –40°C to +85°C
Video Displays
Message Boards
DESCRIPTION
The TLC59284 is a 16-channel, constant-current sink
light-emitting diode (LED) driver. Each channel can
be individually controlled with a simple serial
communications protocol that is compatible with 3.3-V
or 5-V CMOS logic levels, depending on the
operating VCC. When the serial data buffer is loaded,
a LAT rising edge transfers the data to the OUTn
outputs. The BLANK pin can be used to turn off all
OUTn outputs during power-on and output data
latching to prevent unwanted image displays during
these times. The constant-current value of all 16
channels is set by a single external resistor.
VLED
OUT0
DATA
¼
¼
¼
¼
¼
¼
SIN
SCLK
Controller
¼
OUT15
LAT
BLANK
OUT15
SOUT
VCC
SCLK
LAT
VCC
VCC
BLANK
BLANK
IREF
RIREF
¼
SIN
VCC
SCLK
LAT
OUT0
SOUT
IREF
GND
Device 1
RIREF
Device n
GND
3
Typical Application Circuit (Multiple Daisy-Chained TLC59284s)
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated
TLC59284
SBVS208A – OCTOBER 2012 – REVISED OCTOBER 2012
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE AND ORDERING INFORMATION (1)
PRODUCT
TLC59284
(1)
PACKAGE-LEAD
ORDERING NUMBER
TRANSPORT MEDIA, QUANTITY
TLC59284DBQR
Tape and Reel, 2500
TLC59284DBQ
Tube, 50
SSOP-24, QSOP-24
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1) (2)
Over operating free-air temperature range, unless otherwise noted.
VALUE
MIN
MAX
UNIT
Supply voltage
VCC
–0.3
+6
V
Input voltage range, VIN
SIN, SCLK, LAT, BLANK, IREF
–0.3
VCC + 0.3
V
Output range, SOUT
–0.3
VCC + 0.3
V
Output range, OUT0 to OUT15
–0.3
+11
V
+50
mA
+150
°C
+150
°C
Human body model (HBM)
4000
V
Charged device model (CDM)
2000
V
Output voltage range, VOUT
Current, IOUT
Output (dc), OUT0 to OUT15
Operating junction, TJ(MAX)
Temperature
Storage range, Tstg
Electrostatic discharge (ESD) ratings
(1)
(2)
–55
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
All voltage values are with respect to network ground terminal.
THERMAL INFORMATION
TLC59284
THERMAL METRIC
(1)
DBQ
UNITS
24 PINS
θJA
Junction-to-ambient thermal resistance
91.5
θJCtop
Junction-to-case (top) thermal resistance
55.2
θJB
Junction-to-board thermal resistance
44.9
ψJT
Junction-to-top characterization parameter
16.8
ψJB
Junction-to-board characterization parameter
44.5
θJCbot
Junction-to-case (bottom) thermal resistance
N/A
(1)
2
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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RECOMMENDED OPERATING CONDITIONS
At TA = –40°C to +85°C, unless otherwise noted.
TLC59284
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
3
5.5
V
10
V
V
DC CHARACTERISTICS (VCC = 3 V to 5.5 V)
VCC
Supply voltage
VO
Voltage applied to output
VIH
Input voltage
VIL
IOH
Output current
IOL
IOLC
OUT0 to OUT15
High
SIN, SCLK, LAT, BLANK
0.7 × VCC
VCC
Low
SIN, SCLK, LAT, BLANK
GND
0.3 × VCC
High
SOUT
Low
SOUT
Constant output sink current
TA
Temperature range
TJ
V
–2
mA
2
mA
OUT0 to OUT15, 3 V ≤ VCC ≤ 3.6 V
2
35
mA
OUT0 to OUT15, 3.6 V < VCC ≤ 5.5 V
2
45
mA
Operating free-air
–40
+85
°C
Operating junction
–40
+125
°C
AC CHARACTERISTICS (VCC = 3 V to 5.5 V)
fCLK
(SCLK)
Data shift clock frequency
SCLK
35
MHz
tWH0
SCLK
10
ns
tWL0
SCLK
10
ns
LAT
20
ns
tWH1
Pulse duration
tWH2
BLANK
100
ns
tWL2
BLANK
50
ns
tSU0
SIN↑↓ – SCLK↑
4
ns
LAT↓ – SCLK↑
10
ns
SIN↑↓ – SCLK↑
4
ns
LAT↓ – SCLK↑
10
ns
tSU1
tH0
tH1
Setup time
Hold time
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ELECTRICAL CHARACTERISTICS
All minimum and maximum specifications are at TA = –40°C to +85°C and VCC = 3 V to 5.5 V, unless otherwise noted.
Typical specifications are at TA = +25°C and VCC = 3.3 V.
TLC59284
PARAMETER
VOH
Output voltage
VOL
TEST CONDITIONS
High
IOH = –2 mA at SOUT
Low
IOL = 2 mA at SOUT
MIN
TYP
VCC – 0.4
VIREF
Reference voltage output
RIREF = 1.5 kΩ, TA = +25°C
IIN
Input current
VIN = VCC or GND at SIN and SCLK
MAX
UNIT
VCC
V
0.4
V
1
μA
1.208
V
–1
ICC0
SIN, SCLK, LAT = GND, BLANK = VOUTn = VCC, RIREF = open
1
2
mA
ICC1
SIN, SCLK, LAT = GND, BLANK = VOUTn = VCC,
RIREF = 3 kΩ (IOUT = 17.6 mA target)
3
4
mA
All OUTn = ON, SIN, SCLK, LAT, BLANK = GND,
VOUTn = 0.8 V, RIREF = 3 kΩ
7
9
mA
All OUTn = ON, SIN, SCLK, LAT, BLANK = GND,
VOUTn = 0.8 V, RIREF = 1.5 kΩ (IOUT = 35.3 mA target)
8
11
mA
35.3
37.7
mA
0.1
μA
0.2
μA
0.07
0.5
μA
Supply current (VCC)
ICC2
ICC3
IOLC
Constant output current
All OUTn = ON, VOUTn = VOUTfix = 0.8 V, RIREF = 1.5 kΩ,
TA = +25°C (see Figure 8)
IOLKG0
Output leakage current
TJ = +25°C
All OUTn = OFF, VOUTn = VOUTfix = 10 V,
T = +85°C
BLANK = VCC, RIREF = 1.5 kΩ (see Figure 8) J
TJ = +125°C
ΔIOLC0
ΔIOLC1
Constantcurrent error
Channel-tochannel (1)
All OUTn = ON, VOUTn = VOUTfix = 0.8 V, RIREF = 1.5 kΩ,
TA = +25°C (see Figure 8)
±1.4
±3
%
Device-todevice (2)
All OUTn = ON, VOUTn = VOUTfix = 0.8 V, RIREF = 1.5 kΩ,
TA = +25°C (see Figure 8)
±2
±4
%
±0.05
±1
%/V
±0.5
±1
%/V
ΔIOLC2
Line regulation (3)
All OUTn = ON, VOUTn = VOUTfix = 0.8 V, RIREF = 1.5 kΩ,
VCC = 3 V to 5.5 V
ΔIOLC3
Load regulation (4)
All OUTn = ON, VOUTn = 0.8 V to 3 V, VOUTfix = 0.8 V,
RIREF = 1.5 kΩ
RPUP
RPDWN
(1)
Resistor
32.9
Pull-up
BLANK
250
500
750
kΩ
Pull-down
LAT
250
500
750
kΩ
The deviation of each output from the average of OUT0 to OUT15 constant-current. Deviation is calculated by the formula:
D (%) =
IOUTn
(IOUT0 + IOUT1 + ... + IOUT14 + IOUT15)
-1
´ 100
16
(2)
The deviation of the OUT0 to OUT15 constant-current average from the ideal constant-current value.
Deviation is calculated by the following formula:
(IOUT0 + IOUT1 + ... IOUT14 + IOUT15)
16
D (%) =
- (Ideal Output Current)
´ 100
Ideal Output Current
Ideal current is calculated by the formula:
IOUT(IDEAL) = 43.8 ´
(3)
(IOUTn at VCC = 5.5 V) - (IOUTn at VCC = 3 V)
(IOUTn at VCC = 3 V)
´
100
5.5 V - 3 V
Load regulation is calculated by the equation:
D (%/V) =
4
RIREF
Line regulation is calculated by this equation:
D (%/V) =
(4)
1.208 V
(IOUTn at VOUTn = 3 V) - (IOUTn at VOUTn = 1 V)
(IOUTn at VOUTn = 1 V)
100
´
3V-1V
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SWITCHING CHARACTERISTICS
All minimum and maximum specifications are at TA = –40°C to +85°C, VCC = 3 V to 5.5 V, CL = 15 pF, RL = 110 Ω,
RIREF = 1.5 kΩ, and VLED = 5.0 V, unless otherwise noted. Typical values are at TA = +25°C and VCC = 3.3 V.
TLC59284
PARAMETER
TYP
MAX
SOUT (see Figure 7)
3
10
OUTn (see Figure 6)
44
SOUT (see Figure 7)
3
OUTn (see Figure 6)
44
tD0
SCLK↑ to SOUT↑↓
11
20
ns
tD1
LAT↑ or BLANK↑↓ to OUT0 on or off, TA = +25°C
60
100
ns
Grouped OUTn on or off to next group on or off,
TA = +25°C
2
tR0
Rise time
tR1
tF0
Fall time
tF1
Propagation delay time
tD2
tON_ERR
(1)
Output on-time error (1)
TEST CONDITIONS
MIN
Output on or off latch data = all '1', 50-ns BLANK GND
level pulse, VCC = 3.3 V, TA = +25°C
–45
UNIT
ns
ns
10
ns
ns
ns
45
ns
Output on-time error (tON_ERR) is calculated by the formula: tON_ERR (ns) = tOUT_ON – BLANK low-level one-shot pulse width (tWL2).
tOUT_ON indicates the actual on-time of the constant-current output.
PIN CONFIGURATIONS
DBQ PACKAGE
SSOP-24 AND QSOP-24
(TOP VIEW)
GND
1
24
VCC
SIN
2
23
IREF
SCLK
3
22
SOUT
LAT
4
21
BLANK
OUT0
5
20
OUT15
OUT1
6
19
OUT14
OUT2
7
18
OUT13
OUT3
8
17
OUT12
OUT4
9
16
OUT11
OUT5
10
15
OUT10
OUT6
11
14
OUT9
OUT7
12
13
OUT8
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PIN DESCRIPTIONS
PIN
NAME
6
NUMBER
I/O
DESCRIPTION
All outputs empty (blank); Schmitt buffer input. When BLANK is high, all constant-current outputs (OUT0
to OUT15) are forced off. When BLANK is low, all constant-current outputs are controlled by the data in
the output on or off data latch. This pin is internally pulled up to VCC with a 500-kΩ (typ) resistor.
BLANK
21
I
GND
1
—
Power ground
IREF
23
I/O
Constant-current value setting, the OUT0 to OUT15 sink constant-current outputs are set to the desired
values by connecting an external resistor between IREF and GND.
LAT
4
I
Level-triggered latch; Schmitt buffer input. The data in the 16-bit shift register continue to transfer to the
output on or off data latch while LAT is high. Therefore, if the data in the 16-bit shift register are changed
when LAT is high, the data in the data latch are also changed. The data in the data latch are held when
LAT is low. This pin is internally pulled down to GND with a 500-kΩ (typ) resistor.
OUT0
5
O
Constant-current output. Each output can be tied together with others to increase the constant-current.
Different voltages can be applied to each output.
OUT1
6
O
Constant-current output
OUT2
7
O
Constant-current output
OUT3
8
O
Constant-current output
OUT4
9
O
Constant-current output
OUT5
10
O
Constant-current output
OUT6
11
O
Constant-current output
OUT7
12
O
Constant-current output
OUT8
13
O
Constant-current output
OUT9
14
O
Constant-current output
OUT10
15
O
Constant-current output
OUT11
16
O
Constant-current output
OUT12
17
O
Constant-current output
OUT13
18
O
Constant-current output
OUT14
19
O
Constant-current output
OUT15
20
O
Constant-current output
SCLK
3
I
Serial data shift clock; Schmitt buffer input.
All data in the 16-bit shift register are shifted toward the MSB by a 1-bit SCLK synchronization.
SIN
2
I
Serial data input for driver on or off control; Schmitt buffer input.
When SIN is high, the LSB is set to '1' for only one SCLK input rising edge. If two SCLK rising edges are
input while SIN is high, then the 16-bit shift register LSB and LSB+1 are set to '1'. When SIN is low, the
LSB is set to '0' at the SCLK input rising edge.
SOUT
22
O
Serial data output. This output is connected to the 16-bit shift register MSB. SOUT data changes at the
SCLK rising edge.
VCC
24
—
Power-supply voltage
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SBVS208A – OCTOBER 2012 – REVISED OCTOBER 2012
FUNCTIONAL BLOCK DIAGRAM
VCC
VCC
SIN
LSB
MSB
16-Bit Shift Register
(1 Bit x 16 Channels)
SCLK
0
SOUT
15
¼
MSB
LSB
LAT
Output On/Off Data Latch
(1 Bit x 16 Channels)
0
15
¼
BLANK
16-Channel Constant-Current Sink Driver
with Switching Delay
IREF
GND
GND
¼
OUT0
OUT1
OUT14 OUT15
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PARAMETER MEASUREMENT INFORMATION
PIN-EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
VCC
VCC
INPUT
BLANK
GND
GND
Figure 1. SIN and SCLK
Figure 3. BLANK
VCC
VCC
LAT
SOUT
GND
GND
Figure 2. LAT
Figure 4. SOUT
OUTn
(1)
GND
(1)
n = 0 to 15.
Figure 5. OUT0 Through OUT15
8
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TEST CIRCUITS
RL
VCC
VCC
OUTn
IREF
RIREF
VLED
CL
GND
Figure 6. OUTn Rise and Fall Time Test Circuit
VCC
SOUT
VCC
CL
GND
Figure 7. SOUT Rise and Fall Time Test Circuit
VCC
OUT0
¼
VCC
IREF
¼
RIREF
OUTn
GND OUT15
VOUTfix
VOUTn
Figure 8. OUTn Constant-Current Test Circuit
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TIMING DIAGRAMS
tWH0, tWL0, tWH1, tWH2, tWL2:
VCC
Input
(1)
50%
GND
tWL
tWH
tSU0, tSU1, tH0, tH1:
VCC
SCLK
(1)
50%
GND
tSU
tH
VCC
Data and Control
Clock
50%
(1)
GND
(1) Input pulse rise and fall time is 1 ns to 3 ns.
Figure 9. Input Timing Diagram
(1)
tR0, tR1, tF0, tF1, tD0, tD1, tD2, tD3, tON_ERR :
VCC
Input
(2)
50%
GND
tWL2
tD
VOH or VOUTn
90%
Output
50%
10%
tOUT_ON
VOL or VOUTn
tR or tF
(1) tON_ERR is calculated by tOUTON – tWL2.
(2) Input pulse rise and fall time is 1 ns to 3 ns.
Figure 10. Output Timing Diagram
10
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SIN
DATA
0A
DATA
15B
DATA
13B
DATA
14B
DATA
12B
DATA
11B
DATA
3B
DATA
2B
DATA
1B
DATA
0B
tH0
tSU0
tH1
tWH0
DATA
15C
DATA
14C
DATA
13C
DATA
12C
DATA
11C
DATA
10C
1
2
3
tWL0
4
5
6
tSU1
SCLK
1
2
3
4
5
13
14
15
16
tWH1
LAT
DATA
15B
DATA
14B
DATA
13B
DATA
12B
DATA
3B
DATA
2B
DATA
1B
DATA
0B
DATA
15C
DATA
14C
DATA
13C
DATA
12C
DATA
11C
Shift Register
LSB+1 Data (Internal)
DATA
1A
DATA
0A
DATA
15B
DATA
14B
DATA
13B
DATA
4B
DATA
3B
DATA
2B
DATA
1B
DATA
0B
DATA
15C
DATA
14C
DATA
13C
DATA
12C
Shift Register
MSB-1 Data (Internal)
DATA
14A
DATA
13A
DATA
12A
DATA
11A
DATA
10A
DATA
2A
DATA
1A
DATA
15B
DATA
14B
DATA
13B
DATA
12B
DATA
11B
DATA
10B
DATA
9B
Shift Register
MSB Data (Internal)
DATA
15A
DATA
14A
DATA
13A
DATA
12A
DATA
11A
DATA
3A
DATA
2A
DATA
1A
DATA
15B
DATA
14B
DATA
13B
DATA
12B
DATA
11B
DATA
10B
¼
¼
Output On or Off Control
Data Latch (Internal)
Previous On or Off Control Data
(1)
SOUT
¼
DATA
0A
¼
Shift Register
LSB Data (Internal)
DATA
15A
DATA
14A
DATA
13A
DATA
12A
tD0
DATA
2A
DATA
1A
DATA
0A
Latest On or Off Control Data
DATA
15B
DATA
14B
DATA
13B
tR0/tF0
DATA
12B
DATA
11B
DATA
10B
tWH2
BLANK
tWL2
OFF
OUT0
OFF
ON
ON
OFF
OUT1, 15
tD1
tD1
tOUTON
tD2
tD2
OFF
ON
ON
¼
¼
¼
¼
tF1
tR1
OFF
OUT7, 9
ON
tD2
tD2
OFF
OUT8
OFF
ON
OFF
ON
ON
(1) Output on or off data = FFFFh.
(2) tON_ERR = tOUTON – tWL2.
Figure 11. Data Write and Output On or Off Timing Diagram
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TYPICAL CHARACTERISTICS
At TA = +25°C and VCC = 3.3 V, unless otherwise noted.
REFERENCE RESISTOR
vs OUTPUT CURRENT
OUTPUT CURRENT vs
OUTPUT VOLTAGE (VCC = 3.3 V)
50
100
Output Current (mA)
Reference Resistor (kW)
40
26.5
10.6
10
5.29
3.53
2.65
2.12 1.76
1
10
20
30
Output Current (mA)
30
25
20
15
40
0
50
0
0.5
1
G020
OUTPUT CURRENT vs OUTPUT VOLTAGE
(VCC = 3.3 V, Magnified)
39
IO = 45 mA
38
IO = 40 mA
37
35
IO = 35 mA
30
IO = 30 mA
25
IO = 20 mA
Output Current (mA)
40
20
15
IO = 10 mA
IO = 5 mA
5
0.5
1
1.5
2
Output Voltage (V)
36
35
34
33
TA = −40°C
TA = +25°C
TA = +85°C
32
IO = 2 mA
0
VCC = 3.3 V
VOUTn = 0.8 V
IO = 35 mA
2.5
31
3
0
0.5
1
Output Voltage (V)
G001
Figure 14.
39
VCC = 5.0 V
VOUTn = 0.8 V
IO = 35 mA
37
G004
ΔIOLC vs AMBIENT TEMPERATURE
3
38
1.5
Figure 15.
OUTPUT CURRENT vs OUTPUT VOLTAGE
(VCC = 5.0 V, Magnified)
2
VOUTn = 0.8 V
IO = 20 mA
1
36
∆IOLC (%)
Output Current (mA)
3
G000
OUTPUT CURRENT vs
OUTPUT VOLTAGE (VCC = 5.0 V)
10
35
34
0
−1
33
TA = −40°C
TA = +25°C
TA = +85°C
32
0
0.5
1
Output Voltage (V)
−2
1.5
−3
−40
G005
Figure 16.
12
2.5
Figure 13.
45
31
1.5
2
Output Voltage (V)
Figure 12.
VCC = 5.0 V, VOUTn = 0.8 V, TA = +25°C
50
Output Current (mA)
35
5
1.32
55
0
IO = 10 mA
IO = 5 mA
IO = 2 mA
10
1.51
1.18
0
IO = 35 mA
IO = 30 mA
IO = 20 mA
VCC = 3.3 V
VOUTn = 0.8 V
TA = +25°C
45
VCC = 3.3 V
VCC = 5.0 V
−20
0
20
40
60
Ambient Temperature (°C)
80
100
G006
Figure 17.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C and VCC = 3.3 V, unless otherwise noted.
SUPPLY CURRENT vs OUTPUT CURRENT
SUPPLY CURRENT vs AMBIENT TEMPERATURE
12
12
VCC = 5.0 V
VCC = 3.3 V
11
10
10
9
ICC (mA)
ICC (mA)
VCC = 3.3 V
VCC = 5.0 V
11
8
9
8
7
5
4
7
SIN = 17.5 MHz
SCLK = 35 MHz
All Outputs On
TA = +25°C
6
0
10
20
30
Output Current (mA)
40
SIN = 17.5 MHz
SCLK = 35 MHz
All Outputs On
IO = 35 mA
6
5
−40
50
−20
0
20
40
60
80
Ambient Temperature (°C)
G018
Figure 18.
100
G008
Figure 19.
CONSTANT-CURRENT OUTPUT
VOLTAGE WAVEFORM
CH1-BLANK
(50 ns)
Channel 1
(5 V/div)
Channel 2
(2 V/div)
Channel 3
(2 V/div)
Channel 4
(2 V/div)
CH2-OUT0
(BLANK = 50 ns)
IO = 35 mA
TA = +25°C
RL = 110 W
CL = 15 pF
VCC = 5 V
VLED = 5 V
CH3-OUT1
(BLANK = 50 ns)
CH4-OUT2
(BLANK = 50 ns)
Time (20 ns/div)
G021
Figure 20.
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TLC59284
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DETAILED DESCRIPTION
CONSTANT SINK CURRENT VALUE SETTING
The constant-current values are determined by an external resistor (RIREF) placed between IREF and GND. The
resistor (RIREF) value is calculated by Equation 1.
RIREF (kW) =
VIREF (V)
´ 43.8
IOLC (mA)
Where:
VIREF = the internal reference voltage on the IREF pin (typically 1.208 V)
(1)
IOLC must be set in the range of 2 mA to 35 mA when VCC is less than 3.6 V. Also, when VCC is equal to 3.6 V or
greater, IOLC must be set in the range of 2 mA to 45 mA. The constant sink current characteristic for the external
resistor value is illustrated in Figure 12. Table 1 describes the constant-current output versus external resistor
value.
Table 1. Constant-Current Output versus External Resistor Value
IOLC (mA)
RIREF (kΩ, Typical)
45 (VCC > 3.6 V only)
1.18
40 (VCC > 3.6 V only)
1.32
35
1.51
30
1.76
25
2.12
20
2.65
15
3.53
10
5.29
5
10.6
2
26.5
CONSTANT-CURRENT DRIVER ON OR OFF CONTROL
When BLANK is low, the corresponding output is turned on if the data in the on or off control data latch are '1'
and remains off if the data are '0'. When BLANK is high, all outputs are forced off. This control is shown in
Table 2.
Table 2. Output On or Off Control Data Truth Table
OUTPUT ON OR OFF DATA
CONSTANT-CURRENT OUTPUT
STATUS
0
Off
1
On
When the device is initially powered on, the data in the 16-bit shift register and output on or off data latch are not
set to default values. Therefore, the output on or off data must be written to the data latch before turning the
constant-current output on. BLANK should be high when powered on because the constant-current may be
turned on as a result of random data in the output on or off data latch.
14
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REGISTER CONFIGURATION
The TLC59284 has a 16-bit shift register and an output on or off data latch. Both the shift register and data latch
are 16 bits long and are used to turn the constant-current outputs on and off. Figure 21 shows the shift register
and data latch configuration. The data at the SIN pin are shifted into the 16-bit shift register LSB at the rising
edge of the SCLK pin; SOUT data change at the SCLK rising edge.
16-Bit Shift Register (1 Bit ´ 16 Channels)
SOUT
MSB
15
14
13
12
On or Off
Data for
OUT15
On or Off
Data for
OUT14
On or Off
Data for
OUT13
On or Off
Data for
OUT12
4
11
¼
3
2
1
LSB
0
On or Off
Data for
OUT3
On or Off
Data for
OUT2
On or Off
Data for
OUT1
On or Off
Data for
OUT0
3
2
1
LSB
0
On or Off
Data for
OUT3
On or Off
Data for
OUT2
On or Off
Data for
OUT1
On or Off
Data for
OUT0
SIN
SCLK
¼
MSB
15
14
13
12
On or Off
Data for
OUT15
On or Off
Data for
OUT14
On or Off
Data for
OUT13
On or Off
Data for
OUT12
4
11
¼
Output On or Off Data Latch (1 Bit ´ 16 Channels)
LAT
16 Bits
To Constant-Current Driver Control Block
Figure 21. 16-Bit Shift Register and Output On or Off Data Latch Configuration
The output on or off data in the 16-bit shift register continue to transfer to the output on or off data latch while
LAT is high. Therefore, if the data in the 16-bit shift register are changed when LAT is high, the data in the data
latch are also changed. The data in the data latch are held when LAT is low. When the device initially powers on,
the data in the output on or off shift register and latch are not set to default values; on or off control data must be
written to the on or off control data latch before turning the constant-current output on. All constant-current
outputs are forced off when BLANK is high. The OUTn on or off outputs are controlled by the data in the output
on or off data latch. The writing data truth table and timing diagram are shown in Table 3 and Figure 22,
respectively.
Table 3. Truth Table in Operation
SCLK
LAT
BLANK
SIN
OUT0…OUT7…OUT15
SOUT
↑
High
Low
Dn
Dn…Dn – 7…Dn – 15
Dn – 15
↑
Low
Low
Dn + 1
No change
Dn – 14
↑
High
Low
Dn + 2
Dn + 2…Dn – 5…Dn – 13
Dn – 13
↓
—
Low
Dn + 3
Dn + 2…Dn – 5…Dn – 13
Dn – 13
↓
—
High
Dn + 3
Off
Dn – 13
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TLC59284
SBVS208A – OCTOBER 2012 – REVISED OCTOBER 2012
0
1
2
3
4
5
6
D15
D14
D13
D12
D11 D10
www.ti.com
7
8
9
10
11
12
13
14
15
SCLK
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SIN
LAT
BLANK
D0
OFF
OUT0
ON
OFF
OUT1
D1
ON
OFF
OUT2
D2
ON
D3
OFF
OUT3
ON
¼
¼
¼
¼
OFF
D15
OUT15
ON
SOUT
Don’t Care
D15
Figure 22. Operation Timing Diagram
NOISE REDUCTION
Large surge currents may flow through the device and board if all 16 outputs turn on or off simultaneously. These
large current surges can induce detrimental noise and electromagnetic interference (EMI) into other circuits. The
TLC59284 independently turns on or off the outputs for each group with a 1-ns (typ) delay time; see Figure 11.
The 16 outputs are grouped into nine groups of either one or two outputs: group 1 (OUT0), group 2 (OUT1 and
OUT15), group 3 (OUT2 and OUT14), group 4 (OUT3 and OUT13), group 5 (OUT4 and OUT12), group 6 (OUT5
and OUT11), group 7 (OUT6 and OUT10), group 8 (OUT7 and OUT9), and group 9 (OUT9). Both turn-on and
turn-off times are delayed when BLANK transitions from low to high or high to low. Also when output-on and -off
data are changed at the LAT rising edge while BLANK is low, both turn-on and turn-off times are delayed.
However, the state of each output is controlled by the data in the output on or off data latch and the BLANK
level.
16
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SBVS208A – OCTOBER 2012 – REVISED OCTOBER 2012
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (October 2012) to Revision A
Page
•
Changed HBM ESD rating maximum specification in Absolute Maximum Ratings table ..................................................... 2
•
Changed ICC2 maximum specification in Electrical Characteristics table .............................................................................. 4
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TLC59284DBQ
ACTIVE
SSOP
DBQ
24
50
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TLC59284
TLC59284DBQR
ACTIVE
SSOP
DBQ
24
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TLC59284
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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