TLC5949
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SBVS219A – DECEMBER 2012 – REVISED DECEMBER 2012
16-Channel, 12-Bit, ES-PWM, Full Self-Diagnosis LED Driver for
7-Bit Global BC LED Lamp
Check for Samples: TLC5949
FEATURES
1
•
•
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
16 Constant-Current Sink Output Channels
Sink Current Capability with
Maximum BC Data: 2 mA to 45 mA
Global Brightness Control (BC):
– 7-Bit (128 Steps) with 25% to 100% Range
Grayscale Control (GS) with Enhanced
Spectrum or Conventional PWM:
– 12-Bit (4096 Steps)
LED Power-Supply Voltage: Up to 10 V
VCC: 3.0 V to 3.6 V
Constant-Current Accuracy:
– Channel-to-Channel: ±0.6% (typ), ±2% (max)
– Device-to-Device: ±1% (typ), ±4% (max)
Data Transfer Rate: 33 MHz
Grayscale Control Clock: 33 MHz
Auto Display Repeat and Auto Data Refresh
Display Timing Reset
Power-Save Mode to Minimize VCC Current
LOD and LSD with Invisible Detection
Mode (IDM)
Output Leakage Detection (OLD)
Current Reference Terminal Short Flag (ISF)
Thermal Shutdown (TSD) and Error Flag (TEF)
•
Pre-Thermal Warning (PTW)
Four-Channel Grouped Delay Switching to
Prevent Inrush Current
Operating Temperature: –40°C to +85°C
APPLICATIONS
•
•
LED Video Displays
LED Signboards
DESCRIPTION
The TLC5949 is a 16-channel, constant-current sink
LED driver. Each channel has an individuallyadjustable, pulse width modulation (PWM) grayscale
(GS) brightness control with 4096 steps. All channels
have a 128-step global brightness control (BC). BC
adjusts brightness deviation with other LED drivers.
GS and BC data are accessible with a serial interface
port.
The TLC5949 has six error flags: LED open detection
(LOD), LED short detection (LSD), output leakage
detection (OLD), reference current terminal short flag
detection (ISF), pre-thermal warning (PTW), and
thermal error flag (TEF). The error detection results
can be read with a serial interface port.
VLED
OUT0
DATA
¼
¼
¼
¼
¼
¼
¼
SCLK
SOUT
LAT
GSCLK
Device 1
OUT15
SOUT
VCC
SCLK
LAT
VCC
Device n
VCC
GSCLK
GSCLK
IREF
Controller
¼
SIN
VCC
SCLK
LAT
OUT0
OUT15
SIN
IREF
GND
RIREF
GND
RIREF
3
Data Read
Typical Application Circuit (Multiple Daisy-Chained TLC5949s)
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated
TLC5949
SBVS219A – DECEMBER 2012 – REVISED DECEMBER 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE AND ORDERING INFORMATION (1)
PRODUCT
PACKAGE DESIGNATOR
DBQ
TLC5949
PWP
(1)
ORDERING NUMBER
TRANSPORT MEDIA
TLC5949DBQR
Tape and Reel
TLC5949DBQ
Tube
TLC5949PWPR
Tape and Reel
TLC5949PWP
Tube
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range, unless otherwise noted.
VALUE
MIN
Voltage (2)
Current
(1)
(2)
–0.3
+6.0
V
SIN, SCLK, LAT, GSCLK, IREF
–0.3
VCC + 0.3
V
SOUT
–0.3
VCC + 0.3
V
OUT0 to OUT15
–0.3
+11
V
+60
mA
+150
°C
Operating junction, TJ (max)
Storage, Tstg
Electrostatic discharge (ESD) ratings
UNIT
VCC
OUT0 to OUT15
Temperature
MAX
+150
°C
Human body model (HBM)
–55
3000
V
Charged device model (CDM)
2000
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to device ground terminal.
THERMAL INFORMATION
TLC5949
THERMAL METRIC (1)
DBQ
(SSOP, QSOP)
PWP
(HTSSOP)
24 PINS
24 PINS
θJA
Junction-to-ambient thermal resistance
80.4
39.9
θJCtop
Junction-to-case (top) thermal resistance
44.2
23.2
θJB
Junction-to-board thermal resistance
33.5
21.5
ψJT
Junction-to-top characterization parameter
8.8
0.6
ψJB
Junction-to-board characterization parameter
33.2
21.3
θJCbot
Junction-to-case (bottom) thermal resistance
N/A
3.8
(1)
2
UNITS
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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SBVS219A – DECEMBER 2012 – REVISED DECEMBER 2012
RECOMMENDED OPERATING CONDITIONS
At TA = –40°C to +85°C and VCC = 3 V to 3.6 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
DC CHARACTERISTICS
VCC
Supply voltage
VO
Voltage applied to output
OUT0 to OUT15
3.0
3.6
V
10
VIH
High-level input voltage
SIN, SCLK, LAT, GSCLK
V
0.7 × VCC
VCC
V
VIL
Low-level input voltage
SIN, SCLK, LAT, GSCLK
IOH
High-level output current
SOUT
GND
0.3 × VCC
–2
mA
IOL
Low-level output current
SOUT
2
mA
IOLC
Constant output sink current
OUT0 to OUT15,
3 V ≤ VCC ≤ 3.6 V
45
mA
TA
Operating free-air temperature range
–40
+85
°C
TJ
Operating junction temperature range
–40
+125
°C
V
AC CHARACTERISTICS
fCLK
fCLK
(SCLK)
Data shift clock frequency
SCLK
33
MHz
(GSCLK)
Grayscale control clock frequency
GSCLK
33
MHz
tWH0
SCLK
10
ns
tWL0
SCLK
10
ns
GSCLK
10
ns
tWL1
GSCLK
10
ns
tWH2
LAT
30
ns
tSU0
SIN↑↓ to SCLK↑
5
ns
tSU1
LAT↑ to SCLK↑
120
ns
LAT↑ for BLANK bit '0' set to
GSCLK↑
50
ns
LAT↑ for GS data written to
GSCLK↑ when display time
reset mode is enabled
100
ns
SCLK↑ to SIN↑↓
5
ns
SCLK↑ to LAT↑
5
ns
tWH1
tSU2
Pulse duration
Setup time
tSU3
tH0
tH1
Hold time
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SBVS219A – DECEMBER 2012 – REVISED DECEMBER 2012
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ELECTRICAL CHARACTERISTICS
At TA = –40°C to +85°C and VCC = 3 V to 3.6 V, unless otherwise noted. Typical values are at TA = +25°C and VCC = 3.3 V.
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
(SOUT)
IOH = –2 mA
VOL
Low-level output voltage
(SOUT)
IOL = 2 mA
MIN
TYP
VCC – 0.4
MAX
UNIT
VCC
V
0.4
V
VLOD0
All OUTn = on, LODVLT = 00
0.25
0.30
0.35
V
VLOD1
All OUTn = on, LODVLT = 01
0.55
0.6
0.65
V
All OUTn = on, LODVLT = 10
0.85
0.9
0.95
V
VLOD3
All OUTn = on, LODVLT = 11
1.15
1.2
1.25
V
VLSD0
All OUTn = on, LSDVLT = 00
0.30 × VCC
0.35 × VCC
0.40 × VCC
V
VLSD1
All OUTn = on, LSDVLT = 01
0.40 × VCC
0.45 × VCC
0.50 × VCC
V
All OUTn = on, LSDVLT = 10
0.50 × VCC
0.55 × VCC
0.60 × VCC
V
All OUTn = on, LSDVLT = 11
0.60 × VCC
0.65 × VCC
0.70 × VCC
V
1.17
1.20
1.23
V
1
μA
VLOD2
VLSD2
LED open-detection threshold
LED short-detection threshold
VLSD3
VIREF
Reference voltage output
RIREF = 1.1 kΩ
IIN
Input current
(SIN, SCLK, LAT, GSCLK)
VIN = VCC or GND
–1
ICC0
SIN, SCLK, LAT, and GSCLK = GND, BLANK = 1,
GSn = FFFh, BC = 7Fh, VOUTn = 0.8 V,
RIREF = open (all outputs off)
1.5
3
mA
ICC1
SIN, SCLK, LAT, and GSCLK = GND, BLANK = 1,
GSn = FFFh, BC = 7Fh,
VOUTn = 0.8 V, RIREF = 2.2 kΩ
(all outputs off, IOUTn = 23.1-mA target)
5
7
mA
ICC2
SIN, SCLK, and LAT = GND, BLANK = 0, auto display
repeat enabled, GSCLK = 33 MHz, GSn = FFFh,
BC = 7Fh, VOUTn = 0.8 V, RIREF = 2.2 kΩ
(IOUT = 23.1-mA target)
7
9
mA
ICC3
SIN, SCLK, and LAT = GND, BLANK = 0, auto display
repeat enabled, GSCLK = 33 MHz, GSn = FFFh,
BC = 7Fh, VOUTn = 0.8 V, RIREF = 1.1 kΩ
(IOUT = 46.1-mA target)
11
14
mA
ICC4
VCC = 3.3 V, SIN, SCLK, LAT, and GSCLK = GND,
BLANK = 0, auto display repeat enabled, GSn = 000h,
BC = 7Fh, in power-save mode,
VOUTn = 0.8 V, RIREF = 1.1 kΩ
(IOUT = 46.1-mA target)
10
40
µA
46.1
48.8
mA
TJ = +25°C
0.1
μA
TJ = +85°C (1)
0.2
μA
0.8
μA
Supply current (VCC)
IOLC0
Constant output sink current
(OUT0 to OUT15)
All OUTn = on, BC = 7Fh, VOUTn = VOUTfix = 0.8 V,
RIREF = 1.1 kΩ, TA = +25°C
(IOLCn = 46.1-mA target)
Output leakage current
(OUT0 to OUT15)
All OUTn = off, BLANK = 1,
VOUTn = VOUTfix = 10 V,
RIREF = 1.1 kΩ
IOLKG0
IOLKG1
IOLKG2
(1)
4
TJ = +125°C (1)
43.4
0.3
Not tested; specified by design.
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SBVS219A – DECEMBER 2012 – REVISED DECEMBER 2012
ELECTRICAL CHARACTERISTICS (continued)
At TA = –40°C to +85°C and VCC = 3 V to 3.6 V, unless otherwise noted. Typical values are at TA = +25°C and VCC = 3.3 V.
TYP
MAX
ΔIOLC0
Constant-current error
(channel-to-channel,
OUT0 to OUT15) (2)
PARAMETER
All OUTn = on, BC = 7Fh, VOUTn = VOUTfix = 0.8 V,
RIREF = 1.1 kΩ, TA = +25°C
(IOUTn = 46.1-mA target)
±0.6
±2
%
ΔIOLC1
Constant-current error
(device-to-device,
OUT0 to OUT15) (3)
All OUTn = on, BC = 7Fh, VOUTn = VOUTfix = 0.8 V,
RIREF = 1.1 kΩ, TA = +25°C
(IOUTn = 46.1-mA target)
±1
±4
%
ΔIOLC2
Line regulation
(OUT0 to OUT15) (4)
VCC = 3.0 V to 3.6 V, all OUTn = on, BC = 7Fh,
VOUTn = VOUTfix = 0.8 V, RIREF = 1.1 kΩ
(IOUTn = 46.1-mA target)
±0.1
±1
%/V
ΔIOLC3
Load regulation
(OUT0 to OUT15) (5)
All OUTn = on, BC = 7Fh, VOUTn = 0.8 V to 3.0 V,
VOUTfix = 0.8 V, RIREF = 1.1 kΩ
(IOUTn = 46.1-mA target)
±0.1
±1
%/V
TTEF
Thermal error flag threshold
Junction temperature (6)
150
165
180
°C
THYS
Thermal error flag hysteresis
Junction temperature (6)
5
10
20
°C
TPTW
Pre-thermal warning threshold
Junction temperature (6)
125
138
150
°C
(2)
TEST CONDITIONS
MIN
UNIT
The deviation of each output from the OUT0 to OUT15 constant-current average. Deviation is calculated by the formula:
IOLCn
D (%) = 100 ´
-1
IOLC0 + IOLC1 + ... + IOLC14 + IOLC15
16
(3)
where n = 0 to 15.
Deviation of the OUT0 to OUT15 constant-current average from the ideal constant-current value. Deviation is calculated by the formula:
(IOLC0 + IOLC1 + ... IOLC14 + IOLC15)
D (%) = 100 ´
16
- Ideal Output Current
Ideal Output Current
Ideal current is calculated by the formula:
IOUTn =
(4)
Line regulation is calculated by the formula:
D (%/V) =
(5)
(IOLCn at VCC = 3.6 V) - (IOLCn at VCC = 3 V)
´
IOLCn at VCC = 3 V
100
3.6 V - 3 V
where n = 0 to 15.
Load regulation is calculated by the equation:
D (%/V) =
(6)
1 3/4 BC
´ IOLCMax
+
4
127
(IOLCn at VOUTn = 3 V) - (IOLCn at VOUTn = 0.8 V)
IOLCn at VOUTn = 0.8 V
´
100
3 V - 0.8 V
where n = 0 to 15.
Not tested; specified by design.
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TLC5949
SBVS219A – DECEMBER 2012 – REVISED DECEMBER 2012
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SWITCHING CHARACTERISTICS (See Figure 4, Figure 5, and Figure 8 through Figure 11)
At TA = –40°C to +85°C, VCC = 3 V to 3.6 V, CL = 15 pF, RL = 82 Ω, RIREF = 1.1 kΩ, and VLED = 5.0 V, unless otherwise noted.
Typical values are at VCC = 3.3 V and TA = +25°C.
PARAMETER
tR0
Rise time
tR1
tF0
Fall time
tF1
TEST CONDITIONS
MIN
TYP
SOUT
MAX
5
OUTn and BC = 7Fh
13
SOUT
UNIT
ns
ns
5
ns
OUTn and BC = 7Fh
23
tD0
SCLK↑ to SOUT↑↓
15
25
ns
tD1
LAT↑ for BLANK = 1 and OUT0, OUT7, OUT8, and OUT15 off
40
75
ns
tD2
GSCLK↑ to OUT0, OUT7, OUT8, and OUT15 on/off with BC = 7Fh
5
36
65
ns
tD3
GSCLK↑ to OUT1, OUT6, OUT9, and OUT14 on/off with BC = 7Fh
20
62
97
ns
tD4
GSCLK↑ to OUT2, OUT5, OUT10, and OUT13 on/off with BC = 7Fh
35
88
129
ns
tD5
GSCLK↑ to OUT3, OUT4, OUT11, and OUT12 on/off with BC = 7Fh
50
114
161
ns
tD6
LAT↑ to power-save mode by writing data for OUTn off with BLANK = 1
and PSMODE = 110
200
ns
tD7
SCLK↑ to normal mode with PSMODE = 101 or LAT ↑ to normal mode
by writing GS data for OUTn on with BLANK = 1 and PSMODE = 110
50
µs
10
ns
Propagation delay
tON_ERR
(1)
6
Output on-time error (1)
tOUTON – tGSCLK, GSn = 001h, GSCLK = 33 MHz,
BC = 7Fh, TA = +25°C
–20
ns
Output on-time error (tON_ERR) is calculated by the formula: tON_ERR = tOUT_ON – tGSCLK. tOUTON is the actual on-time of the constantcurrent driver. tGSCLK is the GSCLK period.
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SBVS219A – DECEMBER 2012 – REVISED DECEMBER 2012
PARAMETER MEASUREMENT INFORMATION
PIN-EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
VCC
INPUT
GND
Figure 1. SIN, SCLK, LAT, GSCLK
VCC
SOUT
GND
Figure 2. SOUT
VCC
OUTn
(1)
GND
(1) n = 0 to 15.
Figure 3. OUT0 Through OUT15
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TEST CIRCUITS
RL
VCC
VCC
OUTn
IREF
RIREF
(1)
VLED
(2)
CL
GND
(1) n = 0 to 15.
(2) CL includes measurement probe and jig capacitance.
Figure 4. Rise Time and Fall Time Test Circuit for OUTn
VCC
SOUT
VCC
CL
GND
(1)
(1) CL includes measurement probe and jig capacitance.
Figure 5. Rise Time and Fall Time Test Circuit for SOUT
VCC
OUT0
¼
VCC
IREF
(1)
¼
RIREF
OUTn
GND OUT15
VOUTfix
VOUTn
(1) n = 0 to 15.
Figure 6. Constant-Current Test Circuit for OUTn
8
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SBVS219A – DECEMBER 2012 – REVISED DECEMBER 2012
TIMING DIAGRAMS
tWH0, tWL0, tWH1, tWL1, tWH2:
VCC
Input
(1)
50%
GND
tWH
tWL
tSU0, tSU1, tSU2, tSU3, tH0, tH1:
VCC
Clock Input
(1)
50%
GND
tSU
tH
VCC
Data and Control
Clock
(1)
50%
GND
(1)
Input pulse rise and fall time is 1 ns to 3 ns.
Figure 7. Input Timing
tR0, tR1, tF0, tF1, tD0, tD1, tD2, tD3, tD4, tD5, tD6, tD7:
VCC
Input
(1)
50%
GND
tD
VOH or VOUTnH
90%
Output
50%
10%
VOL or VOUTnL
tR or tF
(1)
Input pulse rise and fall time is 1 ns to 3 ns.
Figure 8. Output Timing
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GS Data Write
GS Data Write
SIN
GS0
0A
Low
GS15
15B
GS15
14B
GS15
13B
GS0
3B
GS15
12B
GS0
2B
GS0
0B
GS0
1B
tH0
tSU0
tH1
tWH0
Low
GS15
15C
GS15
14C
GS15
13C
1
2
3
4
GS15
12C
GS15
11C
GS15
10C
6
7
tSU1
SCLK
1
2
4
3
5
190
191
192
193
tWL0
5
tWH1
tGSCLK
GSCLK
4094
4096
1
4095
3
2
5
4
tWH2
6
tWL1
LAT
tSU2, tSU3
BLANK Bit
In First Control Data Latch
(Internal)
Data = 0
Grayscale Data
In First GS Data Latch
(Internal)
New Data
Old Data
The data in the 193-bit common shift register are copied
to the first and second GS data latches when the display
timing reset is enabled.
Grayscale Data
In Second GS Data Latch
(Internal)
New Data
Old Data
tD0
SOUT
Low
RSV
tD0
RSV
RSV
RSV
RSV
(1)
RSV
RSV
RSV
Low
RSV
RSV
RSV
RSV
LOD
15
LOD
14
LOD
13
tR0, tF0
Display Timing Reset Enabled, Auto Display Repeat Disabled, All GS Data Are FFFh
OUT0, OUT7,
OUT8, OUT15
OFF
OUT1, OUT6,
OUT9, OUT14
OFF
OUT2, OUT5,
OUT10, OUT13
OFF
ON
(VOUTnH)
tR1
tF1
tD2
tD2
(VOUTnL)
ON
tD3
tD3
ON
tD4
tD4
OUT3, OUT4,
OUT11, OUT12
OFF
ON
tD5
tD5
Display Timing Reset Enabled, Auto Display Repeat Disabled, All GS Data Are 001h
OUT0, OUT7,
OUT8, OUT15
OFF
ON
tD2
OUT1, OUT6,
OUT9, OUT14
ON
tOUTON
OFF
ON
tD4
OUT3, OUT4,
OUT11, OUT12
(2)
OFF
tD3
OUT2, OUT5,
OUT10, OUT13
tOUTON
tOUTON
OFF
ON
tD5
tOUTON
(1) RSV = reserved.
(2) tOUTON refers to tON_ERR = tOUTON – tGSCLK.
Figure 9. Grayscale Data Write Timing
10
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Low
SIN
SCLK
1
2
3
191
192
193
1
2
3
4
5
6
¼
LAT
BLANK Bit
In Control Data Latch
(Internal)
'1'
PSMODE Bit
In Control Data Latch
(Internal)
001b
First Grayscale
Data Latch
(Internal)
Previous On/Off Data
All Data Are ‘0'
First and second GS data latches are changed
simultaneously because the BLANK bit is '1'.
Second Grayscale
Data Latch
(Internal)
Previous On/Off Data
All Data Are '0'
OFF
OUT0, OUT7,
OUT8, OUT15
ON or OFF
ON or OFF
OUT1, OUT6,
OUT9, OUT14
ON or OFF
ON or OFF
OUT2, OUT5,
OUT10, OUT13
ON or OFF
ON or OFF
OUT3, OUT4,
OUT11, OUT12
ON or OFF
ON or OFF
Normal Mode
Normal Mode
ON
OFF
ON
OFF
ON
OFF
Power-Save Mode
More Than 100 mA
ICC
(VCC Current)
ON
Power-Save Mode
tD6
Normal Mode
tD7
Less Than 100 mA
Figure 10. Power-Save Mode Timing
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SIN
RSV
8A
RSV
6A
RSV
7A
RSV
5A
RSV
3A
RSV
4A
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RSV
2A
RSV
1A
RSV
(1)
tH0
tSU0
High NV(2)
0A
NV
NV
3
4
RSV
2B
RSV
0B
RSV
1B
tSU1
tWH0
SCLK
185
186
187
188
189
190
191
192
tWL0
193
tH1
1
tWH1
2
191
192
193
LAT
BLANK Bit
In First Control Data Latch
(Internal)
Data = 0
BC Data
In First Control Data Latch
(Internal)
Old Data
Data = 1
New Data
Next New Data
tD0
SOUT
OUT0, OUT7, OFF
OUT8, OUT15 ON
RSV
7
RSV
6
RSV
5
(VOUTnH)
RSV
4
RSV
3
RSV
2
RSV
1
tR0/tF0
RSV
0
High
NV
tD1
NV
NV
NV
RSV
2A
RSV
1A
RSV
0A
High
OUTn is turned off when the BLANK bit is ‘1’.
(VOUTnL)
tD2
OUT1, OUT6, OFF
OUT9, OUT14 ON
tD3
OUT2, OUT5, OFF
OUT10, OUT13 ON
tD4
OUT3, OUT4, OFF
OUT11, OUT12 ON
(1) RSV = reserved.
(2) NV = Not valid; these data are not used for any function.
Figure 11. Control Data Write Timing
12
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PIN CONFIGURATION
DBQ AND PWP PACKAGES
SSOP-24, QSOP-24, AND HTSSOP-24
(TOP VIEW)
GND
1
24
VCC
SIN
2
23
IREF
SCLK
3
22
SOUT
LAT
4
21
GSCLK
OUT0
5
20
OUT15
OUT1
6
19
OUT14
OUT2
7
18
OUT13
OUT3
8
17
OUT12
OUT4
9
16
OUT11
OUT5
10
15
OUT10
OUT6
11
14
OUT9
OUT7
12
13
OUT8
(1)
PowerPAD
(Bottom Side)
NOTE: The PowerPAD only applies to the PWP package.
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PIN DESCRIPTIONS
PIN
NAME
NO.
I/O
GND
1
—
GSCLK
IREF
14
21
23
DESCRIPTION
Power ground
I
Grayscale (GS) pulse width modulation (PWM) reference clock control for OUTn.
When BLANK = 0, each GSCLK rising edge increments the GS counter for PWM control.
When BLANK = 1, all constant-current outputs (OUT0 to OUT15) are forced off, the GS counter is reset
to '0', and the GS PWM timing controller is initialized.
I/O
Reference current terminal.
A resistor connected between IREF to GND sets the maximum current for all constant-current outputs.
When IREF is shorted to GND with low resistance, all constant-current outputs are forced off and the
IREF short flag (ISF) bit in the status information data (SID) is set to '1'.
The LAT rising edge either latches the data from the 193-bit common shift register into the first GS data
latch when the common shift register MSB is '0' or latches the data into the first control data latch when
the common shift register MSB is '1'.
When the display timing reset bit (TMGRST) in the first control data latch is '1', the GS counter is
initialized at the LAT signal for GS data writes. At the same time, the data in the 193-bit common shift
register are copied to the first and second GS data latches simultaneously and the BC data in the first
control data latch are copied to the second data latch.
LAT
4
I
OUT0
5
O
OUT1
6
O
OUT2
7
O
OUT3
8
O
OUT4
9
O
OUT5
10
O
OUT6
11
O
OUT7
12
O
OUT8
13
O
OUT9
14
O
OUT10
15
O
OUT11
16
O
OUT12
17
O
OUT13
18
O
OUT14
19
O
OUT15
20
O
SCLK
3
I
Serial data shift clock.
Data present on SIN are shifted to the 193-bit common shift register LSB with the SCLK rising edge. Data
in the shift register are shifted towards the MSB at each SCLK rising edge.
The common shift register MSB appears on SOUT.
SIN
2
I
193-bit common shift register serial data input.
Constant-current outputs.
Multiple outputs can be configured in parallel to increase the constant-current capability.
Different voltages can be applied to each output.
SOUT
22
O
193-bit common shift register serial data output.
LED open detection (LOD), LED short detection (LSD), output leak detection (OLD), thermal error flag
(TEF), and the IREF pin short flag (ISF) bits can be read out with SOUT as SID after the LAT rising edge.
SOUT is connected to the 193-bit common shift register MSB. Data are clocked out at the SCLK rising
edge.
VCC
24
—
Power-supply voltage
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FUNCTIONAL BLOCK DIAGRAM
VCC
lodlsdlat
VCC
LSB
oldlat
LOD, LSD, and OLD
Data Latch
ISF
48
MSB
SIN
193-Bit Common Shift Register
0
SCLK
lat
SOUT
192
Bit 192
192
LSB
MSB
First Grayscale (GS) Data Latch
191
0
192
MSB
LSB
Second GS Data Latch
188
LSB
MSB
First Control Data Latch
LAT
0
48
136
119
oldlat
192
MSB
LSB
TEF and
PTW
lat
118
Function Control Bit
TEF
0
17
13
GS Counter,
Auto Repeat,
Refresh
PTW
Second Control Data Latch
for BC Only
lat2nd
lodlsdlat
lat
UVLO
GSCLK
2
191
0
12-Bit ES PWM Timing Control
7
Thermal
Detection
16
7
ISF
Four-Channel Grouped Switched Delay
16
IREF
Reference
Current
Control with
7-Bit BC
Constant Sink Current Driver
with 7-Bit BC
¼
4
GND
LOD, LSD, OLD
¼
OUT0
OUT1
OUT14
OUT15
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TYPICAL CHARACTERISTICS
At TA = +25°C, unless otherwise noted.
70
25380
10152
10k
VCC = 3.3 V
BC = 7Fh
VOUTn = 0.8 V
TA = +25°C
60
5076
3384
2538
1692
2030
1269 1128
1450
1k
1015
923
846
Output Current (mA)
RIREF, Reference Resistor (kW)
100k
50
40
IOLCMax = 30 mA
30
IOLCMax = 20 mA
20
IOLCMax = 2 mA
20
30
40
50
60
IOLC, Output Current (V)
0
0.5
1.5
2
3
2.5
Output Voltage (V)
G011
Figure 13. OUTPUT CURRENT vs
OUTPUT VOLTAGE (+3.3 V)
3
49
VCC = 3.3 V
BC = 7Fh
VOUTn = 0.8 V
RIREF = 1.13 kW
48
47
2
1
DIOLC (%)
46
45
44
0
-1
43
TA = -40°C
42
TA = +25°C
TA = +25°C
BC = 7Fh
VLED = 0.8 V
-2
TA = +85°C
-3
41
0
0.5
1
1.5
2
2.5
Output Voltage (V)
0
3
10
20
30
40
60
50
Output Current (mA)
G013
Figure 14. OUTPUT CURRENT vs
OUTPUT VOLTAGE (+3.3 V)
G003
Figure 15. CONSTANT-CURRENT ERROR
vs OUTPUT CURRENT
3
70
RIREF = 1.13 kW
BC = 7Fh
VLED = 0.8 V
IO = 60 mA
60
Output Current (mA)
2
1
G001
Figure 12. REFERENCE RESISTOR
vs OUTPUT CURRENT
Output Current (mA)
IOLCMax = 10 mA
0
10
0
1
DIOLC (%)
IOLCMax = 5 mA
10
100
0
-1
-2
IO = 45 mA
50
IO = 30 mA
40
30
20
IO = 10 mA
IO = 2 mA
10
-3
0
-40
-20
0
20
40
60
80
Ambient Temperature (°C)
100
0
16
32
48
64
80
BC Data (Decimal)
G004
Figure 16. CONSTANT-CURRENT ERROR vs
AMBIENT TEMPERATURE
16
IOLCMax = 45 mA
96
112
128
G006
Figure 17. GLOBAL BRIGHTNESS CONTROL LINEARITY
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TYPICAL CHARACTERISTICS (continued)
25
25
20
20
15
15
ICC (mA)
ICC (mA)
At TA = +25°C, unless otherwise noted.
10
TA = +25°C
BC = 7Fh
2 ´ SIN = SCLK = 33 MHz
GSCLK = 33 MHz
All Outputs On
5
10
RIREF = 1.13 kW
BC = 7Fh
2 ´ SIN = SCLK = 33 MHz
GSCLK = 33 MHz
All Outputs On
5
0
0
0
10
20
30
40
50
Output Current (mA)
60
-40
Figure 18. SUPPLY CURRENT vs OUTPUT CURRENT
-20
0
20
40
60
ICC (mA)
12
RIREF = 1.13 kW
BC = 7Fh
SIN = SCLK = Low
GSCLK = Low
Power-Save Mode
100
G008
Figure 19. SUPPLY CURRENT vs AMBIENT TEMPERATURE
16
14
80
Ambient Temperature (°C)
G007
Channel 1
GSCLK
Ch 1 (5 V/div)
Ch 2 (2 V/div)
Channel 2
OUT0
10
8
Ch 3 (2 V/div)
6
4
Ch 4 (2 V/div)
2
RIREF = 0.85 kW
VCC = 3.3 V
VLED = 5 V
BC = 7Fh, GS = 001h
RL = 68 W, CL = 15 pF
GSCLK = 33 MHz
Channel 3
OUT1
Channel 4
OUT4
0
-40
-20
0
20
40
60
Ambient Temperature (°C)
80
100
Time (20 ns/div)
G010
G009
Figure 20. SUPPLY CURRENT IN POWER-SAVE MODE
vs AMBIENT TEMPERATURE
Figure 21. CONSTANT-CURRENT OUTPUT
VOLTAGE WAVEFORM
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DETAILED DESCRIPTION
MAXIMUM CONSTANT SINK CURRENT VALUE
The maximum output current value of each channel (IOLCMax) is programmed by a single resistor (RIREF) that is
placed between the IREF and GND pins. The current value can be calculated by Equation 1:
RIREF =
VIREF
´ 42.3
IOLCMax
Where:
VIREF = the internal reference voltage on IREF, typically 1.20 V when the global brightness control (BC) data
are at maximum
IOLCMax = 2 mA to 45 mA with BC = 7Fh
(1)
IOLCMax is the highest current for each output. Each output sinks IOLCMax current when it is turned on, and the
global brightness control (BC) data are set to the maximum value of 7Fh (127). Each output sink current can be
reduced by lowering the BC value.
RIREF must be between 1.13 kΩ and 25.4 kΩ in order to hold IOLCMax between 45 mA (typ) and 2 mA (typ).
Otherwise, the output may be unstable. Output currents lower than 2 mA can be achieved by setting IOLCMax to
2 mA or higher and then using global BC to lower the output current.
Table 1 shows the characteristics of the constant-current sink versus the external resistor, RIREF.
Table 1. Maximum Constant-Current Output versus
External Resistor Value
IOLCMax (mA)
RIREF (kΩ, typ)
45
1.13
40
1.27
35
1.45
30
1.70
25
2.03
20
2.53
15
3.38
10
5.08
5
10.2
2
25.4
GLOBAL BRIGHTNESS CONTROL (BC) FUNCTION
The TLC5949 is capable of adjusting the output current of all constant-current outputs simultaneously. This
function is called global brightness control (BC). The global BC for all outputs (OUT0 to OUT15) is programmed
with a 7-bit word. The global BC adjusts all output currents in 128 steps from 25% to 100%, where 100%
corresponds to the maximum output current set by RIREF. Equation 2 calculates the actual output current as a
function of RIREF and global BC value. BC data can be set via the serial interface. When the device is powered
on, the BC data in the first and second control data latches contain random data. Therefore, BC data must be
written to the BC data latch before turning the constant-current output on.
The output current value controlled by BC can be calculated by Equation 2.
IOUTn =
1 3/4 BC
´ IOLCMax
+
4
127
Where:
IOLCMax = the maximum constant-current value for each output determined by RIREF
BC = the global brightness control value in the second control data latch (0h to 7Fh)
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Table 2 summarizes the BC data versus the set current value.
Table 2. BC Data versus Constant-Current Ratio and Set Current Value
BC DATA
BINARY
DECIMAL
HEX
RATIO OF OUTPUT
CURRENT TO IOLCMax(%)
IOUT (mA)
(IOLCMax= 45 mA, typ)
IOUT (mA)
(IOLCMax= 2 mA, typ)
000 0000
0
00h
25.0
11.25
0.50
000 0001
1
01h
25.6
11.52
0.51
000 0010
2
02h
26.2
11.78
0.52
—
—
—
—
—
—
111 1101
125
7Dh
98.8
44.47
1.98
111 1110
126
7Eh
99.4
44.73
1.99
111 1111
127
7Fh
100.0
45.00
2.00
GRAYSCALE (GS) FUNCTION (PWM CONTROL)
The TLC5949 can adjust the brightness of each output channel using a pulse width modulation (PWM) control
scheme. The architecture of 12 bits per channel results in 4096 brightness steps, from 0% up to 100%
brightness.
The PWM operation for OUTn is controlled by a 12-bit grayscale (GS) counter. The GS counter increments on
each GS reference clock (GSCLK) rising edge. The GS counter resets to 000h when the BLANK bit in the first
control data latch is set to '1'; the counter value is held at 000h while the BLANK bit is '1', even if the GS clock
input is toggled high and low.
The TLC5949 has two types of PWM control: conventional PWM control and enhanced spectrum (ES) PWM
control. The conventional PWM control can be selected when the ESPWM bit in the first control data latch is '0'.
The ES PWM control is selected when the ESPWM bit is '1'.
The on-time (tOUT_ON) of each output (OUTn) can be calculated by Equation 3.
tOUT_ON = tGSCLK × GSn
(3)
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Table 3 summarizes the GS data values versus the output on-time duty cycle. When the device powers up, the
BLANK bit in the first control data latch is set to '1'. The 193-bit common shift register and the first and second
GS data latches contain random data. Therefore, GS data must be written to the GS latches before the BLANK
bit is set to '0'. All constant-current outputs are off when the BLANK bit is '1'.
Table 3. Output Duty Cycle and On-Time versus GS Data
GS DATA
GS DATA
DECIMAL
HEX
ON-TIME DUTY (%)
DECIMAL
HEX
ON-TIME DUTY (%)
0
1
000h
0
2048
800h
50.001
001h
0.002
2049
801h
50.002
2
002h
0.003
2050
802h
50.004
3
003h
0.005
2051
803h
50.005
—
—
—
—
—
—
511
1FFh
12.499
2559
9FFh
62.499
512
200h
12.500
2560
A00h
62.501
513
201h
12.502
2561
A01h
62.502
—
—
—
—
—
—
1023
3FFh
24.999
3071
BFFh
74.997
1024
400h
25.000
3072
C00h
74.998
1025
401h
25.002
3073
C01h
75.000
—
—
—
—
—
—
1535
5FFh
37.499
3583
DFFh
87.500
1536
600h
37.501
3584
E00h
87.501
1537
601h
37.502
3585
E01h
87.503
—
—
—
—
—
—
2045
7FDh
49.996
4093
FFDh
99.997
2046
7FEh
49.998
4094
FFEh
99.998
2047
7FFh
49.999
4095
FFFh
100.000
Conventional PWM Control
In this PWM control, the GS clock is enabled when the BLANK bit is set to '0'. The first GS clock rising edge after
the BLANK bit is set to '0' increments the GS counter by one and switches on all outputs with a non-zero GS
value programmed into the second GS data latch. Each additional GS clock rising edge increases the
corresponding GS counter by one.
The GS counter keeps track of the number of clock pulses from the GS clock inputs. Each output stays on while
the counter is less than or equal to the programmed GS value. Each output turns off at the GS counter value
rising edge when the counter becomes greater than the output GS latch value. Figure 22 illustrates the
conventional PWM operation.
20
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BLANK Bit
(Internal)
(1)
1
2
3
4095
4096
4097
2048
2049
2050
4
1
2
3 4
GSCLK
OUTn
(GSDATA = 000h)
OFF
OUTn
(GSDATA = 001h)
OFF
OUTn
(GSDATA = 002h)
OFF
OUTn
(GSDATA = 003h)
OFF
OUTn
(GSDATA = 7FFh)
OFF
OUTn
(GSDATA = 800h)
OFF
OUTn
(GSDATA = 801h)
OFF
OUTn
(GSDATA = FFDh)
OFF
OUTn
(GSDATA = FFEh)
OFF
OUTn
(GSDATA = FFFh)
OFF
ON
(VOUTnH)
(VOUTnL)
See (2)
No drivers turn on when GS data are '0'.
(VOUTnH)
t = GSCLK ´ 1
(VOUTnL)
ON
t = GSCLK ´ 2
(VOUTnH)
(VOUTnL)
ON
(VOUTnH)
t = GSCLK ´ 3
(VOUTnL)
ON
(VOUTnH)
t = GSCLK ´ 2047
(VOUTnL)
ON
(VOUTnH)
t = GSCLK ´ 2048
(VOUTnL)
ON
(VOUTnH)
t = GSCLK ´ 2049
(VOUTnL)
ON
(VOUTnH)
t = GSCLK ´ 4093
(VOUTnL)
ON
(VOUTnH)
t = GSCLK ´ 4094
(VOUTnL)
ON
(VOUTnH)
t = GSCLK ´ 4095
See (3)
See (4)
(VOUTnL)
ON
(1) The internal signal is generated when LAT inputs GS data with the display timing reset bit (TMGRST) set to '1'. This signal has the same
function as a BLANK = 1 pulse. Furthermore, the signal is generated at the 4096th GSCLK when the auto display repeat bit (DSPRPT) is set
to '1'.
(2) The GS counter begins to count GSCLK pulses after the BLANK bit is set to '0' or when the LAT signal for a GS data write is input with
the display time reset mode enabled.
(3) OUTn turns on at the first GSCLK rising edge except when GS data are '0' after the BLANK bit is set to '0' or when the LAT signal for a
GS data write is input with the display time reset mode enabled.
(4) OUTn does not turn on again until BLANK is set to '1' at least one time, except when the TMGRST or DSPRPT bits are '1'.
Figure 22. Conventional PWM Operation
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Enhanced Spectrum (ES) PWM Control
In this PWM control, the total display period is divided into 32 display segments. The total display period is the
time from the first GS clock (GSCLK) to the 4096th GSCLK input after the BLANK bit is set to '0'. Each display
segment has a maximum of 128 GSCLKs. The OUTn on-time changes, depending on the 12-bit GS data. Refer
to Table 4 for the sequence of information and to Figure 23 for the timing information.
Table 4. ES PWM Drive Turn-On Time Length
GS DATA
22
DECIMAL
HEX
OUTn DRIVER OPERATION
0
000h
Does not turn on
1
001h
Turns on for one GSCLK period in the first display segment
2
002h
Turns on for one GSCLK period in the first and 17th display segments
3
003h
Turns on for one GSCLK period in the first, 17th, and 9th display segments
4
004h
Turns on for one GSCLK period in the first, 17th, 9th, and 25th display segments
5
005h
Turns on for one GSCLK period in the first, 17th, 9th, 25th, and 5th display segments
6
006h
Turns on for one GSCLK period in the first, 17th, 9th, 25th, 5th, and 21th display segments
—
—
The number of display segments where OUTn is turned on for one GSCLK is incremented by
increasing GS data in the following order:
1 > 17 > 9 > 25 5 > 21 > 13 > 29 > 3 > 19 > 11 > 27 > 7 > 23 > 15 > 31 > 2 > 18 > 10 > 26 > 6 >
22 > 14 > 30 > 4 > 20 > 12 > 28 > 8 > 24 > 16 > 32.
31
01Fh
Turns on for one GSCLK period in the first to 31st display segments, but does not turn on in the
32nd display segment
32
020h
Turns on for one GSCLK period in all display segments (first to 32nd)
33
021h
Turns on for two GSCLK periods in the first display period and for one GSCLK period in all other
display periods
—
—
The number of display segments where OUTn is turned on for one GSCLK is incremented by
increasing GS data in the following order:
1 > 17 > 9 > 25 5 > 21 > 13 > 29 > 3 > 19 > 11 > 27 > 7 > 23 > 15 > 31 > 2 > 18 > 10 > 26 > 6 >
22 > 14 > 30 > 4 > 20 > 12 > 28 > 8 > 24 > 16 > 32.
63
03Fh
Turns on for two GSCLK periods in the first to 31st display segments and turns on one GSCLK
period in the 32nd display segment
64
040h
Turns on for two GSCLK periods in all display segments (first to 32nd)
65
041h
Turns on for three GSCLK periods in the first display segment and for two GSCLK periods in all
other display segments
—
—
4063
EDFh
Turns on for 127 GSCLK periods in the first to 31st display segments, but only turns on for 126
GSCLK periods in the 32nd display segment
4064
FE0h
Turns on for 127 GSCLK periods in all display segments (first to 32nd)
4065
FE1h
Turns on for 128 GSCLK periods in the first display period and for 127 GSCLK periods in the
second to 32nd display segments
—
—
4094
FFEh
Turns on for 128 GSCLK periods in the first to 15th and 17th to 31st display segments; also turns
on for 127 GSCLK periods in the 16th and 32nd display segments.
4095
FFFh
Turns on for 128 GSCLK periods in the first to 31st display segments but only turns on for 127
GSCLK periods in the 32nd display segment
The number of display segments where OUTn is turned on for one GSCLK is incremented by
increasing GS data in the following order:
1 > 17 > 9 > 25 5 > 21 > 13 > 29 > 3 > 19 > 11 > 27 > 7 > 23 > 15 > 31 > 2 > 18 > 10 > 26 > 6 >
22 > 14 > 30 > 4 > 20 > 12 > 28 > 8 > 24 > 16 > 32.
—
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BLANK Bit in the
First Control Data Latch
(Internal)
(1)
1022
127
1 2 3 ¼
129
¼
128
130
2046
1025
1023
1024
2049
2047
2048
1026 ¼
1027
3070
2050 ¼
2051
3073
3071
3072
3074 ¼
3075
3967
3970
4096
3968
¼ 4094
3969
4095
GSCLK
1st Period
(Voltage Level = High)
OUTn OFF
(GS Data = 000h)
ON
9th
2nd ¼ 8th
Period Period
Period
¼
17th
16th
Period Period
¼
24th
Period
32nd
Period
25th ¼ 31st
Period
Period
1st
Period
(Voltage Level = Low)
t = GSCLK ´ 1d
OUTn OFF
(GS Data = 001h)
ON
Note (2)
t = GSCLK ´ 1d
t = GSCLK ´ 1d
OUTn OFF
(GS Data = 002h)
ON
t = GSCLK ´ 1d
t = GSCLK ´ 1d
t = GSCLK ´ 1d
OUTn OFF
(GS Data = 003h)
ON
t = GSCLK ´ 1d
t = GSCLK ´ 1d
t = GSCLK ´ 1d
OUTn OFF
(GS Data = 004h)
ON
t = GSCLK ´ 1d
t = GSCLK ´ 1d
t = GSCLK
t = GSCLK ´ 1d
OUTn OFF
(GS Data = 010h)
ON
t = GSCLK ´ 1d
t = GSCLK ´ 1d
t = GSCLK ´ 1d
t = GSCLK ´ 1d
OUTn OFF
(GS Data = 020h)
ON
t = GSCLK ´ 1d
t = GSCLK ´ 1d
t = GSCLK ´ 1d
t = GSCLK ´ 1d
t = GSCLK ´ 1d
t = GSCLK ´ 1d
t = GSCLK ´ 1d
t = GSCLK ´ 2d
t = GSCLK ´ 1d
OUTn OFF
(GS Data = 021h)
ON
t = GSCLK ´ 1d
t = GSCLK ´ 1d
t = GSCLK ´ 1d
t = GSCLK ´ 1d
t = GSCLK ´ 2d
t = GSCLK ´ 2d
OUTn OFF
(GS Data = 022h)
ON
t=
GSCLK ´ 127
t = GSCLK ´ 127 in 2nd to 32nd Period
t = GSCLK ´ 128
t = GSCLK ´ 127 in 2nd to 32nd Period
t = GSCLK ´ 128
t = GSCLK ´ 128 in 2nd to 15th and 17th to 31st Periods,
t = GSCLK ´ 127 in 16th Period
t=
GSCLK ´ 127
t = GSCLK ´ 128
t = GSCLK ´ 128 in 2nd to 31st Period
t=
GSCLK ´ 127
OUTn OFF
(GS Data = F80h)
ON
OUTn OFF
(GS Data = F81h)
ON
OUTn OFF
(GS Data = FFEh)
ON
OUTn OFF
(GS Data = FFFh)
ON
(1) The internal signal is generated when LAT inputs GS data when the display timing reset bit (TMGRST) is set to '1'. This signal has the
same function as BLANK = 1. Furthermore, the signal is generated at the 4096th GSCLK when the auto display repeat bit (DSPRPT) is set to
'1'.
(2) When auto display repeat is on.
Figure 23. ES PWM Operation
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Auto Display Repeat Function
This function can repeat the total display period as long as GSCLK is present, as shown in Figure 24. This
function is switched on or off by the content of the DSPRPT bit in the first control data latch.
When the DSPRPT bit is '1', auto display repeat is enabled and the entire display period automatically repeats.
When the DSPRST bit is '0', the auto display repeat is disabled and the entire display period executes only one
time after either the BLANK bit is changed from '1' to '0', or after a LAT signal rising edge for a GS data write is
input when the display timing reset is enabled.
BLANK Bit
in First Control Data Latch
(Internal)
BLANK = 1 (Blank)
BLANK = 0 (Not Blank)
3
1 2
4
5
4094
1
4095
2
4096
4093
4
5
3
4095
4094
1
4095
2
4096
4093
3
4
5
6
7
8
9 10
1 2
4094
1
4095
2
4096
GSCLK
'1' (Auto Display
Repeat Enabled)
DSPRPT Bit
in First Control Data Latch
(Internal)
DSPRPT = 0
(Auto Display
Repeat Disabled)
1st Entire Display Period
2nd Entire Display Period
Display period is repeated with
Auto display repeat function.
3rd Entire Display Period
1st Entire
Display Period
OUTn is forced off
when BLANK is set to '1'.
OFF
OUTn
(GS Data = FFFh)
Note (1)
ON
(1) OUTn is not turned on until BLANK changes from '1' to '0' or until LAT changes from low to high for a GS data write with TMGRST = 1.
Figure 24. Auto Display Repeat Function
Auto Data Refresh Function
This function allows grayscale (GS) data and global brightness control (BC) data to be input at any time without
synchronizing the input to the display timing. If GS and BC data are sent during a display period, the input data
are held in the first latch for each data register. The data are then transferred to the second latch when the
4096th GSCLK occurs. The second latch data are used for the next display period. Refer to Figure 25 and
Figure 26 for the auto data refresh function timing. However, when the BLANK bit in the first control data latch is
set to '1' before the 4096th GSCLK occurs, the first latch data immediately upload to the second latch. Also,
when a LAT rising edge occurs while the BLANK bit is '1', the selected shift register data are transferred to the
first and second latch at the same time. The data of bits 119-136 (BLANK, DSPRPT, TMGRST, ESPWM,
LODVLT, LSDVLT, LATTMG, IDMENA, IDMRPT, IDMCUR, OLDEN, and PSMODE) in the control data latch
immediately update whenever the data are written into the first latch.
24
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GS Data Write
GS0
4A
SIN
188
189
GS0
3A
190
GS Data Write
Control Data Write
GS0
2A
GS0
1A
191
192
GS0
0A
High
193
Not
Valid
Not
Valid
2
3
1
RSV
3A
RSV
2A
190
191
RSV
1A
192
RSV
(1)
193
0A
Low
GS15
15B
1
2
GS15
14B
GS15
13B
3
4
SCLK
LAT
4096
4095 1 2
3
4
5 6
7
8
GSCLK
BLANK Bit
in First Control Data Latch
(Internal)
(2)
Data = 0
Common Shift Register
(Internal)
First GS Data Latch
(Internal)
Old GS Data
New GS Data
Second GS Data Latch
(Internal)
Old GS Data
New GS Data
First Control Data Latch
(Internal)
Old Control Data
New Control Data
Second Control Data Latch
(Internal)
Old Control Data
New Control Data
OFF
OUTn
Controlled by New Data
GS and BC Controlled by Old Data
ON
Low
(Bit 193 Data)
SOUT
GS15
15A
GS15
14A
GS15
13A
GS0
2A
GS0
1A
GS0
0A
High
(1) RSV = reserved.
(2) BLANK data do not change with Auto Display Repeat enabled.
Figure 25. Auto Data Refresh Function 1
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GS Data Write
GS0
4A
SIN
188
189
GS0
3A
190
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Control Data Write
GS0
2A
191
GS0
1A
192
GS0
0A
High
193
Control Data Write
Not
Valid
Not
Valid
2
3
1
RSV
3A
RSV
2A
190
RSV
1A
191
RSV
192
(1)
0A
193
High
1
Not
Valid
Not
Valid
3
2
RSV
0A
193
SCLK
LAT
1
2
3
GSCLK
BLANK Bit
in First Control Data Latch
(Internal)
(2)
Data = 0
Data = 1
'0'
Common Shift Register
(Internal)
First GS Data Latch
(Internal)
New GS Data
Old GS Data
Second GS Data Latch
(Internal)
Old GS Data
New GS Data
First Control Data Latch
(Internal)
Old Control Data
New Data
Second Control Data Latch
(Internal)
Old Control Data
New Data
OFF
OUTn
New Data
Note (3)
GS and BC Controlled by Old Data
ON
SOUT
Low
(Bit 193 Data)
GS15
15A
GS15
14A
GS15
13A
GS0
2A
GS0
1A
GS0
0A
High
(Bit 193 Data)
Not
Valid
High
(1) RSV = reserved.
(2) The BLANK bit value is changed after the LAT rising edge.
(3) GS and BC are controlled by new data.
Figure 26. Auto Data Refresh Function 2
Display Timing Reset Function
The display timing reset function allows initializing the display timing with a LAT rising edge for a GS data write.
This function can be switched on or off with the TMGRST bit in the first control data latch. When the TMGRST bit
is '1', the GS counter is reset to '0' and all outputs are forced off at the LAT rising edge for a GS data write.
Furthermore, the data in the 193-bit common shift register are copied to the first and second GS data latches at
the same time. In addition, the BC data in the first control data latch are transferred to the second data latch
simultaneously. This configuration is identical to the BLANK bit when it changes data from '0' to '1' and '1' to '0'.
Therefore, the BLANK bit is not required to control the display reset. PWM control resumes from the next GSCLK
rising edge. When the TMGRST bit is '0', the GS counter is not reset and the outputs are not forced off even with
a LAT rising edge.
26
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REGISTER AND DATA LATCH CONFIGURATION
The TLC5949 has one common shift register and two pairs of data latches: the first and second grayscale (GS)
data latches and the first and second control data latches. The common shift register is 193 bits long and the GS
data latches are 192 bits long in total. The first control data latch is 137 bits long and the second latch is 119 bits
long. When the common shift register MSB is '0', the least significant 256 bits from the common shift register are
latched into the first GS data latch. When the MSB is '1', the data are latched into the first control data latch.
Figure 27 shows the common shift register and latch configurations.
Common Shift Register (193Bits)
LSB
MSB
SOUT
Latch
Select
Bit
192
Common Common Common Common Common
Data Bit Data Bit Data Bit Data Bit Data Bit
191
190
189
188
187
191
190
189
188
Common Common Common Common Common Common
Data Bit Data Bit Data Bit Data Bit Data Bit Data Bit
0
5
4
3
2
1
187
5
4
3
2
1
SIN
SCLK
0
Lower 192 Bits
192 Bits
First Grayscale (GS) Data Latch (192 Bits)
MSB
191
180
48
47
32
31
16
15
LSB
0
OUT15
Bit 15
OUT15
Bit 0
OUT3
Bit 0
OUT2
Bit 15
OUT2
Bit 0
OUT1
Bit 15
OUT1
Bit 0
OUT0
Bit 15
OUT0
Bit 0
GS Data for OUT15
GS Data for OUT2
GS Data for OUT1
This latch pulse comes
from the LAT pin when
the MSB of the Common
Shift Register is '0'.
GS Data for OUT0
192 Bits
Second Grayscale (GS) Data Latch (192 Bits)
MSB
191
180
48
47
32
31
16
15
LSB
0
OUT15
Bit 15
OUT15
Bit 0
OUT3
Bit 0
OUT2
Bit 15
OUT2
Bit 0
OUT1
Bit 15
OUT1
Bit 0
OUT0
Bit 15
OUT0
Bit 0
GS Data for OUT15
GS Data for OUT2
GS Data for OUT1
The 4096th GSCLK is used
to latch the data when the
Auto Display Repeat is
enabled or when the BLANK bit
is set to '1'.
GS Data for OUT0
192 Bits
To GS Timing Control Circuit
Lower 137 Bits of 192 Bits
First Control Data Latch (137 Bits)
MSB
136-119 118-112 111-105 104-98
FUNC
Bits
17-0
BC
Bits[6:0]
for OUTn
FC,
18 Bits
BC,
7 Bits
(1)
RSV
Bits
RSV
Bits
97-91
90-84
27-21
20-14
13-7
LSB
6-0
RSV
Bits
RSV
Bits
RSV
Bits
RSV
Bits
RSV
Bits
RSV
Bits
This latch pulse
comes from the
LAT pin when the
MSB of the Common
Shift Register is ‘1’.
112 Reserved Bits (Write ‘1’ to All Bits)
119 Bits
Second Control Data Latch (119 Bits)
MSB
118-112 111-105 104-98
BC
Bits[6:0]
for OUTn
RSV
Bits
RSV
Bits
BC,
7 Bits
18 Bits
7 Bits
To
To
Global Brightness
Function
Control Circuit
Control Circuit
97-91
90-84
27-21
20-14
13-7
LSB
6-0
RSV
Bits
RSV
Bits
RSV
Bits
RSV
Bits
RSV
Bits
RSV
Bits
The 4096th GSCLK is used
to latch the data when the
Auto Display Repeat is
enabled or when the BLANK bit
is set to '1'.
112 Reserved Bits (Write '1' to All Bits)
112 Bits
No
Applied
Bits
(1) RSV = reserved.
Figure 27. Common Shift Register and Control Data Latches Configuration
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193-Bit Common Shift Register
The 193-bit common shift register is used to shift data from the SIN pin into the TLC5949. The data shifted into
the register are used for GS and global BC functions. The common shift register LSB is connected to SIN and
the MSB is connected to SOUT. On each SCLK rising edge, the data on SIN are shifted into the LSB and all 193
bits are shifted towards the MSB. The register MSB is always connected to SOUT. When the device is powered
up, the data in the 193-bit common shift register are random.
First and Second Grayscale (GS) Data Latch
The first and second GS data latches are each 192 bits long, and set the PWM timing for each constant-current
output. The on-time of all constant-current outputs is controlled by the data in the second GS data latch. A LAT
rising edge when the common shift register MSB is '0' shifts the least significant 192 bits of the common shift
register into the first GS latch. The GS data from the first latch are copied into the second latch either when the
4096th GSCLK occurs with the auto display repeat mode enabled, a LAT rising edge for a GS data write occurs
with the display timing reset mode enabled, or the BLANK bit in the first control data latch is set to '1'.
When the device is powered up, the data in the first and second latches are random. Therefore, GS data must
be written to the GS data latches before turning on the constant-current output. The first and second GS data
latch configurations are shown in Figure 28. The data bit assignment is shown in Table 5.
From Common Shift Register
192 Bits
First Grayscale (GS) Data Latch (192 Bits)
MSB
191
180
48
47
32
31
16
15
LSB
0
OUT15
Bit 15
OUT15
Bit 0
OUT3
Bit 0
OUT2
Bit 15
OUT2
Bit 0
OUT1
Bit 15
OUT1
Bit 0
OUT0
Bit 15
OUT0
Bit 0
GS Data for OUT15
GS Data for OUT2
GS Data for OUT1
This latch pulse comes
from the LAT pin when
the MSB of the Common
Shift Register is ‘0’.
GS Data for OUT0
192 Bits
Second Grayscale (GS) Data Latch (192 Bits)
MSB
191
180
48
47
32
31
16
15
LSB
0
OUT15
Bit 15
OUT15
Bit 0
OUT3
Bit 0
OUT2
Bit 15
OUT2
Bit 0
OUT1
Bit 15
OUT1
Bit 0
OUT0
Bit 15
OUT0
Bit 0
GS Data for OUT2
GS Data for OUT15
GS Data for OUT1
The 4096th GSCLK is used
to latch the data when the
Auto Display Repeat is
enabled or when the BLANK bit
is set to ‘1’.
GS Data for OUT0
192 Bits
To GS Timing Control Circuit
Figure 28. First and Second Grayscale Data Latch Configuration
Table 5. Grayscale Data Latch Bit Description
GS DATA LATCH BIT
NUMBER
BIT NAME
CONTROLLED
CHANNEL
28
GS DATA LATCH BIT
NUMBER
BIT NAME
CONTROLLED
CHANNEL
Bits 11 to 0 for OUT8
11-0
GSOUT0
Bits 11 to 0 for OUT0
107-96
GSOUT8
23-12
GSOUT1
Bits 11 to 0 for OUT1
119-108
GSOUT9
Bits 11 to 0 for OUT9
35-24
GSOUT2
Bits 11 to 0 for OUT2
131-120
GSOUT10
Bits 11 to 0 for OUT10
47-36
GSOUT3
Bits 11 to 0 for OUT3
143-132
GSOUT11
Bits 11 to 0 for OUT11
59-48
GSOUT4
Bits 11 to 0 for OUT4
155-144
GSOUT12
Bits 11 to 0 for OUT12
71-60
GSOUT5
Bits 11 to 0 for OUT5
167-156
GSOUT13
Bits 11 to 0 for OUT13
83-72
GSOUT6
Bits 11 to 0 for OUT6
179-168
GSOUT14
Bits 11 to 0 for OUT14
95-84
GSOUT7
Bits 11 to 0 for OUT7
191-180
GSOUT15
Bits 11 to 0 for OUT15
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First and Second Control Data Latch
The first and second control data latches are 137 bits and 119 bits long, respectively. The first latch contains
global brightness control (BC) data and function control (FC) data; the second latch contains global BC data. The
DC for each constant-current output and the BC for all constant-current outputs are controlled by the second
control data latch. The control data in the first latch are set by the least significant 137 bits from the common shift
register at the LAT rising edge when the common shift register MSB is '1'. The 119 bits of BC data from the first
control data latch are copied to the second latch when the 4096th GSCLK occurs or when the BLANK bit in the
first control data latch is set to '1'.
When the device is powered up, the data in the first latch (except the BLANK and PSMODE bits of the FC bits)
and second latch are random. Therefore, BC and FC data must be written to the first and second control data
latches before turning on the constant-current outputs. The default value of the BLANK bit is '1'. The first and
second control data latch configurations are shown in Figure 29.
From Common Shift Register
Lower 137 Bits
First Control Data Latch (137 Bits)
MSB
136-119 118-112 111-105 104-98
FC
Bits
17-0
BC
Bits[6:0]
for OUTn
FC,
18 Bits
BC,
7 Bits
(1)
RSV
Bits
RSV
Bits
97-91
90-84
27-21
20-14
13-7
LSB
6-0
RSV
Bits
RSV
Bits
RSV
Bits
RSV
Bits
RSV
Bits
RSV
Bits
This latch pulse comes
from the LAT pin when
the MSB of the Common
Shift Register is ‘1’.
112 Reserved Bits (Write ‘1’ to All Bits)
119 Bits
Second Control Data Latch (119 Bits)
MSB
118-112 111-105 104-98
BC
Bits[6:0]
for OUTn
RSV
Bits
RSV
Bits
97-91
90-84
27-21
20-14
13-7
LSB
6-0
RSV
Bits
RSV
Bits
RSV
Bits
RSV
Bits
RSV
Bits
RSV
Bits
BC,
7 Bits
18 Bits
7 Bits
To
To
Global Brightness
Function
Control Circuit
Control Circuit
The 4096th GSCLK is used
to latch the data when the
Auto Display Repeat is
enabled or when the BLANK bit
is set to ‘1’.
112 Reserved Bits (Write '1' to All Bits)
112 Bits
No
Applied
Bits
(1) RSV = reserved.
Figure 29. First and Second Control Data (BC and FC) Latch Configuration
Global Brightness Control (BC) Data
Global BC data are seven bits long. The global brightness for all outputs is controlled by the second control data
latch. The data are used to adjust the constant-current values for the 16 constant-current outputs. As explained
in the Global Brightness Control (BC) Function section, the BC values are used to adjust the output current from
25% to 100% of the maximum value. The global BC data bit assignment in the first and second latches is shown
in Table 6. Table 2 summarizes the BC data value versus set current value.
Table 6. Global Brightness Control Data Bit Assignment in the Control Data Latch
BIT NUMBER
BIT NAME
CONTROLLED CHANNEL
118-112
BC
BC[6:0] bits for all channels (OUT0-OUT15)
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Function Control (FC) Data Latch
The FC data latch is 13 bits long. This latch enables the constant-current outputs, enables the auto display
repeat and display timing reset functions, and sets the PWM control mode and the LOD, LSD, and OLD data
latch timing. Each function is selected by the first control data latch. When the device is powered on, the FC data
in the first control data latch are random (except the BLANK and PSMODE bits) in order to disable all constantcurrent outputs. The FC data bit assignment in the first control data latch is shown in Table 7.
Table 7. Function Control Data Latch Bit Description
BIT
NUMBER
119
120
121
122
123, 124
125, 126
127, 128
30
BIT
NAME
BLANK
DSPRPT
TMGRST
ESPWM
LODVLT
LSDVLT
LATTMG
DEFAULT
VALUE
(Binary)
DESCRIPTION
1
Constant-current output blank bit
0 = On, 1 = Off
When this bit is '0', all constant-current outputs (OUT0-OUT15) are controlled
by the GS PWM timing controller.
When this bit is '1', all constant-current outputs are forced off, the GS counter is
reset to '0', and the GS PWM timing controller is initialized. When the device is
powered on, this bit is set to '1'.
—
Auto display repeat mode enable bit
0 = Disabled, 1 = Enabled
When this bit is '0', the auto display repeat function is disabled. Each constantcurrent output is turned on and off for one display period after the BLANK bit is
set to '0'.
When this bit is '1', each output is repeated every 4096 GS clocks. When the
device is powered on, this bit is random.
—
Display timing reset mode enable bit
0 = Disabled, 1 = Enabled
When this bit is '0', the GS counter is not reset and the outputs are not forced
off even with a LAT rising edge.
When this bit is '1', the GS counter is reset to '0' and all outputs are forced off
at the LAT rising edge for a GS data write. This function is identical to the
BLANK bit. Therefore, a BLANK bit data change is not required to control the
outputs from a controller. PWM control resumes from the next GSCLK rising
edge. When the device is powered on, this bit is random.
—
ES-PWM mode enable bit
0 = Disabled, 1 = Enabled
When this bit is '0', the conventional PWM control mode is selected.
When this bit is '1', ES-PWM control mode is selected. If the TLC5949 is used
for multiplexing a drive, the conventional PWM mode should be selected to
prevent excess on/off switching. When the device is powered on, this bit is
random.
—
LOD detection voltage selection bits
LED open detection (LOD) detects a fault caused by an open LED by
comparing the OUTn voltage to the LOD detection threshold voltage. The
threshold voltage is selected with these bits. Refer to Table 8 for the detect
voltage truth table. When the device is powered on, this bit is random.
—
LSD detection voltage selection bits
LED short detection (LSD) detects a fault caused by a shorted LED by
comparing the OUTn voltage to the LSD detection threshold voltage. The
threshold voltage is selected by these bits. Refer to Table 9 for the detect
voltage truth table. When the device is powered on, this bit is random.
—
LOD and LSD data reading timing selection bits
The LOD and LSD data reading time is selected by these bits.
When DSPRPT is '1' and IDMRPT is '0', LOD and LSD data are loaded to the
LOD and LSD data latch one time only after new GS data are written into the
second GS data latch. Refer to Table 10 for the data load timing truth table.
When the device is powered on, this bit is random.
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Table 7. Function Control Data Latch Bit Description (continued)
BIT
NUMBER
129
130
131, 132
BIT
NAME
IDMENA
IDMRPT
IDMCUR
DEFAULT
VALUE
(Binary)
DESCRIPTION
—
Invisible detection mode (IDM) enable bit
0 = Disabled, 1 = Enabled
When this bit is '0', IDM is disabled. Therefore, LOD and LSD check LED status
only at power-up.
When this bit is '1', LOD and LSD check LED status with very small current
sinking at OUTn in a specific display segment. LOD and LSD can be checked
even if OUTn is off. The current value is set by the IDMCUR bits (bits 132, 131)
and the time is set by the LATTMG bits (bits 128, 127) in the function control
data latch. Furthermore, the IDM operation is repeated every display period
with auto display mode enabled when the IDMRPT bit (bit 130) is set to '1'.
When the device is powered on, this bit is random.
—
Invisible detection mode (IDM) repeat bit
0 = Not repeated, 1 = Repeated
When this bit is '0', IDM is not repeated. Therefore, LOD and LSD check LED
status only one time after the BLANK bit is changed from '1' to '0'. Otherwise,
LAT is input for a GS write when TMGRST is '1' or the GS counter is reset at
power-up only one time at the time programmed by LATTMG. IDM is disabled
when IDMENA is set to '0' even if this bit is '1'.
When this bit is '1', IDM operation is repeated every display period with the auto
display mode enabled. LOD and LSD check LED status at OUTn every display
period even if OUTn is off. When the device is powered on, this bit is random.
—
Invisible detection mode (IDM) current select bits
The OUTn sink current for IDM can be selected with these bits. Refer to
Table 11 for the IDM sink current truth table. When the device is powered on,
these bits are random.
Output leak detection mode (OLD) enable bit
0 = Disabled, 1 = Enabled
When this bit is '0', OLD is not checked and all OLD bits in the status
information data (SID) are set to '0'. OLD data are loaded into the OLD data
latch at the 4095th GS clock. OLD data in SID may show the result of the
previous display period, depending on the LAT input timing.
When this bit is '1', OLD checks the LED status with a small current sourced
through OUTn in a display segment. OLD only checks OUTn with GS data set
to '0'. When OUTn current leakage is detected, the OLD bit that corresponds to
the leaking output is set to '1' in the SID. When IDMENA is '1', OLD operation is
disabled even if the OLDENA bit is set to '1' because OLD cannot obtain a
correct result when IDM is enabled. When the device is powered on, this bit is
random.
133
OLDENA
—
134-136
PSMODE
111
Power-save mode (PSM) selection bits
The power-save mode is selected with these bits. Refer to Table 12 and
Table 13 for the PSM truth tables. When the device is powered on, these bits
are all set to '1'.
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Table 8. LOD Threshold Voltage Truth Table
LODVLT
BIT 124
BIT 123
LED OPEN DETECTION (LOD) THRESHOLD VOLTAGE
0
0
VLOD0 (0.3 V, typ)
0
1
VLOD1 (0.6 V, typ)
1
0
VLOD2 (0.9 V, typ)
1
1
VLOD3 (1.2 V, typ)
Table 9. LSD Threshold Voltage Truth Table
LSDVLT
BIT 126
BIT 125
LED SHORT DETECTION (LSD) THRESHOLD VOLTAGE
0
0
VLSD0 (0.35 × VCC, typ)
0
1
VLSD1 (0.45 × VCC, typ)
1
0
VLSD2 (0.55 × VCC, typ)
1
1
VLSD3 (0.65 × VCC, typ)
Table 10. LOD and LSD Data Latch Time Truth Table
LATTMG
(1)
BIT 128
BIT 127
LOD and LSD DATA LATCH TIMING
0
0
17th GSCLK after BLANK bit is changed to '0' or GS counter is reset. (1)
0
1
33rd GSCLK after BLANK bit is changed to '0' or GS counter is reset. (1)
1
0
65th GSCLK after BLANK bit is changed to '0' or GS counter is reset. (1)
1
1
129th GSCLK after BLANK bit is changed to '0' or GS counter is reset. (1)
When DSPRPT is '1' and IDMRPT is '0', the resulting LOD and LSD data are loaded to the LOD and LSD data latch only one time after
new GS data are written into the second GS data latch.
Table 11. IDM Sink Current Truth Table
IDMCUR
32
BIT 132
BIT 131
INVISIBLE DETECTION MODE (IDM) SINK CURRENT
0
0
2 μA (typ)
0
1
10 μA (typ)
1
0
20 μA (typ)
1
1
1 mA (typ)
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Table 12. PSM Select Truth Table: Bits 135, 134
PSMODE
BIT 135
BIT 134
POWER-SAVE MODE (PSM) FUNCTION
0
0
Power-save mode is disabled in every condition
0
1
When all '0's are written into the second GS data latch, the device goes into
power-save mode. When an SCLK rising edge occurs, the device goes to normal
operation and starts to control the output current. However, some recovery time
(tD7) is required to resume normal operation after an SCLK rising edge.
1
0
When all '0's are written into the second GS data latch, the device goes into
power-save mode. When the data (except all '0's) are written into the second GS
data latch, the device goes to normal operation and starts to control the output
current. However, some recovery time (tD7) is required to resume normal operation
after the data changes.
1 (default)
1 (default)
Power-save mode is enabled in every condition. When the device is powered up,
this mode is selected.
Table 13. PSM Select Truth Table: Bit 136
PSMODE
BIT 136
0
1 (default)
POWER-SAVE MODE (PSM) FUNCTION
The GSCLK signal is used for GS timing control in the same manner as in normal mode even if the
device is in power-save mode.
When the device is in power-save mode, the GSCLK signal is forced low internally and GS timing
control logic is not operational in order to reduce power consumption. However, if the lower two bits of
PSMODE (bits 135, 134) are set to '0', the GSCLK signal is not forced low because the PSM is
disabled. When the device is powered up, this mode is selected.
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STATUS INFORMATION DATA (SID)
The status information data (SID) contain the status of the LED open detection (LOD), LED short detection
(LSD), output leakage detection (OLD), pre-thermal warning (PTW), thermal error flag (TEF), and IREF short flag
(ISF). When the LAT rising edge for a GS data write is input, the SID overwrite the common shift register data
after the data in the common shift register are copied to the GS latch. If the common shift register MSB is '1', the
SID data are not copied to the common shift register.
After being copied into the common shift register, new SID data cannot be copied until at least one new bit of
data is written into the common shift register. Otherwise, the LAT signal is ignored. To recheck SID without
changing the GS data, reprogram the common shift register with the same data currently programmed into the
GS latch. When LAT goes high, the GS data do not change, but the SID data are loaded into the common shift
register. LOD, LSD, OLD, PTW, TEF, and ISF are shifted out of SOUT with each SCLK rising edge. The SID
load configuration and SID read timing are shown in Figure 30 and Table 14, respectively.
Reserved
H[3:0]
LOD
Reserved
Data
G[3:0]
OUT[15:8]
LOD
Data
OUT[7:0]
Reserved
F[3:0]
LSD
Reserved
Data
E[3:0]
OUT[15:8]
LSD
Data
OUT[7:0]
Reserved
D[3:0]
OLD
Reserved
Data
C[3:0]
OUT[15:8]
OLD
Data
OUT[7:0]
Reserved
B[3:0]
TEF
PTW
ISF
Reserved
A[112:0]
SID are loaded to the
common shift register
at the LAT rising edge
when the common
shift register MSB is ‘0’.
MSB
SOUT
Common
Data Bit
192
LSB
Common
Data Bits
[191:188]
Common
Data Bits
[187:180]
Common
Data Bits
[179:176]
Common
Data Bits
[175:168]
Common
Data Bits
[167:164]
Common
Data Bits
[163:156]
Common
Data Bits
[155:152]
Common
Data Bits
[151:144]
Common
Data Bits
[143:140]
Common
Data Bits
[139:132]
Common
Data Bits
[131:128]
Common
Data Bits
[127:120]
Common
Data Bits
[119:116]
Common
Data Bits
[115:113]
Common
Data Bits
[112:0]
SIN
SCLK
Common Shift Register (193 Bits)
Figure 30. SID Load Configuration
Table 14. SID Load Description
COMMON SHIFT
REGISTER BIT NUMBER
Bits[112:0]
LOADED SID DESCRIPTION
Reserved data. These 113 bits of data are not set and can be '0' or '1'.
IREF short flag (ISF) data; 1-bit data.
Bit 113
0 = Normal operation (default)
1 = IREF terminal connected to GND with low resistance
Pre-thermal warning (PTW) data; 1-bit data.
Bit 114
0 = Normal operation (default)
1 = Higher temperature condition than the detected PTW temperature range
Thermal error flag (TEF) data; 1-bit data.
Bit 115
Bits[119:116]
0 = Normal operation (default)
1 = Higher temperature condition than the detected TEF temperature range
Reserved data. These four bits of data are not set and can be either '0' or '1'.
Output leakage detection (OLD) data bit for OUT0 to OUT7. The 8-bit data bit assignment of the output channel
is:
Bits[127:120]
Bit
Bit
…
Bit
Bit
120 = OUT0 OLD
121 = OUT1 OLD
126 = OUT6 OLD
127 = OUT7 OLD
0 = Normal operation (default)
1 = LED current leaks to GND when the output is off
Bits[131:128]
34
Reserved data. These four bits of data are not set and can be either '0' or '1'.
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Table 14. SID Load Description (continued)
COMMON SHIFT
REGISTER BIT NUMBER
LOADED SID DESCRIPTION
Output leakage detection (OLD) data bit for OUT8 to OUT15. The 8-bit data bit assignment of the output
channel is:
Bits[139:132]
Bit
Bit
…
Bit
Bit
132 = OUT8 OLD
133 = OUT9 OLD
138 = OUT14 OLD
139 = OUT15 OLD
0 = Normal operation (default)
1 = Output current leaks to GND when the output is off
Bits[143:140]
Reserved data. These four bits of data are not set and can be either '0' or '1'.
LED short detection (LSD) data bit for OUT0 to OUT7. The 8-bit data bit assignment of the output channel is:
Bits[151:144]
Bit
Bit
…
Bit
Bit
144 = OUT0 LSD
145 = OUT1 LSD
150 = OUT6 LSD
151 = OUT7 LSD
0 = Normal operation (default)
1 = LED is shorted
Bits[155:152]
Reserved data. These four bits of data are not set and can be either '0' or '1'.
LED short detection (LSD) data bit for OUT8 to OUT15. The 8-bit data bit assignment of the output channel is:
Bits[163:156]
Bit
Bit
…
Bit
Bit
156 = OUT8 LSD
157 = OUT9 LSD
162 = OUT14 LSD
163 = OUT15 LSD
0 = Normal operation (default)
1 = LED is shorted
Bits[167:164]
Reserved data. These four bits of data are not set and can be either '0' or '1'.
LED open detection (LOD) data bit for OUT0 to OUT7. The 8-bit data bit assignment of the output channel is:
Bits[175:168]
Bit
Bit
…
Bit
Bit
168 = OUT0 LOD
169 = OUT1 LOD
174 = OUT6 LOD
175 = OUT7 LOD
0 = Normal operation (default)
1 = LED is open or connected to GND with low resistance
Bits[179:176]
Reserved data. These four bits of data are not set and can be either '0' or '1'.
LED open detection (LOD) data bit for OUT8 to OUT15. The 8-bit data bit assignment of the output channel is:
Bits[187:180]
Bit
Bit
…
Bit
Bit
180 = OUT8 LOD
181 = OUT9 LOD
186 = OUT14 LOD
187 = OUT15 LOD
0 = Normal operation (default)
1 = LED is open or connected to GND with low resistance
Bits[191:188]
Bit 192
Reserved data. These four bits of data are not set and can be either '0' or '1'.
No data loaded
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LED OPEN DETECTION (LOD)
LOD detects a fault caused by an LED open circuit or a short from OUTn to ground with low resistance by
comparing the OUTn voltage to the LOD detection threshold voltage. If the OUTn voltage is lower than the
threshold voltage (set by the LODVLT bits in the first control data latch) when OUTn is on, that output LOD bit is
set to '1' to indicate an open LED. Otherwise, the LOD bit is set to '0'. LOD data are only valid for outputs that
are programmed to be on during the LOD data read selected by the LATTMG bits in the first control data latch.
LOD data are latched into the LOD data latch when LOD data are read, as selected by LATTMG. LOD data for
outputs programmed to be off at the LOD latch timing are always '0' when IDM is not enabled.
LED SHORT DETECTION (LSD)
LSD data detect a fault caused by a shorted LED by comparing the OUTn voltage to the LSD detection threshold
voltage level set by LSDVLT in the first control data latch. If the OUTn voltage is higher than the programmed
voltage when OUTn is on, the corresponding output LSD bit is set to '1' to indicate a shorted LED. Otherwise, the
LSD bit is set to '0'. LSD data are only valid for outputs that are programmed to be on when the LSD data are
read, as selected by the LATTMG bits in the first control data latch. LSD data are latched into the LSD data latch
when the LSD data are read, as selected by LATTMG. LSD data for outputs programmed to be off at the LSD
latch timing are always '0' when IDM is not enabled.
OUTPUT LEAKAGE DETECTION (OLD)
OLD detects a fault caused by a short with high resistance from OUTn to GND by comparing the OUTn voltage
to the LSD detection threshold voltage when the output is off. A small current is sourced from OUTn to detect
LED leakage. OLD operation can be disabled by the OLDENA bit. Also, OLD is disabled when the invisible
detection mode (IDM) is enabled (see the Invisible Detection Mode section). If the OUTn voltage is lower than
the programmed LSD threshold voltage, the corresponding output OLD bit is set to '1' to indicate a leaking LED.
Otherwise, the OLD bit is set to '0'. The OLD result is valid for disabled outputs only. The OLD data are latched
into the OLD data latch at the end of the display period or when BLANK is changed to '1'. Also, the OLD data are
latched when the GS data are written if the display timing reset is enabled. OLD data always read '0' when the
output GS is not '0', or when OLD is disabled.
INVISIBLE DETECTION MODE (IDM)
IDM can detect LOD and LSD without dependency upon GS data. When the IDM bit in the function control data
latch is set, OUTn starts sinking the current set by the IDMCUR bits in the function control latch at the first
GSCLK; the IDM sink current is turned off at the GSCLK programmed by LATTMG. When the IDM current is
turned off, LOD and LSD data are latched into the LOD and LSD data latch. During the IDM timing, the original
PWM control continues. When the IDM bit in the control data latch is set to '0', the OUTn on/off timing is only
controlled by GS data.
LOD and LSD data are not valid for approximately 1 µs after the constant-current output turns on. Therefore, GS
data must be set to turn on the output for at least 1 µs. Furthermore, the LOD and LSD latch timing bits
(LATTMG) should be set as shown in Equation 4:
The number of GSCLKs required to obtain a valid LOD and LSD = 1 µs / tGSCLK
where:
tGSCLK = one GSCLK period
(4)
If the GSCLK frequency is 33 MHz, the outputs must be on for 33 GSCLK periods or more. Therefore, the
LATTMG bits can only be set to '01', '10', or '11'. If the GSCLK frequency is 2 MHz, the outputs must be on for
two or more GSCLK periods. In this case, the LATTMG bits can be set to any pattern.
36
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When LOD and LSD data must be read with invisible brightness, the LATTMG bits should be set to the minimum
data larger than the calculated number of GSCLK periods defined by Equation 4. IDM does not work in powersave mode. Figure 31 shows the LOD, LSD, OLD, and IDM circuit and Table 15 shows a truth table for LOD,
LSD, OLD, and IDM. Refer to Figure 32 for the PWM operation timing.
VCC
VLED
OLD
Control
2 mA (typ)
Current Flow
for OLD
LSD and
OLD Data
Current
Flow
for PWM
OUTn
VLSD
Current
Flow
for IDM
PWM
Control
LOD Data
VLOD
IDM
Control
GND
Figure 31. LOD, LSD, and OLD Circuit
Table 15. LOD, LSD, OLD, ISF, PTW, and TEF Truth Table
CONDITION
SID DATA
0
1
LOD
LED is not opened
(VOUTn > VLOD)
LED is open or
shorted to GND
(VOUTn ≤ VLOD)
LSD
OLD
ISF
PTW
TEF
LED is not shorted
(VOUTn ≤ VLSD)
OUTn does not leak to
GND
(VOUTn > VLSD when
constant-current
output off and OUTn
source current on)
IREF terminal is not
shorted
Device temperature is
lower than pre-thermal
warning temperature
(temperature ≤ TPTW)
Device temperature is
lower than thermal
shutdown threshold
temperature
(temperature ≤ TTEF)
LED is shorted
between anode and
cathode, or shorted to
higher voltage side
(VOUTn > VLSD)
Current leaks from
OUTn to internal
GND, or OUTn is
shorted to external
GND with high
impedance
(VOUTn ≤ VLSD when
constant-current
output off and OUTn
source current on)
IREF terminal is
shorted to GND with
low impedance and
OUTn are forced off
Device temperature is
higher than prethermal warning
temperature
(temperature > TPTW)
Device temperature is
higher than thermal
shutdown threshold
temperature and driver
is forced off
(temperature > TTEF)
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TMGRST Bit
in Control Data Latch
(Internal)
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'1'
Unknown
Internal BLANK is generated when the LAT
signal is input because display timing reset is enabled.
'1'
BLANK Bit
in Control Data Latch
(Internal)
'0'
4093
1
2 3
5
4
16 17 18 19 20
4095
4094
4096
1
2 3
4
5
Programmed
Output Current
OUTn Current
for PWM Control
(GSDATA = FFFh)
(1)
0 mA
0 mA
2 mA, 10 mA, 20 mA,
or 1 mA
OUTn Current for IDM
2 mA, 10 mA, 20 mA
(2)
0 mA
0 mA
(3)
LOD and LSD data latch updated with latest
data at the clock time selected by LATTMG bit.
LOD and LSD Data Latch
(Internal)
16-Bit LOD and LSD
Circuit Output Data
(Internal)
LOD, LSD
000h
Control data write
latch signal.
LOD
XXXh
LOD
XXXh
LOD and LSD Old Data
LOD
XXXh
LOD
XXXh
LOD
XXXh
LOD
000h
LOD
XXXh
GS data write latch signal.
LOD data are not stable immediately after OUTn turn on.
LAT
193-Bit Common Shift
Register Data
(Internal)
Control Data
GS Data
SID Loaded Into Common Shift Register
(1) Set the current with the external resistor and BC data.
(2) Select the output current with the IDMCUR bit in the control data latch.
(3) Select clock time with the LATTMG bit in the control data latch.
Figure 32. PWM Operation Timing
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POWER-SAVE MODE (PSM)
The power-save mode control bits are assigned in the function control data latch. The device dissipation current
becomes 10 µA (typ) in this mode. When the two lower bits in PSMODE are '01', '10', or '11', the power-save
mode is enabled. When the lower two bits are '01' or '10', and if all '0' data are written in the second GS data
latch, the TLC5949 goes into power-save mode. When an SCLK rising edge is generated with the lower two
PSMODE bits (bits 135, 134) set to '01', the device leaves PSM for normal operation. OUTn are turned on at the
first GSCLK of the next display period after the device has left PSM. Figure 33 shows the power-save mode
timing diagram.
SIN
Low
SCLK
1
2
3
191
192
1
193
2
3
4
5
6
¼
LAT
BLANK Bit
in Control Data Latch
(Internal)
'1'
PSMODE Bit
in Control Data Latch
(Internal)
X01b or X10b
First GS Data Latch
(Internal)
Previous On/Off Data
All Data Are '0'
First and second GS data latches are
changed simultaneously because the BLANK bit is '1'.
Second GS Data Latch
(Internal)
Previous On/Off Data
All Data Are '0'
OFF
OUT0, OUT7,
OUT8, OUT15
ON or OFF
OUT1, OUT6,
OUT9, OUT14
ON or OFF
OUT2, OUT5,
OUT10, OUT13
ON or OFF
OUT3, OUT4,
OUT11, OUT12
ON or OFF
ON
OFF
ON
OFF
ON
OFF
Power-Save Mode
ON
Normal Mode
Normal Mode
Power-Save Mode
Normal Mode
Greater Than 1 mA
ICC
(VCC Current)
Approximately 10 mA
Figure 33. Power-Save Mode Timing (Bits 135 and 134 = 01)
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CURRENT REFERENCE (IREF PIN) SHORT FLAG (ISF)
The ISF function indicates that the IREF terminal is shorted with low impedance to GND. The ISF bit in the SID is
set to '1' during this condition. Then all outputs, OUTn, are forced off. See Table 15 for the ISF truth table.
PRE-THERMAL WARNING (PTW)
The PTW function indicates that the device junction temperature is high. The PTW in the SID is set to '1' while
the device junction temperature exceeds the temperature threshold (TPTW = +138°C, typ); however, the outputs
are not forced off. When the PTW is set, the device temperature should be reduced by lowering the power
dissipated in it to avoid a forced shutdown by the thermal shutdown circuit. This reduction can be accomplished
by lowering the GS or BC data values. When the device junction temperature drops below the TPTW temperature,
the PTW bit in the SID is set to '0'. Figure 34 shows a timing diagram; see Table 15 for the PTW truth table.
LAT
SCLK
First GS Data Latch
(Internal)
Old Latched GS Data
New Latched GS Data
Common Shift Register
(Internal)
SID Data
Write Data for First GS Latch
BLANK Bit
in First Control Data Latch
(Internal)
'0'
(1)
1
2
4093 4095
4094 4096
3 4
1
2
3
GSCLK
TJ ³ TPTW
Device Junction
Temperature (TJ)
TJ ³ TTEF
TJ < TTEF - THYST
TJ ³ TPTW
TJ < TPTW
TJ ³ TTEF
TJ < TPTW
See Note (2)
'1'
PTW in SID
(Internal Data)
'1'
'0'
'0'
See Note (4)
See Note (3)
'1'
TEF in SID
(Internal Data)
'0'
See Note (5)
OFF
OFF
OFF
OUTn
'1'
'0'
ON
ON
See Note (6)
(1) This internal signal is reset when LAT is input for a GS write with the display timing reset enabled.
(2) The PTW bit in SID is reset to '0' at the LAT rising edge for a GS data write if the device junction temperature is below tPTW.
(3) The PTW bit is set to '1' when the device junction temperature is greater than tPTW.
(4) The TEF bit in SID is reset to '0' at the LAT rising edge for a GS data write if the device junction temperature is below tTEF.
(5) OUT0 to OUT15 are forced off when TJ exceeds tTEF. Furthermore, the TEF bit is set to '1' at the same time.
(6) OUT0 to OUT15 are turned on at the first GSCLK rising edge if the device junction temperature is below tTEF with BLANK set to '0'.
Figure 34. PTW, TEF, and TSD Timing
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THERMAL SHUTDOWN (TSD) AND THERMAL ERROR FLAG (TEF)
The TSD function turns off all constant-current outputs on the device when the junction temperature (TJ) exceeds
the threshold (TTEF = +165°C, typ) and sets TEF to '1'. All outputs are latched off when TEF is set to '1' and
remain off at least until the next GS cycle starts and the junction temperature drops below (TTEF – THYST). TEF
remains '1' until a LAT rising edge occurs and the temperature is reduced. TEF is set to '0' when the junction
temperature drops below (TTEF – THYST), but the output does not turn on until the first GSCLK in the next display
period occurs even if TEF is set to '0'. See Figure 34 for a timing diagram; refer to Table 15 for the TEF truth
table.
NOISE REDUCTION
Large surge currents may flow through the device and the board on which the device is mounted if all 16 outputs
turn on simultaneously at the start of each GS cycle. These large current surges could introduce detrimental
noise and electromagnetic interference (EMI) into other circuits. The TLC5949 independently turns the outputs on
with a delay for each group to provide a soft-start feature. The output current sinks are grouped into four groups
in each color group. The first output group that is turned on/off are OUT0, OUT7, OUT8, and OUT15; the second
output group is OUT1, OUT6, OUT9, and OUT14; the third output group is OUT2, OUT5, OUT10, and OUT13;
and the fourth output group is OUT3, OUT4, OUT11, and OUT12. Each output group is turned on and off
sequentially with a small delay between the groups. However, each output on/off is controlled by the GS clock.
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REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (December 2012) to Revision A
Page
•
Changed product status from mixed status to production data ............................................................................................ 1
•
Deleted footnote 1 and gray shading from DBQ rows in Package and Ordering Information table ..................................... 2
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TLC5949DBQR
ACTIVE
SSOP
DBQ
24
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TLC5949
TLC5949PWP
ACTIVE
HTSSOP
PWP
24
60
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TLC5949
TLC5949PWPR
ACTIVE
HTSSOP
PWP
24
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TLC5949
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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