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TLC6946, TLC6948
SLVSEB3A – JUNE 2018 – REVISED JANUARY 2019
TLC694x 16-Channel 32-, 48-Multiplexing 16-Bit ES-PWM Constant-Current LED Driver
1 Features
2 Applications
•
•
•
•
1
•
•
•
•
•
•
•
•
Power Supply Voltage Ranges
– VCC Voltage Range: 3 V to 5.5 V
– VLED Voltage Range: Up to VCC + 0.3 V
16 Constant-Current-Sink Channels
– 0.3 mA to 25 mA (3 V ≤ VCC ≤ 5.5 V)
– Channel Current Deviation: ±1% (typical)
– Device Current Deviation: ±1% (typical)
– Low Knee Voltage: 0.3 V (typical) at 10 mA
7-Bit (128 Steps) Global Brightness Control (BC)
16-Bit (65,536 Steps) Enhanced Spectrum PWM
Grayscale Control
Built-In Memory Supports 32 Multiplexing for
TLC6946 and 48 Multiplexing for TLC6948
LED Display Performance Enhancement
– Low-Grayscale Uniformity Improvement
– Low-Grayscale Coupling Issue Elimination
– Ghosting Removal and Caterpillar Elimination
High-Speed Serial-Data Interface
– Data-Shift Clock: 33 MHz (maximum)
– Grayscale Control Clock: 33 MHz (maximum)
– Supports Dual-Edge Grayscale Control
Diagnostics and Protection
– LED-Open Detection (LOD)
– IREF Resistor Short Protection (ISP)
– Thermal Shutdown (TSD)
Smart Power-Save Mode
Mono-Color, Multi-Color, Full-Color LED Displays
High-Refresh-Rate LED Video Displays
High-Density, Fine-Pitch LED Matrix Displays
3 Description
In high-density, fine-pitch LED panel applications, the
performance demand for multi-channel LED drivers is
increasing to achieve high multiplexing, high PWM
resolution, and high refresh rates. To meet strict
display quality requirements, the LED drivers must
have the ability to solve various issues in different
LED-matrix application scenarios.
The TLC694x device is a 16-channel, constantcurrent-sink LED driver. Each channel has an
individually adjustable 65,536 steps of PWM
grayscale control. The maximum constant-current
value of all 16 channels is set by a single external
resistor with 128 steps of global brightness control
from 0.3 mA to 25 mA.
Device Information(1)
PART NUMBER
TLC6946
TLC6948
PACKAGE
BODY SIZE (NOM)
SSOP (24)
8.65 mm × 3.90 mm
VQFN (24)
4.00 mm × 4.00 mm
SSOP (24)
8.65 mm × 3.90 mm
VQFN (24)
4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Schematic of TLC6948 With 48-Multiplexing
VLED
Line 0
VLED
Line n
VLED
Line 47
OUT0
DATA
SCLK
Controller
OUT15
SCLK
LAT
LAT
GSCLK
OUT0
SOUT
SIN
VCC
TLC6948
IC1
SCLK
VCC
LAT
GCLK
DATA BACK
OUT15
OUT0
SOUT
SIN
VCC
TLC6948
IC2
SCLK
VCC
LAT
GCLK
IREF
GND
RIREF
IREF
RIREF
OUT15
SOUT
SIN
VCC
TLC6948
IC3
VCC
GCLK
GND
IREF
RIREF
GND
3
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLC6946, TLC6948
SLVSEB3A – JUNE 2018 – REVISED JANUARY 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
8
1
1
1
2
3
4
6
Absolute Maximum Ratings ...................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 7
Electrical Characteristics........................................... 7
Switching Characteristics .......................................... 9
Typical Characteristics ............................................ 11
Parameter Measurement Information ................ 13
8.1 Pin Equivalent Input and Output Schematic
Diagrams.................................................................. 13
9
Detailed Description ............................................ 14
9.1 Overview ................................................................. 14
9.2 Functional Block Diagram ....................................... 15
9.3 Feature Description................................................. 16
9.4 Device Functional Modes........................................ 18
10 Application and Implementation........................ 19
10.1 Application Information.......................................... 19
10.2 Typical Application ............................................... 19
11 Power Supply Recommendations ..................... 22
12 Layout................................................................... 22
12.1 Layout Guidelines ................................................. 22
12.2 Layout Examples................................................... 23
13 Device and Documentation Support ................. 25
13.1
13.2
13.3
13.4
13.5
13.6
13.7
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
25
25
25
25
25
25
25
14 Mechanical, Packaging, and Orderable
Information ........................................................... 25
4 Revision History
Changes from Original (June 2018) to Revision A
•
2
Page
First release of production-data data sheet ........................................................................................................................... 1
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SLVSEB3A – JUNE 2018 – REVISED JANUARY 2019
5 Description (continued)
The TLC694x device integrates enhanced circuits to solve the various display issues in fine-pitch LED display
applications: the low-grayscale uniformity issue, coupling issue, ghosting issue, and caterpillar issue.
The TLC694x device features an LED-open detection function, and the error detection results can be read via a
serial data interface port. Thermal shutdown and IREF resistor short protection ensure a higher system reliability.
The TLC694x device also has an smart power-save mode that sets the total current consumption to 1 mA
(typical) when all outputs are off.
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SLVSEB3A – JUNE 2018 – REVISED JANUARY 2019
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6 Pin Configuration and Functions
DBQ Package
24-Pin SSOP
Top View
OUT2
7
18
OUT13
OUT3
8
17
OUT12
OUT4
9
16
OUT11
OUT5
10
15
OUT10
OUT6
11
14
OUT9
OUT7
12
13
OUT8
SOUT
OUT14
19
19
1
18
OUT15
OUT0
2
17
OUT14
OUT1
3
16
OUT13
OUT2
4
15
OUT12
OUT3
5
14
OUT11
OUT4
6
13
OUT10
Not to scale
Thermal
Pad
12
6
LAT
OUT9
OUT1
GCLK
OUT15
20
20
11
5
OUT8
OUT0
IREF
GCLK
21
21
10
4
GND
LAT
VCC
SOUT
22
22
9
3
OUT7
SCLK
SIN
IREF
23
23
8
2
OUT6
VCC
SIN
SCLK
24
7
1
OUT5
GND
24
RGE Package
24-Pin VQFN With Exposed Thermal Pad
Top View
Not to scale
Pin Functions
PIN
NAME
NO.
I/O
DBQ
RGE
GCLK
21
20
I
GND
1
10
—
DESCRIPTION
Grayscale (GS) pulse-width modulation (PWM) reference-clock-signal input pin. In the
default operating mode, each GCLK rising edge increments the GS counter for PWM
control. GCLK supports dual-edge operation.
Power-ground reference
IREF
23
21
I
Pin for setting the maximum constant-current value. Connecting an external resistor
between IREF and GND sets the maximum current for each constant-current output
channel. When this pin is connected directly to GND, all outputs are forced off. The
external resistor should be placed close to the device.
LAT
4
1
I
Data latch pin. The falling edge of LAT latches the data from the common shift register
into the GS data memory or the function control register.
4
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SLVSEB3A – JUNE 2018 – REVISED JANUARY 2019
Pin Functions (continued)
PIN
NAME
NO.
I/O
DESCRIPTION
DBQ
RGE
OUT0
5
2
O
OUT1
6
3
O
OUT2
7
4
O
OUT3
8
5
O
OUT4
9
6
O
OUT5
10
7
O
OUT6
11
8
O
OUT7
12
9
O
OUT8
13
11
O
OUT9
14
12
O
OUT10
15
13
O
OUT11
16
14
O
OUT12
17
15
O
OUT13
18
16
O
OUT14
19
17
O
OUT15
20
18
O
SCLK
3
24
I
Clock-signal input pin. Serial data present on SIN are shifted to the LSB of the internal
16-bit common shift register on the SCLK rising edge. All data in the shift register are
shifted toward the MSB of the internal 16-bit common shift register on each SCLK rising
edge.
SIN
2
23
I
Serial-data input pin of the internal 16-bit common shift register. When SIN is high, the
LSB of the internal 16-bit common shift register is set to 1 on the SCLK input rising
edge. When SIN is low, the LSB of the internal 16-bit common shift register is set to 0
on the SCLK input rising edge.
SOUT
22
19
O
Serial data output pin of the internal 16-bit common shift register. The MSB of the
internal 16-bit common shift register appears on SOUT.
VCC
24
22
I
Power supply pin
Thermal
pad
—
—
—
Constant-current output. Each output can be tied together with others to increase the
constant current. A different voltage can be applied to each output.
Internally connected to GND in the RGE package only. The thermal pad and the GND
pin must be connected together on the board.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
(2)
MIN
MAX
VCC
–0.3
6
V
GCLK, IREF, LAT, SCLK, SIN, SOUT
–0.3
VCC + 0.3
V
OUT0 to OUT15
–0.3
VCC + 0.3
OUT0 to OUT15
0
27
mA
Operating junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–55
150
°C
Voltage
Current
(1)
(2)
UNIT
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Theseare stress ratings
only, which do not imply functional operation of the device at these or anyother conditions beyond those indicated under Recommended
OperatingConditions. Exposure to absolute-maximum-rated conditions for extended periods mayaffect device reliability.
All voltage values are with respect to GND.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±7000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safemanufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safemanufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VCC
Supply voltage
Supply voltage
3
5.5
V
VOUTn
Voltage applied to OUT0 to OUT15
Voltage applied to OUT0 to OUT15
0
VCC
V
VIH
High-level input voltage
GCLK, LAT, SCLK, SIN
0.7 ×
VCC
VCC
V
VIL
Low-level input voltage
GCLK, LAT, SCLK, SIN
0
0.3 ×
VCC
V
IOH
High-level output current
SOUT
–2
mA
IOL
Low-level output current
SOUT
2
mA
IOLC,
Maximum constant-output sink current
OUT0 to OUT15
25
mA
fSCLK
Data-shift clock frequency
SCLK
33
MHz
fGCLK
Grayscale control clock frequency
GCLK
33
MHz
fGCLK,B
Grayscale control clock frequency for dual-edge
GCLK
operation
25
MHz
tw(H0)
Pulse width duration
SCLK
10
ns
tw(L0)
Pulse width duration
SCLK
10
ns
tw(H1)
Pulse width duration
GCLK
10
ns
tw(L1)
Pulse width duration
GCLK
10
ns
tw(H2)
Pulse width duration
GCLK (for dual-edge operation)
18
ns
tw(L2)
Pulse width duration
GCLK (for dual-edge operation)
18
ns
tsu(0)
Setup time
SIN to SCLK↑
2
ns
tsu(1)
Setup time
LAT ↑ to SCLK ↑
5
ns
tsu(2)
Setup time
LAT ↓ to SCLK ↑
5
ns
tsu(3)
Setup time
LAT ↓ to SCLK ↑ ,read data from SOUT
50
ns
tsu(4)
Setup time
LAT ↓ (WRTGS) to LAT ↓ (WRTGS)
1.5
µs
0.3
max
6
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Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
tsu(5)
Setup time
LAT ↓ (WRTGS) to LAT ↓ (VSYNC)
1.5
µs
tsu(6)
Setup time
LAT ↓ (VSYNC) to GCLK ↑
2.5
µs
tsu(7)
Setup time
LAT ↓ (VSYNC) to LAT ↓ (WRTGS)
2.5
µs
tsu(8)
Setup time
Last LAT (non-0 GS data latched) ↓ to the first
GCLK ↑ of next frame (wake up from powersave mode)
50
µs
tLSW
Line switching time
Last GCLK ↓ to the first GCLK ↑ of next line
1
µs
th(0)
Hold time
SCLK ↑ to SIN
2
ns
th(1)
Hold time
SCLK ↑ to LAT ↑
2
ns
th(2)
Hold time
SCLK ↑ to LAT ↓
10
ns
TA
Operating ambient temperature
Operating ambient temperature
–40
85
°C
TJ
Operating junction temperature
Operating junction temperature
–40
125
°C
7.4 Thermal Information
TLC6946
THERMAL METRIC (1)
DBQ (SSOP)
RGE (VQFN)
24 PINS
24 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
87.2
35.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
42.3
34.7
°C/W
RθJB
Junction-to-board thermal resistance
41.4
15.2
°C/W
ψJT
Junction-to-top characterization parameter
9.2
0.7
°C/W
ψJB
Junction-to-board characterization parameter
41
15.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
5
°C/W
(1)
For more information about traditional and new thermalmetrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
VCC = 3 V to 5.5 V and TA = –40°C to 85°C; typical values are at VCC = VLED = 3.5 V, TA = 25°C, over recommended operating
conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
IOH = –2 mA at SOUT
VOL
Low-level output voltage
IOL = 2 mA at SOUT
Reference voltage
BC = 00h, RIREF = 10.7 kΩ (IOUTn =
0.3-mA target)
VIREF
V(LOD)
LED open-detection threshold
TYP
MAX
UNIT
VCC
V
0.4
V
0.8
V
All OUTn = on, LODVTH = 00b
0.12
0.2
0.28
V
All OUTn = on, LODVTH = 01b
0.42
0.5
0.58
V
All OUTn = on, LODVTH = 10b
0.82
0.9
0.98
V
All OUTn = on, LODVTH = 11b
1.12
1.2
1.28
V
V(KNEE)
Knee voltage (OUT0 to OUT15)
All OUTn = on, BC = 36h, RIREF =
1.27 kΩ (IOUTn = 10-mA target)
ΔIOLC0
Constant-current error (channel-tochannel) (1)
All OUTn = on, BC = 00h,VOUTn = 1
V, RIREF = 10.7 kΩ (IOUTn = 0.3-mA
target), TA = 25°C, includes the
VIREF tolerance
(1)
MIN
VCC – 0.4
0.3
±1%
V
±3.5%
The deviation of each output from average of all channels constant current. The deviation is calculated by the formula.
' %
ª
«
IOUTn
« IOUT0 IOUT1 ... IOUT14 IOUT15
«
16
¬
º
»
1» u 100
»
¼
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Electrical Characteristics (continued)
VCC = 3 V to 5.5 V and TA = –40°C to 85°C; typical values are at VCC = VLED = 3.5 V, TA = 25°C, over recommended operating
conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
±1%
±2%
UNIT
ΔIOLC1
Constant-current error (device-todevice) (2)
All OUTn = on, BC = 00h,VOUTn = 1
V, RIREF = 10.7 kΩ (IOUTn = 0.3-mA
target), TA = 25°C, includes the
VIREF tolerance
ΔIOLC2
Constant-current error (channel-tochannel) (1)
All OUTn = on, BC = 2Ah,VOUTn = 1
V, RIREF = 10.7 kΩ (IOUTn = 1-mA
target), TA = 25°C, includes the
VIREF tolerance
±1%
±3%
ΔIOLC3
Constant-current error (device-todevice) (2)
All OUTn = on, BC = 2Ah,VOUTn = 1
V, RIREF = 10.7 kΩ (IOUTn = 1-mA
target), TA = 25°C, includes the
VIREF tolerance
±1%
±2.5%
ΔIOLC4
Constant-current error (channel-tochannel) (1)
All OUTn = on, BC = 36h,VOUTn = 1
V, RIREF = 1.27 kΩ (IOUTn = 10-mA
target), TA = 25°C, includes the
VIREF tolerance
±1%
±2.5%
ΔIOLC5
Constant-current error (device-todevice) (2)
All OUTn = on, BC = 36h,VOUTn = 1
V, RIREF = 1.27 kΩ (IOUTn = 10-mA
target), TA = 25°C, includes the
VIREF tolerance
±1%
±2.5%
ΔIOLC6
Constant-current error (channel-tochannel) (1)
All OUTn = on, BC = 7Eh,VOUTn = 1
V, RIREF = 1.02 kΩ (IOUTn = 25-mA
target), TA = 25°C, includes the
VIREF tolerance
±1%
±2%
ΔIOLC7
Constant-current error (device-todevice) (2)
All OUTn = on, BC = 7Eh,VOUTn = 1
V, RIREF = 1.02 kΩ (IOUTn = 25-mA
target), TA = 25°C, includes the
VIREF tolerance
±1%
±2%
ΔIOLC8
Line regulation (3)
All OUTn = on, VCC = 3 V to 5.5 V,
VOUTn = 1 V
±1
±2
%/V
All OUTn = on, VOUTn = 1 V to 3 V
±1
±2
%/V
(4)
ΔIOLC9
Load regulation
VIL(ISP)
IREF resistor short-protection enter
threshold
VIH(ISP)
IREF resistor short-protection
release threshold
T(TSD)
Thermal shutdown threshold (5)
170
T(HYS)
Thermal shutdown hysteresis (5)
15
II
SCLK or SIN Input current
(2)
(3)
8
0.325
VI = VCC or GND at SCLK or SIN
–1
V
0.4
V
°C
°C
1
µA
ª IOUT0 IOUT1 ... IOUT14 IOUT15
º
Ideal Output Current »
«
16
' % «
» u 100
Ideal Output Current
«
»
¬
¼
,Ideal current is calculated by the
§ V
· § 1 BC ·
Ideal Output mA Gain u ¨ IREF ¸ u ¨
¨ RIREF : ¸ © 8 144 ¸¹
©
¹
following equation
Line regulation is calculated by the following equation
ª IOUTn at VCC 5.5V
IOUTn at VCC
«
IOUTn
at
VCC
3V
¬«
3V º
100
»u
5.5V
3V
¼»
Load regulation is calculated by the following equation
' %V
(5)
0.195
The deviation of the average of constant current from the ideal constant current value.
' %V
(4)
0.15
ª IOUTn at VOUTn 3V
IOUTn at VOUTn 1V º
100
«
»u
IOUTn
at
VOUTn
1V
3V
1V
»¼
¬«
Specified by design
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Electrical Characteristics (continued)
VCC = 3 V to 5.5 V and TA = –40°C to 85°C; typical values are at VCC = VLED = 3.5 V, TA = 25°C, over recommended operating
conditions (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
ICC(0)
GCLK = LAT = SCLK = SIN = GND,
GSn = 0000h, BC = 00h, PCHG_EN
= 0, VOUTn = VCC, RIREF = open
3
4.5
6
mA
ICC(1)
GCLK = LAT = SCLK = SIN = GND,
GSn = 0000h, BC = 36h, PCHG_EN
= 0, VOUTn is floating, RIREF = 1.27
kΩ (IOUTn = 10-mA target)
4
6.5
8
mA
ICC(2)
GCLK = LAT = SCLK = SIN = GND,
GSn = 0000h, BC = 7Eh, PCHG_EN
= 0, VOUTn is floating, RIREF = 1.27
kΩ (IOUTn = 20-mA target)
4
7.5
9
mA
ICC(3)
LAT = SCLK = SIN = GND, GCLK =
33 MHz, GSn = FFFFh, BC = 36h,
PCHG_EN = 0, VOUTn = 1 V, RIREF =
1.27 kΩ (IOUTn = 10-mA target)
4.7
7
10
mA
ICC(4)
LAT = SCLK = SIN = GND, GCLK =
33 MHz, GSn = FFFFh, BC = 7Eh,
PCHG_EN = 0, VOUTn = 1 V, RIREF =
1.27 kΩ (IOUTn = 20-mA target)
4.7
7.7
10
mA
ICC(6)
In power-save mode, PCHG_EN =
0, RIREF = 1.60 kΩ
1
1.5
mA
Supply current (5)
RDW
Pulldown resistor
TEST CONDITIONS
LAT
250
480
750
GCLK
250
480
750
UNIT
kΩ
7.6 Switching Characteristics
VCC = 3 V to 5.5 V and TA = –40°C to85°C; Typical values are at VCC = 3.3 V, TA = 25°C,VLED = 5 V, over recommended
operating conditions (unless otherwisenoted)
PARAMETER
tr(0)
Rise time
tr(1)
(1)
tf(0)
Fall time
(1)
tpd(0)
Propagation delay (1)
tpd(1)
MIN
TYP
MAX
UNIT
2
ns
20
ns
2
ns
15
ns
SCLK↑ to SOUT↑↓, SEL_TD0 = 00b
5
ns
SCLK↑ to SOUT↑↓, SEL_TD0 = 01b
10
ns
SCLK↑ to SOUT↑↓, SEL_TD0 = 10b
20
ns
SCLK↓ to SOUT↑↓, SEL_TD0 = 11b
5
ns
OUTn, BC = 7Eh, VOUTn = 1 V,
RIREF = 1.02 kΩ (IOUTn = 25-mA
target), TA = 25°C, RL = 160 Ω
SOUT
tf(1)
(1)
TEST CONDITIONS
SOUT
OUTn, BC = 7Eh, VOUTn = 1 V,
RIREF = 1.02 kΩ (IOUTn = 25-mA
target), TA = 25°C, RL = 160 Ω
LAT↓ to SOUT, read LOD
information
25
50
ns
Specified by design
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tw(L)
SCLK(1)
50%
tw(H)
tsu
SIN
(1)
th
50%
tsu
tsu
tsu
th
(1)
LAT
50%
th
tpd
90%
SOUT
50%
10%
tf
tr
tw(H)
GCLK(1)
50%
n-1
OUTn
tw(L)
n(2)
n(2)
1
tLSW
tsu
1
2
90%
10%
tf
tr
(1) Pulse rise and fall times are 1 ns–3 ns
(2) The last GCLK of each display segment in the sub period
Figure 1. Timing Diagram
10
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7.7 Typical Characteristics
35
35
0.3 mA
1 mA
20 mA
25 mA
0.3 mA
1 mA
30
25
Output Current (mA)
Output Current (mA)
30
5 mA
10 mA
20
15
10
5
25
20
15
10
0
0
0.5
1
Output Voltage (V)
1.5
2
0
0.5
D002
VCC = 5 V
1
Output Voltage (V)
1.5
2
D001
VCC = 3.3 V
Figure 2. Channel Sink Current vs OUTn Voltage
Figure 3. Channel Sink Current vs OUTn Voltage
12
12
10
10
Output Current (mA)
Output Current (mA)
20 mA
25 mA
5
0
8
6
4
TA = -40 oC
TA = 25 oC
TA = 85 oC
2
8
6
4
TA = -40 oC
TA = 25 oC
TA = 85 oC
2
0
0
0
0.2
VCC = 5 V
0.4
0.6
Output Voltage (V)
0.8
0
1
0.2
D004
Temperature
changing
VCC = 3.3 V
Figure 4. Channel Sink Current vs OUTn Voltage
0.4
0.6
Output Voltage (V)
0.8
1
D003
Temperature
changing
Figure 5. Channel Sink Current vs OUTn Current
3
Constant-Current Accuracy (%)
3
Constant Current Accuracy (%)
5 mA
10 mA
2
1
0
-1
Vcc = 3.3 V Min
Vcc = 3.3 V Max
Vcc = 5 V Min
Vcc = 5 V Max
-2
-3
0
5
10
15
20
Output Current (mA)
25
30
2
1
0
-1
1 mA Min
1 mA Max
25 mA Min
25 mA Max
-2
-3
-40
-20
D005
VOUTn = 1 V
0
20
40
60
Ambient Temperature ( oC)
80
100
D006
VOUTn = 1 V
Figure 6. Channel to Channel Accuracy vs OUTn Current
Figure 7. Channel to Channel Accuracy vs Temperature
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Typical Characteristics (continued)
30
30
0.3 mA
1 mA
5 mA
10 mA
20 mA
25 mA
20
25
Output Current (mA)
Output Current (mA)
25
0.3 mA
1 mA
5 mA
10 mA
20 mA
25 mA
15
10
5
20
15
10
5
0
0
0
20
40
60
80
100
Brightness Control Data (Decimal)
VCC = 5 V
120
0
20
40
60
80
100
Brightness Control Data (Decimal)
D008
VOUTn = 1 V
VCC = 3.3 V
Figure 8. Channel Sink Current vs Brightness Control (BC)
120
D007
VOUTn = 1 V
Figure 9. Channel Sink Current vs Brightness Control (BC)
2
10
Supply Current (mA)
Supply Current (mA)
8
6
4
1.5
1
0.5
2
Vcc = 3.3 V
Vcc = 5 V
Vcc = 3.3 V
Vcc = 5 V
0
0
5
VOUTn = 1 V
10
15
Output current (mA)
GCLK = 33 MHz
20
25
0
-40
-20
0
20
40
60
Ambient Temperature (oC)
D009
GSn = FFFFh
VOUTn = 1 V
BC = 36h
80
100
D011
GCLK = 33 MHz
GSn = 0000h
RIREF = 1.27 kΩ (10-mA target)
Figure 10. Supply Current (ICC) vs Channel Sink Current
Figure 11. Supply Current (ICC) in Power-Save Mode vs
Temperature
12
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8 Parameter Measurement Information
8.1 Pin Equivalent Input and Output Schematic Diagrams
VCC
VCC
INPUT
INPUT
GND
GND
Figure 12. SIN, SCLK
Figure 13. LAT, GCLK
VCC
OUTn
INPUT
GND
GND
Figure 15. OUT0 Through OUT15
Figure 14. SOUT
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9 Detailed Description
9.1 Overview
The TLC694x device is a 16-channel constant-current-sink LED driver supporting 1- to 32-, 48-multiplexing. Each
channel has an individually adjustable 65,536-step pulse-width modulation (PWM) grayscale (GS) control. The
TLC6946 device implements 16-Kbit display memory and the TLC6948 device implements 24-Kbit display
memory to increase the visual refresh rate and to decrease the grayscale data-writing frequency.
The TLC694x device supports current from 0.3 mA to 25 mA for each channel, with typical 1% channel-tochannel current deviation and typical 1% device-to-device current deviation. The maximum current value of all 16
channels is set by an external IREF resistor and can be adjusted by the 128-step global brightness control (BC).
The device also implements low-grayscale enhancement technology to solve the coupling issue and improve the
display quality in low-grayscale conditions. These features make the TLC694x device a candidate for highdensity-multiplexing LED-matrix-display and LED-panel applications.
The TLC694x device integrates enhanced circuits to solve the various display issues in fine-pitch LED display
applications: the low-grayscale uniformity issue, coupling issue, ghosting issue, and caterpillar issue. The
TLC694x device features an LED-open detection function, and the error detection results can be read via a serial
data-interface port. Thermal shutdown and IREF-resistor short protection ensure a higher system reliability. The
TLC694x device also has a smart power-save mode that sets the total current consumption to 1 mA (typical)
when all outputs are off.
14
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9.2 Functional Block Diagram
OUT1
OUT0
OUT2
VCC
OUT14
OUT13
OUT15
LED Open Detection (LOD)
Caterpillar Elimination and Ghosting Removal
VCC
16
Reference Current
Control
IREF
16-CH Constant Current Sink Control
7-bit Global BC and Pre-Charge
LOD
Threshold
16
GCLK
Internal
Counter
VSYNC
ES-PWM Decoder
Timing Control
16
Line Counter
VSYNC
BANK A
16-bit × 16-CH
× 32-,48-line
BANK_SEL
BANK B
16-bit × 16-CH
× 32-,48-line
Address Decoder
Writing Control
16
WRTGS
VSYNC
WRTFC
LAT
Command
Decoder
SCLK
Function Control (FC) Registers
READFCx
or
READLOD
16
16
LSB
MSB
16-bit Common Shift Register
SIN
SOUT
16
GND
GND
Power Save
Control
To Analog
16-bit LOD Data
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9.3 Feature Description
9.3.1 Built-In 16Kb Display Memory (SRAM)
The TLC6946 device integrates 16K bits of SRAM to support 1- to 32-multiplexing and the TLC6948 device
integrates 24K bits of SRAM to support 1- to 48-multiplexing. SRAM is divided into two BANKs: BANK A and
BANK B. While BANK A is displaying, BANK B is ready to receive the data of the next frame. While BANK B is
displaying, BANK A is ready to receive the data of next frame.
9.3.2 GCLK Dual-Edge Operation
The TLC694x device uses the rising edge or both edges of GCLK. The selection is made by setting the
GCLK_EDGE bit in the function control register. By default, the TLC6946 device uses the GCLK rising edge, and
the maximum input GCLK frequency is 33 MHz. By setting GCLK_EDGE = 1, the TLC694x device operates at
both GCLK edges (rising and falling), and the maximum internal GCLK frequency is 50 MHz with external 25MHz
input.
9.3.3 Programmable Constant-Sink Channel Current
9.3.3.1 Global Brightness Control (BC)
The TLC694x device is able to adjust the output current of all constant-current outputs simultaneously. This
function is called global brightness control (BC). The global BC for all outputs is programmed with a 7-bit word,
thus all output currents can be adjusted in 128 steps from 12.5% to 100.69% for a given current-programming
resistor, RIREF (See Table 1). BC data can be set through the serial interface. When the BC data changes, the
output current also changes immediately. When the device is powered on, the BC data in the function control
register is set to 36h as the default value.
Table 1. Global BC Data vs Constant-Current Ratio and Set Current Value
BC DATA
GAIN
RATIO OF GAIN /
IOUT (mA) (IOLCmax= 25
GAIN_MAX (AT
mA, TYP)
MAX BC)
IOUT (mA) (IOLCmax=
2.4 mA, TYP)
BINARY
DECIMAL
HEX
000 0000
0
00
4
12.5%
3.13
0.3
000 0001
1
01
4.22
13.19%
3.3
0.32
000 0010
2
02
4.44
13.88%
3.47
0.33
...
...
...
...
...
...
...
011 0101
53
35
15.78
49.31%
12.33
1.18
011 0110
(Default)
54 (Default)
36 (Default)
16
50%
12.5
1.2
011 0111
55
37
16.22
50.69%
12.67
1.22
...
...
...
...
...
...
...
111 1101
125
7D
31.78
99.31%
24.83
2.38
111 1110
126
7E
32
100%
25
2.4
111 1111
127
7F
32.22
100.69%
25.17
2.42
9.3.3.2 Select RIREF for a Given BC
The maximum current per channel, IOLCmax, is determined by resistor RIREF, placed between the IREF and GND
pins. The voltage on IREF is typically 0.8 V. RIREF can be calculated by Equation 1.
R IREF (k:)
VIREF (V)
IOLCmax (mA)
u Gain
VIREF (V)
§ 1 BC ·
u 32 u ¨
¸
IOLCmax (mA)
© 8 144 ¹
where
•
•
•
16
VIREF is the internal reference voltage on IREF (0.8 V)
IOLCmax is the maximum current for each channel
Gain is the current gain at BC = 7E (See Table 1)
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RIREF must be between 1.02 kΩ and 10.7 kΩ in order to hold the channel sink current IOLC between 25 mA
(typical) and 0.3 mA (typical). Otherwise, the output may be unstable.
Table 2. Maximum Constant Current vs External Resistor RIREF
IOLCmax (mA)
RIREF (kΩ, typical)
25
1.02
20
1.28
15
1.71
10
2.56
5
5.12
2.4
10.7
9.3.4 Grayscale (GS) Function (PWM Control)
The TLC694x device can adjust the brightness of each output channel using a pulse-width-modulation (PWM)
control scheme. The architecture of 16 bits per channel results in 65536 brightness steps, from 0% up to 100%
brightness. The on-time (tOUT_ON) of each output (OUTn) can be calculated by Equation 2.
t OUT _ ON
t GCLK u GSn
where GSn is the grayscale of channel OUTn
(2)
The TLC694x device implements an enhanced spectrum (ES) PWM control. The ES-PWM control can be
selected with two different modes: 8-bit MSB + 8-bit LSB (8+8) mode, and 9-bit MSB + 7-bit LSB (9+7) mode.
See TLC6946 Technical Reference Manual for more details.
9.3.5 Serial Data Interface
The TLC6948 has a flexible serial interface that can be connected to microcontrollers or digital signal processors
in various ways. Only three pins are needed to input data into the device. More than two TLC6948s can be
connected in series by connecting an SOUT pin from one device to the SIN pin of the next device. The SOUT pin
can also be connected to the controller to read back data from the TLC6948 device.
9.3.6 LED-Open Detection (LOD)
The LED-open detection (LOD) function detects faults caused by an open circuit in any LED string or a short
from OUTn to ground with low impedance. It does this by comparing the OUTn voltage to the LOD-detection
threshold-voltage level set by LODVTH in the function control register. If the OUTn voltage is lower than the
programmed voltage, the corresponding output LOD bit is set to 1 to indicate an open LED. Otherwise, the
output of that LOD bit is 0. LOD data output by the detection circuit are valid only during the on period of that
OUTn output channel.
9.3.7 Caterpillar Removal
The TLC694x device implements an internal circuit that can eliminate the caterpillar issue caused by an open
LED. The caterpillar effect is a common issue for LED panels. The caterpillar removal function is enabled by
setting LODRM_EN to 1 (default value after device powered on) in the function control register. When this
function is enabled, the device automatically detects the open LED, and the corresponding channel does not turn
on until device reset.
9.3.8 Precharge FET
The TLC694x internal precharge FET can prevent ghosting of multiplexed LED modules. One cause of this
phenomenon is the charging current from parasitic capacitance on OUTn through the LED when the supply
voltage switches from one common line to the next common line. To prevent this unwanted charging current, the
TLC694x device uses an internal FET to pull up OUTn during the common-line switching period. As a result, no
charging current flows through LED and ghosting is eliminated.
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9.3.9 Thermal Shutdown
The thermal shutdown (TSD) function turns off all device constant-current outputs when the junction temperature
(TJ) exceeds 170°C (typical). It resumes normal operation when TJ falls below 155°C (typical).
9.3.10 IREF Resistor Short Protection (ISP)
The IREF resistor short protection (ISP) function prevents unwanted large currents from flowing though the
constant-current output when the IREF resistor is shorted accidently. The TLC694x device turns off all output
channels when the IREF pin voltage is lower than 0.19 V (typical). When the IREF pin voltage goes higher than
0.325 V (typical), the TLC694x device resumes normal operation.
9.4 Device Functional Modes
9.4.1 Normal Operating Mode
The TLC694x device is fully functional when VCC reaches 3 V and is below 5.5 V. After power on, all OUTn of the
TLC694x device are turned off. All the internal counters and function control registers are initialized. Write the
proper grayscale data and function control data to enable normal device operation.
9.4.2 Power-Save Mode (PSM)
The power-save mode (PSM) is enabled by setting PSM_EN to 1 in the function control register.
When powered on, the default value of this bit is 0. When this function is enabled, if all the GS data received for
the next frame are 0, then device enters power-save mode during the display of the next frame. When the device
is in power-save mode, it resumes normal mode when it detects non-zero GS data input. In power-save mode,
part of analog circuits are not operational; the device total current consumption, ICC, is 1 mA(typical).
18
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The TLC6948 device is a 16-channel constant-current sink LED driver supporting 1- to 48-multiplexing. Each
channel has an individually adjustable 65,536-step pulse-width-modulation (PWM) grayscale (GS) control. The
TLC6948 device implements 24 Kbits of display memory to increase the visual refresh rate and to decrease the
grayscale data writing frequency. This integrated memory makes TLC6948 a potential for high-density, fine-pitch
LED matrix applications.
10.2 Typical Application
The TLC6948 is typically connected in series to drive the LED matrix with only a few controller ports. Figure 16
shows a typical application diagram with TLC6948 devices connected in cascade for an LED matrix.
VLED
Line 0
VLED
Line n
VLED
Line 47
OUT0
DATA
SCLK
Controller
OUT15
SCLK
LAT
GSCLK
IC1
OUT15
SCLK
VCC
LAT
OUT0
SOUT
SIN
VCC
TLC6948
LAT
DATA BACK
OUT0
SOUT
SIN
VCC
TLC6948
SCLK
VCC
IC2
LAT
GCLK
GCLK
GCLK
IREF
IREF
IREF
GND
RIREF
RIREF
OUT15
SOUT
SIN
GND
RIREF
VCC
TLC6948
IC3
VCC
GND
3
Figure 16. Cascading Three TLC6948 Devices
10.2.1 Design Requirements
For this design example, use the following as the input parameters.
Table 3. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
VCC and VLED voltage
3 V to 5.5 V
SIN, SCLK, LAT, and GCLK voltage range
Low level = GND, high level = VCC
The maximum LED forward voltage, V(F)
Red LED 2V, green and blue LED 3V
The maximum current for each color LED,
IOLCmax
Red LED 10mA, green LED 6mA, blue LED 4mA.
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10.2.2
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Detailed Design Procedures
10.2.2.1 Power Supply Voltage
The LED power supply voltage VLED must be higher than V(F) + V(KNEE). The device power supply voltage, VCC
should be equal or higher than VLED. One example value is VLED = VCC= 3.8 V. See TLC6946 Technical
Reference Manual for more details.
10.2.2.2 Channel Current and Brightness Control
See Global Brightness Control (BC) and Select RIREF for a Given BC. Select the reference-current-setting resistor
RIREF to set the maximum channel current for each color LED. Select the BC data for the best white balance of
the red, green, and blue LED lamp. See TLC6946 Technical Reference Manual for more details.
10.2.2.3 SCLK and GCLK Frequency
SCLK is the serial data shift-in clock signal; and GCLK is the PWM-control reference-clock signal. Equation 3
shows the minimum frequency requirement for GCLK and SCLK. See TLC6946 Technical Reference Manual for
more details.
f GCLK m u n u f VR
f SCLK N u n u 256 u fFPS
where
•
•
•
•
•
•
•
20
fGCLK is the minimum GCLK frequency for single-edge operating mode
fSCLK is the minimum SCLK frequency
m is the GCLK number of each sub-period, determined by the PWM mode selected
fVR is the visual refresh rate of the entire cascading series
N is the number of cascaded TLC6948 devices
n is the number of scan lines
fFPS is the frame rate
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10.2.3 Application Curves
Figure 17. OUTn Waveform for ES-PWM Mode (GSn =
0001h)
Figure 18. OUTn Waveform for ES-PWM Mode Zooming in
One Sub-period (GSn = 0001h)
Figure 19. OUTn Waveform for ES-PWM Mode (GSn =
FFFFh)
Figure 20. OUTn Waveform for ES-PWM Mode Zooming in
One Sub-period (GSn = FFFFh)
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11 Power Supply Recommendations
Decouple the VCC power supply voltage by placing a 0.1-μF ceramic capacitor close to the VCC pin and GND
plane. Depending on panel size, several equally distributed electrolytic capacitors must be placed on the board
for a well-regulated LED supply voltage VLED. VLED voltage ripple must be less than 5% of its nominal value.
12 Layout
12.1 Layout Guidelines
Place the decoupling capacitor near the VCC pin and GND plane.
Place the current-programming resistor, RIREF, close to the IREF pin and the GND pin.
Make the GND trace as wide as possible for large GND currents.
Routing between the LED cathode and the device OUTn pin must be as short and straight as possible to reduce
wire inductance.
The thermal pad (QFN package) must be connected to the GND plane. Because the thermal pad is used as a
power ground pin internally, there is a large current flow through this pad when all channels turn on.
Furthermore, connect the thermal pad to a heat sink layer by thermal vias to reduce device temperature. One
suggested thermal via pattern is shown in Layout Examples. For more information about suggested thermal via
pattern and via size, see PowerPAD Thermally Enhanced Package.
MOSFETs must be placed in the in the middle of the board, which should be laid out as symmetrically as
possible.
22
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12.2 Layout Examples
GND
GND
RIREF
VCC
1
GND
VCC 24
To controller: SIN
2
SIN
IREF 23
To controller: SCLK
3 SCLK
SOUT 22
To controller: SOUT
To controller: LAT
4
GCLK 21
To controller: GCLK
LAT
5 OUT0
OUT15 20
6 OUT1
OUT14 19
7 OUT2
OUT13 18
8 OUT3
OUT12 17
9 OUT4
OUT11 16
10 OUT5
OUT10 15
11 OUT6
OUT9 14
12 OUT7
OUT8 13
VLED
VLED
Copyright © 2017, Texas Instruments Incorporated
Figure 21. SSOP-24 Package Layout Example
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Layout Examples (continued)
VCC
To controller: SIN
GND
RIREF
To controller: SCLK
To controller: GCLK
To controller: LAT
1
19
20
21
22
GND
18
OUT15
3
16
OUT13
OUT2
4
15
OUT12
OUT3
5
14
OUT11
OUT4
6
13
OUT10
OUT5
VLED
12
OUT1
11
OUT14
10
17
9
2
8
OUT0
7
VLED
23
24
To controller: SOUT
OUT6
OUT9
OUT7
OUT8
GND
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Figure 22. VQFN-24 Package Layout Example
24
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13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
For related documentation see the following:
• TLC694x 16-Channel LED Driver Technical Reference Manual
• Semiconductor and IC Package Thermal Metrics
13.2 Related Links
Table 4 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to order now.
Table 4. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TLC6946
Click here
Click here
Click here
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13.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
13.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated device. This data is subject to change without notice and without
revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.
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Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: TLC6946 TLC6948
25
PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TLC6946DBQR
ACTIVE
SSOP
DBQ
24
2500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
TLC6946
TLC6946RGER
ACTIVE
VQFN
RGE
24
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TLC
6946
TLC6948DBQR
ACTIVE
SSOP
DBQ
24
2500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
TLC6948
TLC6948RGER
ACTIVE
VQFN
RGE
24
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TLC
6948
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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