Order
Now
Product
Folder
Support &
Community
Tools &
Software
Technical
Documents
TLV314-Q1, TLV2314-Q1, TLV4314-Q1
SBOS837A – NOVEMBER 2016 – REVISED JANUARY 2019
TLVx314-Q1 3-MHz, low-power, internal EMI filter, RRIO, operational amplifier
1 Features
3 Description
•
•
The TLVx314-Q1 family of single-, dual-, and quadchannel operational amplifiers represents a new
generation of low-power, general-purpose operational
amplifiers. Rail-to-rail input and output swings
(RRIO), low quiescent current (150 μA typically at 5
V) combine with a wide bandwidth of 3 MHz to make
this family very attractive for a variety of batterypowered applications that require a good balance
between cost and performance. The TLVx314-Q1
family achieves a low-input bias current of 1 pA,
making it an excellent choice for high impedance
sensors.
1
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to
+125°C Ambient Operating Temperature
Range
– Device HBM ESD Classification Level 3A
– Device CDM ESD Classification Level C6
Low Offset Voltage: 0.75 mV (Typical)
Low Input Bias Current: 1 pA (Typical)
Wide Supply Range: 1.8 V to 5.5 V
Rail-to-Rail Input and Output
Gain Bandwidth: 3 MHz
Low IQ: 250 µA/Ch (Maximum)
Low Noise: 16 nV/√Hz at 1 kHz
Internal RF and EMI Filter
Number of Channels:
– TLV314-Q1: 1
– TLV2314-Q1: 2
– TLV4314-Q1: 4
Extended Temperature Range:
–40°C to +125°C
2 Applications
•
•
•
•
•
Low-Side Sensing
Battery Management Systems
Passive Safety
Capacitive Sensing
Fuel Pumps
The robust design of the TLVx314-Q1 devices
provides ease-of-use to the circuit designer: unitygain stability, RRIO, capacitive loads of up to 300-pF,
an integrated RF and EMI rejection filter, no phase
reversal in overdrive conditions, and high electrostatic
discharge (ESD) protection (4-kV HBM).
These devices are optimized for low-voltage
operation as low as 1.8 V (±0.9 V) and up to 5.5 V
(±2.75 V), and are specified over the extended
industrial temperature range of –40°C to +125°C.
The TLV314-Q1 (single) is available in both 5-pin
SC70 and SOT-23 packages. The TLV2314-Q1
(dual) is offered in 8-pin SOIC and VSSOP packages.
The quad-channel TLV4314-Q1 is offered in a 14-pin
TSSOP package.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SOT-23 (5)
2.90 mm × 1.60 mm
SC70 (5)
2.00 mm × 1.25 mm
TLV2314-Q1
SOIC (8)
4.90 mm × 3.91 mm
TLV4314-Q1
TSSOP (14)
5.00 mm × 4.40 mm
TLV314-Q1
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
EMIRR vs Frequency
120
110
EMIRR IN+ (dB)
100
90
80
70
60
50
40
30
20
10
0
10M
100M
1G
Frequency (Hz)
10G
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV314-Q1, TLV2314-Q1, TLV4314-Q1
SBOS837A – NOVEMBER 2016 – REVISED JANUARY 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
7
1
1
1
2
3
6
Absolute Maximum Ratings ...................................... 6
ESD Ratings ............................................................ 6
Recommended Operating Conditions....................... 6
Thermal Information: TLV314-Q1 ............................. 7
Thermal Information: TLV2314-Q1 ........................... 7
Thermal Information: TLV4314-Q1 ........................... 7
Electrical Characteristics........................................... 8
Typical Characteristics .............................................. 9
Typical Characteristics ............................................ 10
Detailed Description ............................................ 13
7.1 Overview ................................................................. 13
7.2 Functional Block Diagram ....................................... 13
7.3 Feature Description................................................. 14
7.4 Device Functional Modes........................................ 15
8
Application and Implementation ........................ 16
8.1 Application Information............................................ 16
8.2 Typical Application ................................................. 16
8.3 System Examples ................................................... 17
9
Power Supply Recommendations...................... 19
9.1 Input and ESD Protection ....................................... 19
10 Layout................................................................... 20
10.1 Layout Guidelines ................................................. 20
10.2 Layout Example .................................................... 20
11 Device and Documentation Support ................. 21
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support......................................................
Documentation Support ........................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
21
21
21
21
21
21
21
12 Mechanical, Packaging, and Orderable
Information ........................................................... 22
4 Revision History
Changes from Original (November 2016) to Revision A
Page
•
Deleted TLV2314-Q1 Preview notation in Device Information .............................................................................................. 1
•
Deleted VSSOP (8) package from Device Information ......................................................................................................... 1
•
Deleted VSSOP package information and preview notation for 8-Pin SOIC in Pin Functions............................................... 4
•
Deleted DGK (VSSOP) thermal information .......................................................................................................................... 7
2
Submit Documentation Feedback
Copyright © 2016–2019, Texas Instruments Incorporated
Product Folder Links: TLV314-Q1 TLV2314-Q1 TLV4314-Q1
TLV314-Q1, TLV2314-Q1, TLV4314-Q1
www.ti.com
SBOS837A – NOVEMBER 2016 – REVISED JANUARY 2019
5 Pin Configuration and Functions
TLV314-Q1 DBV Package
5-Pin SOT-23
Top View
OUT
1
V-
2
+IN
3
5
4
TLV314-Q1 DCK Package
5-Pin SC70
Top View
V+
-IN
+IN
1
V-
2
-IN
3
5
V+
4
OUT
Pin Functions: TLV314-Q1
PIN
DBV
(SOT-23)
DCK (SC70)
–IN
4
3
+IN
3
OUT
1
V–
V+
NAME
I/O
DESCRIPTION
I
Inverting input
1
I
Noninverting input
4
O
Output
2
2
—
Negative (lowest) supply
5
5
—
Positive (highest) supply
Copyright © 2016–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TLV314-Q1 TLV2314-Q1 TLV4314-Q1
3
TLV314-Q1, TLV2314-Q1, TLV4314-Q1
SBOS837A – NOVEMBER 2016 – REVISED JANUARY 2019
www.ti.com
TLV2314-Q1 D Package
8-Pin SOIC
Top View
OUT A
1
8
V+
-IN A
2
7
OUT B
+IN A
3
6
-IN B
V-
4
5
+IN B
Pin Functions: TLV2314-Q1
PIN
I/O
DESCRIPTION
NAME
NO.
–IN A
2
I
Inverting input, channel A
+IN A
3
I
Noninverting input, channel A
–IN B
6
I
Inverting input, channel B
+IN B
5
I
Noninverting input, channel B
OUT A
1
O
Output, channel A
OUT B
7
O
Output, channel B
V–
4
—
Negative (lowest) supply
V+
8
—
Positive (highest) supply
4
Submit Documentation Feedback
Copyright © 2016–2019, Texas Instruments Incorporated
Product Folder Links: TLV314-Q1 TLV2314-Q1 TLV4314-Q1
TLV314-Q1, TLV2314-Q1, TLV4314-Q1
www.ti.com
SBOS837A – NOVEMBER 2016 – REVISED JANUARY 2019
TLV4314-Q1 PW Package
14-Pin TSSOP
Top View
14
OUT D
13
-IN D
3
12
+IN D
V+
4
11
V-
+IN B
5
10
+IN C
-IN B
6
9
-IN C
OUT B
7
8
OUT C
OUT A
1
-IN A
2
+IN A
A
B
D
C
Pin Functions: TLV4314-Q1
PIN
I/O
DESCRIPTION
NAME
NO.
–IN A
2
I
Inverting input, channel A
+IN A
3
I
Noninverting input, channel A
–IN B
6
I
Inverting input, channel B
+IN B
5
I
Noninverting input, channel B
–IN C
9
I
Inverting input, channel C
+IN C
10
I
Noninverting input, channel C
–IN D
13
I
Inverting input, channel D
+IN D
12
I
Noninverting input, channel D
OUT A
1
O
Output, channel A
OUT B
7
O
Output, channel B
OUT C
8
O
Output, channel C
OUT D
14
O
Output, channel D
V–
11
—
Negative (lowest) supply
V+
4
—
Positive (highest) supply
Copyright © 2016–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TLV314-Q1 TLV2314-Q1 TLV4314-Q1
5
TLV314-Q1, TLV2314-Q1, TLV4314-Q1
SBOS837A – NOVEMBER 2016 – REVISED JANUARY 2019
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted). (1)
MIN
MAX
UNIT
7
V
Supply voltage VS= (V+) – (V–)
Signal input pins
Voltage
(2)
(V–) – 0.5
(V+) + 0.5
V
–10
10
mA
Current (2)
Output short-circuit (3)
Continuous
Specified, TA
Temperature
–40
Junction, TJ
(2)
(3)
125
150
Storage, Tstg
(1)
mA
–65
°C
150
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
Input pins are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails must be
current limited to 10 mA or less.
Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
±4000
Charged-device model (CDM), per AEC Q100-011
±1000
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VS
Single-supply
Supply voltage
Dual-supply
Specified temperature range
6
Submit Documentation Feedback
NOM
MAX
1.8
5.5
±0.9
±2.75
–40
125
UNIT
V
°C
Copyright © 2016–2019, Texas Instruments Incorporated
Product Folder Links: TLV314-Q1 TLV2314-Q1 TLV4314-Q1
TLV314-Q1, TLV2314-Q1, TLV4314-Q1
www.ti.com
SBOS837A – NOVEMBER 2016 – REVISED JANUARY 2019
6.4 Thermal Information: TLV314-Q1
TLV314-Q1
THERMAL METRIC (1)
DBV (SOT-23)
DCK (SC70)
5 PINS
5 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
228.5
281.4
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
99.1
91.6
°C/W
RθJB
Junction-to-board thermal resistance
54.6
59.6
°C/W
ψJT
Junction-to-top characterization parameter
7.7
1.5
°C/W
ψJB
Junction-to-board characterization parameter
53.8
58.8
°C/W
(1)
For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics (SPRA953).
6.5 Thermal Information: TLV2314-Q1
TLV2314-Q1
THERMAL METRIC (1)
D (SOIC)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
138.4
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
89.5
°C/W
RθJB
Junction-to-board thermal resistance
78.6
°C/W
ψJT
Junction-to-top characterization parameter
29.9
°C/W
ψJB
Junction-to-board characterization parameter
78.1
°C/W
(1)
For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics (SPRA953).
6.6 Thermal Information: TLV4314-Q1
TLV4314-Q1
THERMAL METRIC (1)
PW (TSSOP)
UNIT
14 PINS
RθJA
Junction-to-ambient thermal resistance
121
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
49.4
°C/W
RθJB
Junction-to-board thermal resistance
62.8
°C/W
ψJT
Junction-to-top characterization parameter
5.9
°C/W
ψJB
Junction-to-board characterization parameter
62.2
°C/W
(1)
For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics (SPRA953).
Copyright © 2016–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TLV314-Q1 TLV2314-Q1 TLV4314-Q1
7
TLV314-Q1, TLV2314-Q1, TLV4314-Q1
SBOS837A – NOVEMBER 2016 – REVISED JANUARY 2019
www.ti.com
6.7 Electrical Characteristics
VS = 1.8 V to 5.5 V; at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
±0.75
±3
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
VCM = (VS+) – 1.3 V, TA = 25°C
dVOS/dT
VOS vs temperature
TA = –40°C to +125°C
PSRR
Power-supply rejection ratio
VCM = (VS+) – 1.3 V, TA = 25°C
±30
Channel separation, dc
At dc, TA = 25°C
100
2
mV
μV/°C
±135
µV/V
dB
INPUT VOLTAGE RANGE
VCM
CMRR
Common-mode voltage range
TA = 25°C
Common-mode rejection ratio
VS = 5.5 V, (VS–) – 0.2 V < VCM < (VS+) – 1.3 V,
TA = 25°C
(V–) – 0.2
72
VS = 5.5 V, VCM = –0.2 V to 5.7 V (2), TA = 25°C
(V+) + 0.2
96
V
dB
75
INPUT BIAS CURRENT
IB
Input bias current
TA = 25°C
±1.0
pA
IOS
Input offset current
TA = 25°C
±1.0
pA
Input voltage noise (peak-to-peak)
ƒ = 0.1 Hz to 10 Hz, TA = 25°C
NOISE
5
ƒ = 10 kHz, TA = 25°C
15
ƒ = 1 kHz, TA = 25°C
16
ƒ = 1 kHz, TA = 25°C
6
Differential
VS = 5 V, TA = 25°C
1
Common-mode
VS = 5 V, TA = 25°C
5
en
Input voltage noise density
in
Input current noise density
μVPP
nV/√Hz
fA/√Hz
INPUT CAPACITANCE
CIN
Input capacitance
pF
OPEN-LOOP GAIN
AOL
Open-loop voltage gain
Phase margin
VS = 1.8 V to 5.5 V, 0.2 V < VO < (V+) – 0.2 V,
RL = 10 kΩ, TA = 25°C
85
115
VS = 1.8 V to 5.5 V, 0.5 V < VO < (V+) – 0.5 V,
RL = 2 kΩ (2), TA = 25°C
85
100
dB
VS = 5 V, G = 1, RL = 10 kΩ, TA = 25°C
65
VS = 1.8 V, RL = 10 kΩ, CL = 10 pF, TA = 25°C
2.7
°
FREQUENCY RESPONSE
GBW
Gain-bandwidth product
SR
Slew rate (3)
VS = 5 V, G = 1, TA = 25°C
tS
Settling time
To 0.1%, VS = 5 V, 2-V step , G = 1, TA = 25°C
3
μs
Overload recovery time
VS = 5 V, VIN × gain > VS, TA = 25°C
8
μs
Total harmonic distortion + noise (4)
VS = 5 V, VO = 1 VRMS, G = 1, f = 1 kHz,
RL = 10 kΩ, TA = 25°C
THD+N
VS = 5 V, RL = 10 kΩ, CL = 10 pF, TA = 25°C
MHz
3
1.5
V/μs
0.005%
OUTPUT
VS = 1.8 V to 5.5 V, RL = 10 kΩ, TA = 25°C
5
25
VS = 1.8 V to 5.5 V, RL = 2 kΩ, TA = 25°C
22
45
VO
Voltage output swing from supply rails
mV
ISC
Short-circuit current
VS = 5 V, TA = 25°C
±20
mA
RO
Open-loop output impedance
VS = 5.5 V, ƒ = 100 Hz, TA = 25°C
570
Ω
POWER SUPPLY
VS
Specified voltage range
IQ
Quiescent current per amplifier, over
temperature
1.8
VS = 5 V, IO = 0 mA, TA = –40°C to +125°C
150
5.5
V
250
µA
TEMPERATURE
Tstg
(1)
(2)
(3)
(4)
8
Specified range
–40
125
°C
Storage range
–65
150
°C
Parameters with minimum or maximum specification limits are 100% production tested at 25ºC, unless otherwise noted. Overtemperature limits are based on characterization and statistical analysis.
Specified by design and characterization; not production tested.
Signifies the slower value of the positive or negative slew rate.
Third-order filter; bandwidth = 80 kHz at –3 dB.
Submit Documentation Feedback
Copyright © 2016–2019, Texas Instruments Incorporated
Product Folder Links: TLV314-Q1 TLV2314-Q1 TLV4314-Q1
TLV314-Q1, TLV2314-Q1, TLV4314-Q1
www.ti.com
SBOS837A – NOVEMBER 2016 – REVISED JANUARY 2019
6.8 Typical Characteristics
Table 1. Table of Graphs
TITLE
FIGURE
Open-Loop Gain and Phase vs Frequency
Figure 1
Quiescent Current vs Supply Voltage
Figure 2
Offset Voltage Production Distribution
Figure 3
Offset Voltage vs Common-Mode Voltage (Maximum Supply)
Figure 4
Input Voltage Noise Spectral Density vs Frequency (1.8 V, 5.5 V)
Figure 5
Input Bias and Offset Current vs Temperature
Figure 6
Output Voltage Swing vs Output Current (Overtemperature)
Figure 7
Small-Signal Overshoot vs Load Capacitance
Figure 8
Small-Signal Step Response, Noninverting (1.8 V)
Figure 9
Large-Signal Step Response, Noninverting (1.8 V)
Figure 10
No Phase Reversal
Figure 11
Channel Separation vs Frequency (Dual)
Figure 12
EMIRR
Figure 13
Copyright © 2016–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TLV314-Q1 TLV2314-Q1 TLV4314-Q1
9
TLV314-Q1, TLV2314-Q1, TLV4314-Q1
SBOS837A – NOVEMBER 2016 – REVISED JANUARY 2019
www.ti.com
6.9 Typical Characteristics
0
180
120
-20
170
100
-40
80
-60
60
-80
40
-100
20
-120
0
-140
90
-20
-160
10M
80
1
10
100
1k
10k
100k
1M
Quiescent Current (mA/Ch)
140
Phase (°)
Gain (dB)
at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
160
150
140
130
120
110
100
1.5
2
2.5
3
4
3.5
4.5
5
5.5
6
Supply Voltage (V)
Frequency (Hz)
RL = 10 kΩ and 10 pF, VS = ±2.5 V
Figure 1. Open-Loop Gain and Phase vs Frequency
Figure 2. Quiescent Current vs Supply
1000
12
600
Offset Voltage (mV)
Percent of Amplifiers (%)
800
10
8
6
4
400
200
0
-200
-400
-600
2
-800
0
-1.4
-1.3
-1.2
-1.1
-1
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
-1000
-2.75
-2
-1.25
-0.5
0
0.5
1.25
2
2.75
Common-Mode Voltage (V)
Offset Voltage (mV)
Typical units, VS = ±2.75 V
Figure 4. Offset Voltage vs Common-Mode Voltage
Figure 3. Offset Voltage Production Distribution
1000
100
Input Bias Current (pA)
Voltage Noise (nv/ÖHz)
900
VS = ±0.9 V
VS = ±2.75 V
800
700
IB
600
500
400
300
200
IOS
100
10
0
10
100
1k
10k
100k
-50
-25
0
Frequency (Hz)
Figure 5. Input Voltage Noise Spectral Density vs
Frequency
10
Submit Documentation Feedback
25
50
75
100
125
150
Temperature (°C)
Figure 6. Input Bias and Offset Current vs Temperature
Copyright © 2016–2019, Texas Instruments Incorporated
Product Folder Links: TLV314-Q1 TLV2314-Q1 TLV4314-Q1
TLV314-Q1, TLV2314-Q1, TLV4314-Q1
www.ti.com
SBOS837A – NOVEMBER 2016 – REVISED JANUARY 2019
Typical Characteristics (continued)
3
70
2
60
50
1
Overshoot (%)
Output Voltage Swing (V)
at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
25°C
0
125°C
-40°C
-1
40
30
20
-2
10
0
-3
5
0
10
15
20
25
30
35
0
40
200
400
600
800
1000
1200
Capacitive Load (pF)
Output Current (mA)
VS = ±2.75 V
VS = ±2.75 V
Figure 7. Output Voltage Swing vs Output Current
(Overtemperature)
Gain = 1 V/V
RL = 10 kΩ
Figure 8. Small-Signal Overshoot vs Load Capacitance
1
0.75
VIN
0.5
Voltage (V)
Voltage (25 mV/div)
VIN
0.25
0
-0.25
VOUT
-0.5
ZL = 10 pF + 10 kW
ZL = 100 pF + 10 kW
-0.75
-1
Time (1 ms/div)
VS = ±0.9 V
Time (1 ms/div)
RF = 10 kΩ
Gain = 1 V/V
RL = 10 kΩ
Gain = 1 V/V
Figure 9. Small-Signal Pulse Response (Noninverting)
Figure 10. Large-Signal Pulse Response (Noninverting)
4
-60
Channel Separation (dB)
VIN
VOUT
3
2
Voltage (1 V/div)
VS = ±0.9 V
1
0
-1
-2
-80
-100
-120
-3
-140
-4
0
250
500
750
1000
100
1k
10k
100k
1M
10M
Frequency (Hz)
Time (125 ms/div)
VS = ±2.75 V
Figure 11. No Phase Reversal
Copyright © 2016–2019, Texas Instruments Incorporated
Figure 12. Channel Separation vs Frequency (TLV2314)
Submit Documentation Feedback
Product Folder Links: TLV314-Q1 TLV2314-Q1 TLV4314-Q1
11
TLV314-Q1, TLV2314-Q1, TLV4314-Q1
SBOS837A – NOVEMBER 2016 – REVISED JANUARY 2019
www.ti.com
Typical Characteristics (continued)
at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
120
110
EMIRR IN+ (dB)
100
90
80
70
60
50
40
30
20
10
0
10M
PRF = –10 dBm
100M
1G
Frequency (Hz)
VS = ±2.5 V
10G
VCM = 0 V
Figure 13. Electromagnetic Interference Rejection Ratio
Referred to Noninverting Input (EMIRR IN+) vs Frequency
12
Submit Documentation Feedback
Copyright © 2016–2019, Texas Instruments Incorporated
Product Folder Links: TLV314-Q1 TLV2314-Q1 TLV4314-Q1
TLV314-Q1, TLV2314-Q1, TLV4314-Q1
www.ti.com
SBOS837A – NOVEMBER 2016 – REVISED JANUARY 2019
7 Detailed Description
7.1 Overview
The TLVx314-Q1 is a family of low-power, rail-to-rail input and output operational amplifiers specifically designed
for portable applications. These devices operate from 1.8 V to 5.5 V, are unity-gain stable, and suitable for a
wide range of general-purpose applications. The class AB output stage is capable of driving ≤ 10-kΩ loads
connected to any point between V+ and ground. The input common-mode voltage range includes both rails, and
allows the TLVx314-Q1 to be used in virtually any single-supply application. Rail-to-rail input and output swing
significantly increases dynamic range, especially in low-supply applications, and makes these devices suitable
for driving sampling analog-to-digital converters (ADCs).
The TLVx314-Q1 family features 3-MHz bandwidth and 1.5-V/μs slew rate with only 150-μA supply current per
channel, providing good ac performance at very-low-power consumption. DC applications are also well served
with a very low input noise voltage of 14 nV / √Hz at 1 kHz, low input bias current (0.2-pA), and a typical input
offset voltage of 0.5 mV.
7.2 Functional Block Diagram
V+
Reference
Current
VIN+
VINVBIAS1
Class AB
Control
Circuitry
VO
VBIAS2
V(Ground)
Copyright © 2016–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TLV314-Q1 TLV2314-Q1 TLV4314-Q1
13
TLV314-Q1, TLV2314-Q1, TLV4314-Q1
SBOS837A – NOVEMBER 2016 – REVISED JANUARY 2019
www.ti.com
7.3 Feature Description
7.3.1 Operating Voltage
The TLVx314-Q1 series of operational amplifiers is fully specified and ensured for operation from 1.8 V to 5.5 V.
In addition, many specifications apply from –40°C to +125°C. Parameters that vary significantly with operating
voltages or temperature are provided in the Typical Characteristics section. Bypass power-supply pins with
0.01-μF ceramic capacitors.
7.3.2 Rail-to-Rail Input
The input common-mode voltage range of the TLVx314-Q1 extends 200 mV beyond the supply rails. This
performance is achieved with a complementary input stage: an N-channel input differential pair in parallel with a
P-channel differential pair, as shown in the Functional Block Diagram. The N-channel pair is active for input
voltages close to the positive rail, typically (V+) – 1.3 V to 200 mV above the positive supply, and the P-channel
pair is on for inputs from 200 mV below the negative supply to approximately (V+) – 1.3 V. There is a small
transition region, typically (V+) – 1.4 V to (V+) – 1.2 V, in which both pairs are on. This 200-mV transition region
may vary up to 300 mV with process variation. Thus, the transition region (with both stages on) ranges from
(V+) – 1.7 V to (V+) – 1.5 V on the low end, up to (V+) – 1.1 V to (V+) – 0.9 V on the high end. Within this
transition region, PSRR, CMRR, offset voltage, offset drift, and THD can degrade compared to device operation
outside this region.
7.3.3 Rail-to-Rail Output
Designed as a micro-power, low-noise operational amplifier, the TLVx314-Q1 delivers a robust output drive
capability. A class AB output stage with common-source transistors achieves full rail-to-rail output swing
capability. For resistive loads up to 10-kΩ, the output typically swings to within 5 mV of either supply rail
regardless of the applied power-supply voltage . Different load conditions change the ability of the amplifier to
swing close to the rails, as shown in Figure 7.
7.3.4 Common-Mode Rejection Ratio (CMRR)
The CMRR for the TLVx314-Q1 is specified in several ways so the best match for a given application can be
used; see the Electrical Characteristics table. First, the CMRR of the device in the common-mode range below
the transition region [VCM < (V+) – 1.3 V] is given. This specification is the best indicator of the capability of the
device when the application requires using one of the differential input pairs. Second, the CMRR over the entire
common-mode range is specified at (VCM = –0.2 V to 5.7 V). This last value includes the variations measured
through the transition region, as shown in Figure 4.
14
Submit Documentation Feedback
Copyright © 2016–2019, Texas Instruments Incorporated
Product Folder Links: TLV314-Q1 TLV2314-Q1 TLV4314-Q1
TLV314-Q1, TLV2314-Q1, TLV4314-Q1
www.ti.com
SBOS837A – NOVEMBER 2016 – REVISED JANUARY 2019
Feature Description (continued)
7.3.5 Capacitive Load and Stability
The TLVx314-Q1 is designed for applications where driving a capacitive load is required. As with all operational
amplifiers, there may be specific instances where the TLVx314-Q1 can become unstable. The particular
operational amplifier circuit configuration, layout, gain, and output loading are some of the factors to consider
when establishing whether or not an amplifier is stable in operation. An operational amplifier in the unity-gain
(1 V/V) buffer configuration that drives a capacitive load exhibits a greater tendency to be unstable than an
amplifier operated at a higher noise gain. The capacitive load, in conjunction with the operational amplifier output
resistance, creates a pole within the feedback loop that degrades the phase margin. The degradation of the
phase margin increases when capacitive loading increases. When operating in the unity-gain configuration, the
TLVx314-Q1 remains stable with a pure capacitive load up to approximately 1 nF. The equivalent series
resistance (ESR) of some very large capacitors (CL capacitors with a value greater than 1 μF) is sufficient to alter
the phase characteristics in the feedback loop so the amplifier remains stable. Increasing the amplifier closedloop gain allows the amplifier to drive increasingly larger capacitance. This increased capability is evident when
measuring the overshoot response of the amplifier at higher voltage gains, as shown in Figure 8.
Inserting a small resistor (typically 10-Ω to 20-Ω) can increase the capacitive load drive of the amplifier in a unitygain configuration, as shown in Figure 14. This resistor significantly reduces the overshoot and ringing
associated with large capacitive loads. One possible problem with this technique, however, is that a voltage
divider is created with the added series resistor and any resistor connected in parallel with the capacitive load.
The voltage divider introduces a gain error at the output that reduces the output swing.
V+
RS
VOUT
Device
VIN
10 W to
20 W
RL
CL
Figure 14. Improving Capacitive Load Drive
7.3.6 EMI Susceptibility and Input Filtering
Operational amplifiers vary with regard to the susceptibility of the device to electromagnetic interference (EMI). If
conducted EMI enters the operational amplifier, the dc offset at the amplifier output can shift from the nominal
value when EMI is present. This shift is a result of signal rectification associated with the internal semiconductor
junctions. Although EMI can affect all operational amplifier pin functions, the signal input pins are likely to be the
most susceptible. The TLVx314-Q1 operational amplifier family incorporates an internal input low-pass filter that
reduces the amplifiers response to EMI. The filter provides common-mode and differential mode filtering. The
filter is designed for a cutoff frequency of approximately 80 MHz (–3 dB), with a roll-off of 20 dB per decade.
Texas Instruments has developed the ability to accurately measure and quantify the immunity of an operational
amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. The EMI rejection ratio (EMIRR)
metric allows operational amplifiers to be directly compared to the EMI immunity. Figure 13 illustrates the testing
results on the TLVx314-Q1. For more detailed information, see EMI Rejection Ratio of Operational Amplifiers
(SBOA128), available for download from www.ti.com.
7.4 Device Functional Modes
The TLVx314-Q1 family has a single functional mode. These devices are powered on as long as the powersupply voltage is between 1.8 V (±0.9 V) and 5.5 V (±2.75 V).
Copyright © 2016–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TLV314-Q1 TLV2314-Q1 TLV4314-Q1
15
TLV314-Q1, TLV2314-Q1, TLV4314-Q1
SBOS837A – NOVEMBER 2016 – REVISED JANUARY 2019
www.ti.com
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TLVx314-Q1 device is a low-power, rail-to-rail input and output operational amplifier specifically designed for
portable applications. These devices operate from 1.8 V to 5.5 V, are unity-gain stable, and suitable for a wide
range of general-purpose applications. The class AB output stage is capable of driving ≤ 10-kΩ loads connected
to any point between V+ and ground. The input common-mode voltage range includes both rails, and allows the
TLVx314-Q1 family to be used in virtually any single-supply application. Rail-to-rail input and output swing
significantly increases dynamic range, especially in low-supply applications, and makes the device suitable for
driving sampling analog-to-digital converters (ADCs).
The TLVx314-Q1 features a 3-MHz bandwidth and 1.5-V/μs slew rate with only 150-μA supply current per
channel, providing good ac performance at very-low-power consumption. DC applications are also well served
with a very-low input noise voltage of 14 nV/√Hz at 1 kHz, low-input bias current (0.2 pA), and a typical input
offset voltage of 0.5 mV.
8.2 Typical Application
A typical application for an operational amplifier is an inverting amplifier, as shown in Figure 15. An inverting
amplifier takes a positive voltage on the input and outputs a signal inverted to the input, making a negative
voltage of the same magnitude. In the same manner, the amplifier also makes negative input voltages positive on
the output. In addition, amplification can be added by selecting the input resistor (RI) and the feedback resistor
(RF).
RF
VSUP+
RI
VOUT
+
VIN
VSUP-
Figure 15. Application Schematic
8.2.1 Design Requirements
The supply voltage must be chosen to be larger than the input voltage range and the desired output range. The
limits of the input common-mode range (VCM) and the output voltage swing to the rails (VO) must also be
considered. For instance, this application scales a signal of ±0.5 V (1 V) to ±1.8 V (3.6 V). Setting the supply at
±2.5 V is sufficient to accommodate this application.
8.2.2 Detailed Design Procedure
Calculate the gain required by the inverting amplifier using Equation 1 and Equation 2:
VOUT
AV
VIN
AV
16
1.8
0.5
3.6
(1)
(2)
Submit Documentation Feedback
Copyright © 2016–2019, Texas Instruments Incorporated
Product Folder Links: TLV314-Q1 TLV2314-Q1 TLV4314-Q1
TLV314-Q1, TLV2314-Q1, TLV4314-Q1
www.ti.com
SBOS837A – NOVEMBER 2016 – REVISED JANUARY 2019
Typical Application (continued)
When the desired gain is determined, select a value for RI or RF. Selecting a value in the kilohm range is
desirable for general-purpose applications because the amplifier circuit uses currents in the milliamp range. This
milliamp current range ensures the device does not draw too much current. The trade-off is that very large
resistors (hundreds of kilohms) draw the smallest current, but generate the highest noise. Very small resistors
(hundreds of ohms) generate low noise but draw high current. This example uses 10 kΩ for RI, and RF uses 36
kΩ. These values are calculated using Equation 3:
RF
AV
RI
(3)
8.2.3 Application Curve
2
Input
Output
1.5
Voltage (V)
1
0.5
0
-0.5
-1
-1.5
-2
Time
Figure 16. Inverting Amplifier Input and Output
8.3 System Examples
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required.
The simplest way to establish this limited bandwidth is to place an RC filter at the noninverting terminal of the
amplifier, as Figure 17 shows.
RG
RF
R1
VOUT
VIN
C1
f-3 dB =
(
RF
VOUT
= 1+
RG
VIN
((
1
1 + sR1C1
1
2pR1C1
(
Figure 17. Single-Pole, Low-Pass Filter
If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this
task, as Figure 18 shows. For best results, the amplifier must have a bandwidth that is eight to ten times the filter
frequency bandwidth. Failure to follow this guideline can result in phase shift of the amplifier.
Copyright © 2016–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TLV314-Q1 TLV2314-Q1 TLV4314-Q1
17
TLV314-Q1, TLV2314-Q1, TLV4314-Q1
SBOS837A – NOVEMBER 2016 – REVISED JANUARY 2019
www.ti.com
System Examples (continued)
C1
R1
R1 = R2 = R
C1 = C2 = C
Q = Peaking factor
(Butterworth Q = 0.707)
R2
VIN
VOUT
C2
1
2pRC
f-3 dB =
RF
RF
RG =
RG
(
2-
1
Q
(
Figure 18. Two-Pole, Low-Pass, Sallen-Key Filter
18
Submit Documentation Feedback
Copyright © 2016–2019, Texas Instruments Incorporated
Product Folder Links: TLV314-Q1 TLV2314-Q1 TLV4314-Q1
TLV314-Q1, TLV2314-Q1, TLV4314-Q1
www.ti.com
SBOS837A – NOVEMBER 2016 – REVISED JANUARY 2019
9 Power Supply Recommendations
The TLVx314-Q1 family is specified for operation from 1.8 V to 5.5 V (±0.9 V to ±2.75 V); many specifications
apply from –40°C to +125°C. Typical Characteristics presents parameters that can exhibit significant variance
with regard to operating voltage or temperature.
CAUTION
Supply voltages larger than 7 V can permanently damage the device (see the Absolute
Maximum Ratings table).
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. For more detailed information on bypass capacitor placement; see Layout
Guidelines.
9.1 Input and ESD Protection
The TLVx314-Q1 family incorporates internal electrostatic discharge (ESD) protection circuits on all pins. In the
case of input and output pins, this protection primarily consists of current-steering diodes connected between the
input and power-supply pins. These ESD protection diodes provide in-circuit, input overdrive protection, as long
as the current is limited to 10 mA, as stated in the Absolute Maximum Ratings table. Figure 19 shows how a
series input resistor can be added to the driven input to limit the input current. The added resistor contributes
thermal noise at the amplifier input, which must be kept to a minimum in noise-sensitive applications.
V+
IOVERLOAD
10-mA maximum
Device
VOUT
VIN
5 kW
Figure 19. Input Current Protection
Copyright © 2016–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TLV314-Q1 TLV2314-Q1 TLV4314-Q1
19
TLV314-Q1, TLV2314-Q1, TLV4314-Q1
SBOS837A – NOVEMBER 2016 – REVISED JANUARY 2019
www.ti.com
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the
operational amplifier. Use bypass capacitors to reduce the coupled noise by providing low-impedance
power sources local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.
• Separate grounding for analog and digital portions of the circuitry is one of the simplest and most
effective methods of noise suppression. One or more layers on multilayer PCBs are typically devoted to
ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Take care to
physically separate digital and analog grounds, paying attention to the flow of the ground current. For
more detailed information, see Circuit Board Layout Techniques (SLOA089).
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicularly is much
better than crossing in parallel with the noisy trace.
• Place the external components as close to the device as possible. Keep RF and RG close to the inverting
input in order to minimize parasitic capacitance, as shown in Figure 20.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
10.2 Layout Example
+
VIN
VOUT
RG
RF
(Schematic Representation)
Place components
Run the input traces close to the device and
to
each other to reduce
as far away from
parasitic errors.
the supply lines
as possible.
VS+
RF
N/C
N/C
GND
±IN
V+
VIN
+IN
OUTPUT
V±
N/C
RG
Use a low-ESR,
ceramic bypass
capacitor.
GND
GND
Use a low-ESR, ceramic
bypass capacitor.
VOUT
VS±
Ground (GND) plane on another layer.
Figure 20. Operational Amplifier Board Layout for Noninverting Configuration
20
Submit Documentation Feedback
Copyright © 2016–2019, Texas Instruments Incorporated
Product Folder Links: TLV314-Q1 TLV2314-Q1 TLV4314-Q1
TLV314-Q1, TLV2314-Q1, TLV4314-Q1
www.ti.com
SBOS837A – NOVEMBER 2016 – REVISED JANUARY 2019
11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
• EMI Rejection Ratio of Operational Amplifiers (SBOA128).
• Circuit Board Layout Techniques (SLOA089).
• QFN/SON PCB Attachment (SLUA271).
• Quad Flatpack No-Lead Logic Packages (SCBA017).
11.3 Related Links
Table 2 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TLV314-Q1
Click here
Click here
Click here
Click here
Click here
TLV2314-Q1
Click here
Click here
Click here
Click here
Click here
TLV4314-Q1
Click here
Click here
Click here
Click here
Click here
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
Copyright © 2016–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TLV314-Q1 TLV2314-Q1 TLV4314-Q1
21
TLV314-Q1, TLV2314-Q1, TLV4314-Q1
SBOS837A – NOVEMBER 2016 – REVISED JANUARY 2019
www.ti.com
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
22
Submit Documentation Feedback
Copyright © 2016–2019, Texas Instruments Incorporated
Product Folder Links: TLV314-Q1 TLV2314-Q1 TLV4314-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TLV2314QDRQ1
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
V2314Q
TLV314QDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
16SD
TLV314QDBVTQ1
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
16SD
TLV4314QPWRQ1
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
V4314Q1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
