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TLV316-Q1, TLV2316-Q1, TLV4316-Q1
SBOS845B – NOVEMBER 2016 – REVISED AUGUST 2017
TLVx316-Q1
10-MHz, Rail-to-Rail Input/Output, Low-Voltage, 1.8-V CMOS Operational Amplifiers
1 Features
3 Description
•
•
The TLV316-Q1 (single), TLV2316-Q1 (dual), and
TLV4316-Q1 (quad) devices comprise a family of
general-purpose, low-power operational amplifiers.
Features such as rail-to-rail input and output swings,
low quiescent current (400 µA/ch typical) combined
with a wide bandwidth of 10 MHz, and very-low noise
(12 nV/√Hz at 1 kHz) make this family suitable for a
circuits requiring a good speed and power ratio. The
low input bias current supports operational amplifiers
that are used in applications with megaohm source
impedances. The low-input bias current of the
TLVx316-Q1 yields a very-low current noise to make
the family attractive for high impedance sensor
interfaces.
1
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 With the Following Results:
– Device Temperature Grade 1: –40°C to
+125°C Ambient Operating Temperature
Range
– Device HBM ESD Classification Level 3A
– Device CDM ESD Classification Level C5
Unity-Gain Bandwidth: 10 MHz
Low IQ: 400 µA/ch
– Excellent Power-to-Bandwidth Ratio
– Stable IQ Over Temperature and Supply
Range
Wide Supply Range: 1.8 V to 5.5 V
Low Noise: 12 nV/√Hz at 1 kHz
Low Input Bias Current: ±10 pA
Offset Voltage: ±0.75 mV
Unity-Gain Stable
Internal RFI and EMI Filter
Number of Channels:
– TLV316-Q1: 1
– TLV2316-Q1: 2
– TLV4316-Q1: 4
Extended Temperature Range: –40°C to +125°C
The robust design of the TLVx316-Q1 provides easeof-use to the circuit designer: a unity-gain stable,
integrated RFI and EMI rejection filter, no phase
reversal in overdrive condition, and high electrostatic
discharge (ESD) protection (4-kV HBM).
These devices are optimized for low-voltage
operation as low as 1.8 V (±0.9 V) and up to 5.5 V
(±2.75 V). This latest addition of low-voltage CMOS
operational amplifiers to the portfolio, in conjunction
with the TLVx313-Q1 and TLVx314-Q1 series, offer a
family of bandwidth, noise, and power options to
meet the needs of a wide variety of applications.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
2 Applications
TLV316-Q1
SOT-23 (5)
1.60 mm × 2.90 mm
•
TLV2316-Q1
VSSOP (8)
3.00 mm × 3.00 mm
TLV4316-Q1
TSSOP (14)
4.40 mm × 5.00 mm
Automotive Applications:
– ADAS
– Body Electronics and Lighting
– Current Sensing
– Battery Management Systems
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
RG
Low Supply Current (400 µA/Ch) for 10-MHz
Bandwidth
RF
VOUT
VIN
C1
f-3 dB =
1
2pR1C1
120
270
100
225
80
180
60
135
Phase
40
90
20
Phase (º)
R1
Gain (dB)
Single-Pole, Low-Pass Filter
45
VS
= “2.75 V
V
S = “2.75 V
0
0
Gain
VS
= “0.9
“0.9 VV
V
S =
(
RF
VOUT
= 1+
RG
VIN
((
1
1 + sR1C1
(
±20
1
10
100
1k
10k
100k
Frequency (Hz)
1M
10M
-45
100M
C006
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV316-Q1, TLV2316-Q1, TLV4316-Q1
SBOS845B – NOVEMBER 2016 – REVISED AUGUST 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
8
1
1
1
2
3
4
7
Absolute Maximum Ratings ...................................... 7
ESD Ratings ............................................................ 7
Recommended Operating Conditions....................... 7
Thermal Information: TLV316-Q1 ............................. 8
Thermal Information: TLV2316-Q1 ........................... 8
Thermal Information: TLV4316-Q1 ........................... 8
Electrical Characteristics........................................... 9
Typical Characteristics: Table of Graphs ................ 10
Typical Characteristics ............................................ 11
Detailed Description ............................................ 14
8.1 Overview ................................................................. 14
8.2 Functional Block Diagram ....................................... 14
8.3 Feature Description................................................. 15
8.4 Device Functional Modes........................................ 16
9
Application and Implementation ........................ 17
9.1 Application Information............................................ 17
9.2 System Examples ................................................... 17
10 Power Supply Recommendations ..................... 18
10.1 Input and ESD Protection ..................................... 18
11 Layout................................................................... 19
11.1 Layout Guidelines ................................................. 19
11.2 Layout Example .................................................... 19
12 Device and Documentation Support ................. 20
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
20
20
20
20
21
21
13 Mechanical, Packaging, and Orderable
Information ........................................................... 21
4 Revision History
Changes from Revision A (December 2016) to Revision B
Page
•
Corrected typo; changed part numbers from TLV314, TLV2314, and TLV4314 to TLV316-Q1, TLV2316-Q1, and
TLV4316-Q1 in Features section ........................................................................................................................................... 1
•
Changed values in the Thermal Information: TLV4316-Q1 table to align with JEDEC standards. ........................................ 8
Changes from Original (November 2016) to Revision A
Page
•
Changed the CDM ESD Classification Level from C6 to C5 in the Features section ............................................................ 1
•
Deleted the SC70 (5), SOIC (8), and SOIC (14) packages from the Device Information table ............................................ 1
•
Deleted the DCK (SC70) package from the TLV316-Q1 pinout diagram in the Pin Configurations and Functions
section ................................................................................................................................................................................... 4
•
Deleted the DCK (SC70) pinout information from the Pin Functions: TLV316-Q1 table in the Pin Configurations and
Functions section ................................................................................................................................................................... 4
•
Deleted D (SOIC) package from the TLV2316-Q1 pinout diagram in the Pin Configurations and Functions section .......... 5
•
Deleted the D (SOIC) package from TLV4316-Q1 pinout diagram in the Pin Configurations and Functions section ........... 6
•
Changed the ESD Ratings table from commercial to automotive specifications .................................................................. 7
•
Changed the CDM ESD rating from ±1500 to ±750 in the ESD Ratings table ..................................................................... 7
•
Deleted the DCK (SC70) package from the Thermal Information: TLV316-Q1 table in the Specifications section............... 8
•
Changed the formatting of all Thermal Information table notes ............................................................................................ 8
•
Deleted the D (SOIC) package from the Thermal Information: TLV2316-Q1 table in the Specifications section.................. 8
•
Deleted the D (SOIC) package from the Thermal Information: TLV4316-Q1 table in the Specifications section ................. 8
•
Deleted the static literature number in the SBOA128 application note reference in the EMI Susceptibility and Input
Filtering section..................................................................................................................................................................... 16
•
Deleted the static literature number in document reference in the Layout Guidelines section ........................................... 19
•
Changed the layout example image (Figure 41) in Layout Example section....................................................................... 19
•
Deleted the static literature numbers from document references in Related Documentation section ................................ 20
2
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Product Folder Links: TLV316-Q1 TLV2316-Q1 TLV4316-Q1
TLV316-Q1, TLV2316-Q1, TLV4316-Q1
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SBOS845B – NOVEMBER 2016 – REVISED AUGUST 2017
5 Device Comparison Table
PACKAGE-LEADS
DEVICE
NO. OF
CHANNELS
DBV
DCK
D
DGK
PW
TLV316-Q1
1
5
5
—
—
—
TLV2316-Q1
2
—
—
8
8
—
TLV4316-Q1
4
—
—
14
—
14
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3
TLV316-Q1, TLV2316-Q1, TLV4316-Q1
SBOS845B – NOVEMBER 2016 – REVISED AUGUST 2017
www.ti.com
6 Pin Configuration and Functions
TLV316-Q1 DBV Package
5-Pin SOT-23
Top View
OUT
1
V-
2
+IN
3
5
V+
4
-IN
Pin Functions: TLV316-Q1
PIN
NAME
NO.
I/O
DESCRIPTION
–IN
4
I
Inverting input
+IN
3
I
Noninverting input
OUT
1
O
Output
V–
2
—
Negative (lowest) supply or ground (for single-supply operation)
V+
5
—
Positive (highest) supply
4
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SBOS845B – NOVEMBER 2016 – REVISED AUGUST 2017
TLV2316-Q1 DGK Package
8-Pin VSSOP
Top View
OUT A
1
8
V+
-IN A
2
7
OUT B
+IN A
3
6
-IN B
V-
4
5
+IN B
Pin Functions: TLV2316 -Q1
PIN
I/O
DESCRIPTION
NAME
NO.
–IN A
2
I
Inverting input, channel A
+IN A
3
I
Noninverting input, channel A
–IN B
6
I
Inverting input, channel B
+IN B
5
I
Noninverting input, channel B
OUT A
1
O
Output, channel A
OUT B
7
O
Output, channel B
V–
4
—
Negative (lowest) supply or ground (for single-supply operation)
V+
8
—
Positive (highest) supply
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SBOS845B – NOVEMBER 2016 – REVISED AUGUST 2017
www.ti.com
TLV4316-Q1 PW Package
14-Pin TSSOP
Top View
14
OUT D
13
-IN D
3
12
+IN D
V+
4
11
V-
+IN B
5
10
+IN C
-IN B
6
9
-IN C
OUT B
7
8
OUT C
OUT A
1
-IN A
2
+IN A
A
B
D
C
Pin Functions: TLV4316-Q1
PIN
I/O
DESCRIPTION
NAME
NO.
–IN A
2
I
Inverting input, channel A
+IN A
3
I
Noninverting input, channel A
–IN B
6
I
Inverting input, channel B
+IN B
5
I
Noninverting input, channel B
–IN C
9
I
Inverting input, channel C
+IN C
10
I
Noninverting input, channel C
–IN D
13
I
Inverting input, channel D
+IN D
12
I
Noninverting input, channel D
OUT A
1
O
Output, channel A
OUT B
7
O
Output, channel B
OUT C
8
O
Output, channel C
OUT D
14
O
Output, channel D
V–
11
—
Negative (lowest) supply or ground (for single-supply operation)
V+
4
—
Positive (highest) supply
6
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SBOS845B – NOVEMBER 2016 – REVISED AUGUST 2017
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature (unless otherwise noted) (1)
MIN
MAX
UNIT
7
V
Supply voltage
Signal input pins
Voltage (2)
Common-mode
–10
(2)
(3)
mA
Continuous
–40
mA
125
Junction, TJ
150
Storage, Tstg
(1)
V
10
(3)
Specified, TA
Temperature
(V+) + 0.5
(V+) – (V–) + 0.2
Current (2)
Output short-circuit
(V–) – 0.5
Differential
–65
°C
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Input pins are diode-clamped to the power-supply rails. Current limit input signals that can swing more than 0.5 V beyond the supply
rails to 10 mA or less.
Short-circuit to ground, one amplifier per package.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
±4000
Charged-device model (CDM), per AEC Q100-011
±750
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VS
NOM
MAX
UNIT
Supply voltage
1.8
5.5
V
Specified temperature range
–40
125
°C
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7
TLV316-Q1, TLV2316-Q1, TLV4316-Q1
SBOS845B – NOVEMBER 2016 – REVISED AUGUST 2017
www.ti.com
7.4 Thermal Information: TLV316-Q1
TLV316-Q1
THERMAL METRIC (1)
DBV (SOT-23)
UNIT
5 PINS
RθJA
Junction-to-ambient thermal resistance
221.7
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
144.7
°C/W
RθJB
Junction-to-board thermal resistance
49.7
°C/W
ψJT
Junction-to-top characterization parameter
26.1
°C/W
ψJB
Junction-to-board characterization parameter
49.0
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal resistance
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Thermal Information: TLV2316-Q1
TLV2316-Q1
THERMAL METRIC
(1)
DGK (VSSOP)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
186.6
°C/W
RθJC(top)
RθJB
Junction-to-case(top) thermal resistance
78.8
°C/W
Junction-to-board thermal resistance
107.9
°C/W
ψJT
Junction-to-top characterization parameter
15.5
°C/W
ψJB
Junction-to-board characterization parameter
106.3
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal resistance
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.6 Thermal Information: TLV4316-Q1
TLV4316-Q1
THERMAL METRIC
(1)
PW (TSSOP)
UNIT
14 PINS
RθJA
Junction-to-ambient thermal resistance
117.8
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
46.5
°C/W
RθJB
Junction-to-board thermal resistance
59.6
°C/W
ψJT
Junction-to-top characterization parameter
5.3
°C/W
ψJB
Junction-to-board characterization parameter
59
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal resistance
N/A
°C/W
(1)
8
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SBOS845B – NOVEMBER 2016 – REVISED AUGUST 2017
7.7 Electrical Characteristics
at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted); VS (total supply
voltage) = (V+) – (V–) = 1.8 V to 5.5 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
VS = 5 V
±0.75
VOS
Input offset voltage
dVOS/dT
Drift
VS = 5 V, TA = –40°C to 125°C
±2
PSRR
Power-supply rejection ratio
VS = 1.8 V – 5.5 V, VCM = (V–)
±30
Channel separation, dc
At dc
100
VS = 5 V, TA = –40°C to 125°C
±3
±4.5
mV
µV/°C
±175
µV/V
dB
INPUT VOLTAGE RANGE
VCM
Common-mode voltage range
CMRR
VS = 5.5 V
VS = 5.5 V, (V–) – 0.2 V < VCM < (V+) – 1.4 V,
TA = –40°C to 125°C
Common-mode rejection ratio
(V–) – 0.2
72
(V+) + 0.2
V
90
dB
VS = 5.5 V, VCM = –0.2 V to 5.7 V,
TA = –40°C to 125°C
75
INPUT BIAS CURRENT
IB
Input bias current
±10
pA
IOS
Input offset current
±10
pA
NOISE
En
Input voltage noise (peak-to-peak)
VS = 5 V, f = 0.1 Hz to 10 Hz
5
µVPP
en
Input voltage noise density
in
Input current noise density
VS = 5 V, f = 1 kHz
12
nV/√Hz
f = 1 kHz
1.3
fA/√Hz
INPUT IMPEDANCE
ZID
Differential
2 || 2
1016Ω || pF
ZIC
Common-mode
2 || 4
1011Ω || pF
OPEN-LOOP GAIN
AOL
VS = 5.5 V, (V–) + 0.05 V < VO < (V+) – 0.05 V,
RL = 10 kΩ
Open-loop voltage gain
100
104
dB
VS = 5.5 V, (V–) + 0.15 V < VO < (V+) – 0.15 V,
RL = 2 kΩ
104
FREQUENCY RESPONSE
GBP
Gain bandwidth product
VS = 5 V, G = 1
10
MHz
φm
Phase margin
VS = 5 V, G = 1
60
Degrees
SR
Slew rate
VS = 5 V, G = 1
6
V/μs
tS
Settling time
To 0.1%, VS = 5 V, 2-V step , G = 1, CL = 100 pF
1
μs
tOR
Overload recovery time
VS = 5 V, VIN × gain = VS
0.8
μs
THD + N
Total harmonic distortion + noise (1)
VS = 5 V, VO = 0.5 VRMS, G = 1, f = 1 kHz
VO
Voltage output swing from supply
rails
VS = 1.8 V to 5.5 V, RL = 10 kΩ
ISC
Short-circuit current
VS = 5 V
±50
mA
ZO
Open-loop output impedance
VS = 5 V, f = 10 MHz
250
Ω
0.008%
OUTPUT
35
VS = 1.8 to 5.5 V, RL = 2 kΩ
125
mV
POWER SUPPLY
VS
Specified voltage range
IQ
Quiescent current per amplifier
1.8
VS = 5 V, IO = 0 mA, TA = –40°C to 125°C
400
5.5
V
575
µA
TEMPERATURE
TA
Specified
–40
125
°C
Tstg
Storage
–65
150
°C
(1)
Third-order filter; bandwidth = 80 kHz at –3 dB.
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7.8 Typical Characteristics: Table of Graphs
Table 1. Table of Graphs
TITLE
FIGURE
Offset Voltage Production Distribution
Figure 1
Offset Voltage vs Common-Mode Voltage
Figure 2
Open- Loop Gain and Phase vs Frequency
Figure 3
Input Bias and Offset Current vs Temperature
Figure 4
Input Voltage Noise Spectral Density vs Frequency
Figure 5
Quiescent Current vs Supply Voltage
Figure 6
Small-Signal Overshoot vs Load Capacitance
Figure 7
No Phase Reversal
Figure 8
Small-Signal Step Response
Figure 9
Large-Signal Step Response
Figure 10
Short-Circuit Current vs Temperature
Figure 11
Electromagnetic Interference Rejection Ratio Referred to Noninverting Input vs Frequency
Figure 12
Channel Separation vs Frequency
Figure 13
10
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SBOS845B – NOVEMBER 2016 – REVISED AUGUST 2017
7.9 Typical Characteristics
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, (unless otherwise noted)
2500
25
1500
VCM = 2.95 V
VCM = -2.95 V
1000
15
VOS ( V)
Percentage of Amplifiers (%)
2000
20
10
500
0
±500
±1000
5
NChannel
PChannel
±1500
Transition
±2500
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
-1.0
-1.5
-2.0
-2.5
±2000
0
±3
±2
0
±1
1
C013
V+ = 2.75 V
V– = –2.75 V
9 typical units
shown
Figure 2. Offset Voltage vs Common-Mode Voltage
100
225
80
180
60
135
Phase
40
90
20
100000
45
0
Gain
1000
VS
= “0.9
“0.9 VV
V
S =
±20
1
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
IB+
IB Ios
10000
Input Bias Current and
Input Offset Current (pA)
270
Phase (º)
Gain (dB)
Figure 1. Offset Voltage Production Distribution
120
0
-45
100M
100
10
1
0
±75
C006
±50
±25
0
VCM < (V+) – 1.4 V
25
50
75
100
125
Temperature (ƒC)
Figure 3. Open-Loop Gain and Phase vs Frequency
150
C001
Figure 4. Input Bias and Offset Current vs Temperature
450
1000
425
400
100
375
IQ (µA)
9ROWDJH 1RLVH 'HQVLW\ Q9 ¥+]
3
C001
Distribution taken from 12551 amplifiers
VS
= “2.75 V
V
S = “2.75 V
2
VCM (V)
Offset Voltage (mV)
350
325
10
300
275
250
1
0.1
1
10
100
1k
Frequency (Hz)
10k
100k
Figure 5. Input Voltage Noise Spectral Density vs Frequency
Copyright © 2016–2017, Texas Instruments Incorporated
1.5
2
2.5
3
3.5
4
4.5
5
5.5
Supply Voltage (V)
C015
6
C001
Figure 6. Quiescent Current vs Supply Voltage
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Typical Characteristics (continued)
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, (unless otherwise noted)
50
VIN
40
RI = 1 kohm
1 V/div
Overshoot (%)
VOUT
30
RF = 1 kohm
20
+ 2.75 V
±
Device
+ 2.75 V
±
+
10
Device
VIN = 100 mVpp
+
±
± 2.75 V
0
0p
100p
200p
Time (100 s/div)
300p
Capacitive Load (F)
C027
C025
V+ = 2.75 V, V– = –2.75 V
V+ = 2.75 V, V– = –2.75 V, G = –1 V/V
Figure 8. No Phase Reversal
Figure 7. Small-Signal Overshoot vs Load Capacitance
+ 2.75 V
CL
= 10 pF
C
L = 10 pF
±
Device
CL
= 100
100 pF
pF
C
L =
Output Voltage (20 mV/div)
± 2.75 V
6.1 VPP
Sine Wave
±
CL
VOUT
+
+
+
VIN = 1 Vpp
+
± 2.75 V
RL
CL
200 mV/div
±
+ 2.75 V
VOUT
±
Device
+
VIN = 100 mVpp
+
RL
± 2.75 V
CL
±
VIN
Time (200 ns/div)
Time (100 ns/div)
C030
C031
V+ = 2.75 V, V– = –2.75 V, G = 1 V/V
V+ = 2.75 V, V– = –2.75 V, CL = 100 pF, G = 1 V/V
Figure 9. Small-Signal Step Response
Figure 10. Large-Signal Step Response
70
100
80
EMIRR IN+ (dB)
60
ISC (mA)
ISC, Source
50
ISC, Sink
40
60
40
20
0
30
±75
±50
±25
0
25
50
75
100
125
150
Temperature (ƒC)
10M
100M
Frequency (Hz)
C001
1G
10G
C036
PRF = –10 dBm
Figure 11. Short-Circuit Current vs Temperature
12
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Figure 12. Electromagnetic Interference Rejection Ratio
Referred to Noninverting Input vs Frequency
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Typical Characteristics (continued)
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, (unless otherwise noted)
0
Crosstalk (dB)
±20
±40
±60
±80
±100
±120
10
100
1k
10k
100k
1M
Frequency (Hz)
10M
C001
V+ = 2.75 V, V– = –2.75 V
Figure 13. Channel Separation vs Frequency
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8 Detailed Description
8.1 Overview
The TLVx316-Q1 is a family of low-power, rail-to-rail input and output operational amplifiers. These devices
operate from 1.8 V to 5.5 V, are unity-gain stable, and are suitable for a wide range of general-purpose
applications. The class AB output stage is capable of driving ≤ 10-kΩ loads connected to any point between V+
and ground. The input common-mode voltage range includes both rails and allows the TLVx316-Q1 to be used in
virtually any single-supply application. Rail-to-rail input and output swing significantly increases dynamic range,
especially in low-supply applications, and makes them suitable for driving sampling analog-to-digital converters
(ADCs).
The TLVx316-Q1 features 10-MHz bandwidth and 6-V/μs slew rate with only 400-μA supply current per channel,
providing good ac performance at very-low-power consumption. DC applications are well served with a very-low
input noise voltage of 12 nV/√Hz at 1 kHz, low input bias current (5 pA), and an input offset voltage of 0.5 mV
(typical).
8.2 Functional Block Diagram
V+
Reference
Current
VIN–
VIN+
VBIAS1
Class AB
Control
Circuitry
VO
VBIAS2
V–
(Ground)
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8.3 Feature Description
8.3.1 Operating Voltage
The TLVx316-Q1 operational amplifiers are fully specified and ensured for operation from 1.8 V to 5.5 V. In
addition, many specifications apply from –40°C to +125°C. Parameters that vary significantly with operating
voltages or temperature are illustrated in the Typical Characteristics section.
8.3.2 Rail-to-Rail Input
The input common-mode voltage range of the TLVx316-Q1 extends 200 mV beyond the supply rails for supply
voltages greater than 2.5 V. This performance is achieved with a complementary input stage: an N-channel input
differential pair in parallel with a P-channel differential pair, as shown in the Functional Block Diagram. The Nchannel pair is active for input voltages close to the positive rail, typically (V+) – 1.4 V to 200 mV above the
positive supply, whereas the P-channel pair is active for inputs from 200 mV below the negative supply to
approximately (V+) – 1.4 V. There is a small transition region, typically (V+) – 1.2 V to (V+) – 1 V, in which both
pairs are on. This 200-mV transition region can vary up to 200 mV with process variation. Thus, the transition
region (both stages on) can range from (V+) – 1.4 V to (V+) – 1.2 V on the low end, up to (V+) – 1 V to (V+) –
0.8 V on the high end. Within this transition region, PSRR, CMRR, offset voltage, offset drift, and THD can be
degraded compared to device operation outside this region.
8.3.3 Rail-to-Rail Output
Designed as a low-power, low-voltage operational amplifier, the TLVx316-Q1 delivers a robust output drive
capability. A class AB output stage with common-source transistors is used to achieve full rail-to-rail output swing
capability. For resistive loads of 10 kΩ, the output swings typically to within 30 mV of either supply rail regardless
of the power-supply voltage applied. Different load conditions change the ability of the amplifier to swing close to
the rails; see .
8.3.4 Common-Mode Rejection Ratio (CMRR)
CMRR for the TLVx316-Q1 is specified in two ways so the best match for a given application can be selected.
The Electrical Characteristics table provides the CMRR of the device in the common-mode range below the
transition region [VCM < (V+) – 1.4 V]. This specification is the best indicator of device capability when the
application requires using one of the differential input pairs. The CMRR over the entire common-mode range is
specified at VCM = –0.2 V to 5.7 V for VS = 5.5 V. This last value includes the variations through the transition
region.
8.3.5 Capacitive Load and Stability
The TLVx316-Q1 is designed for applications where driving a capacitive load is required. As with all operational
amplifiers, there may be specific instances where the TLVx316-Q1 can become unstable. The particular
operational amplifier circuit configuration, layout, gain, and output loading are some of the factors to consider
when establishing whether or not an amplifier is stable in operation. An operational amplifier in the unity-gain (1
V/V) buffer configuration that drives a capacitive load exhibits a greater tendency to be unstable than an amplifier
operated at a higher noise gain. The capacitive load, in conjunction with the operational amplifier output
resistance, creates a pole within the feedback loop that degrades the phase margin. The degradation of the
phase margin increases when the capacitive loading increases. For a conservative best practice, designing for
25% overshoot (40° phase margin) provides improved stability over process variations. The equivalent series
resistance (ESR) of some very-large capacitors (CL capacitors with a value greater than 1 μF) is sufficient to alter
the phase characteristics in the feedback loop such that the amplifier remains stable. Increasing the amplifier
closed-loop gain allows the amplifier to drive increasingly larger capacitance. This increased capability is evident
when observing the overshoot response of the amplifier at higher voltage gains, as shown in Figure 7 (G = –1
V/V).
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Feature Description (continued)
One technique for increasing the capacitive load drive capability of the amplifier operating in a unity-gain
configuration is to insert a small resistor (typically 10-Ω to 20-Ω) in series with the output, as shown in Figure 14.
This resistor significantly reduces the overshoot and ringing associated with large capacitive loads. One possible
problem with this technique, however, is that a voltage divider is created with the added series resistor and any
resistor connected in parallel with the capacitive load. The voltage divider introduces a gain error at the output
that reduces the output swing.
V+
RS
VOUT
Device
VIN
10 W to
20 W
RL
CL
Figure 14. Improving Capacitive Load Drive
8.3.6 EMI Susceptibility and Input Filtering
Operational amplifiers vary with regard to the susceptibility of the device to electromagnetic interference (EMI). If
conducted EMI enters the operational amplifier, the dc offset measured at the amplifier output can shift from the
nominal value when EMI is present. This shift is a result of signal rectification associated with the internal
semiconductor junctions. Although EMI can affect all operational amplifier pin functions, the signal input pins are
likely to be the most susceptible. The TLVx316-Q1 operational amplifier family incorporates an internal input lowpass filter that reduces the amplifier response to EMI. This filter provides both common-mode and differentialmode filtering. The filter is designed for a cutoff frequency of approximately 80 MHz (–3 dB), with a roll-off of 20
dB per decade.
The immunity of an operational amplifier can be accurately measured and quantified over a broad frequency
spectrum extending from 10 MHz to 6 GHz. The EMI rejection ratio (EMIRR) metric allows operational amplifiers
to be directly compared by the EMI immunity. Figure 12 illustrates the results of this testing on the TLVx316-Q1.
Detailed information can be found in EMI Rejection Ratio of Operational Amplifiers, available for download from
www.ti.com.
8.3.7 Overload Recovery
Overload recovery is defined as the time required for the operational amplifier output to recover from a saturated
state to a linear state. The output devices of the operational amplifier enter a saturation region when the output
voltage exceeds the rated operating voltage, either because of the high input voltage or the high gain. After the
device enters the saturation region, the charge carriers in the output devices require time to return back to the
linear state. After the charge carriers return back to the linear state, the device begins to slew at the specified
slew rate. Thus, the propagation delay in case of an overload condition is the sum of the overload recovery time
and the slew time. The overload recovery time for the TLVx316-Q1 is approximately 300 ns.
8.4 Device Functional Modes
The TLVx316-Q1 family has a single functional mode. These devices are powered on as long as the powersupply voltage is between 1.8 V (±0.9 V) and 5.5 V (±2.75 V).
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TLV316-Q1, TLV2316-Q1, and TLV4316-Q1 devices are powered on when the supply is connected. The
devices can operate as a single-supply operational amplifier or a dual-supply amplifier, depending on the
application.
9.2 System Examples
When receiving low-level signals, the device often requires limiting the bandwidth of the incoming signals into the
system. The simplest way to establish this limited bandwidth is to place an RC filter at the noninverting pin of the
amplifier, as shown in Figure 15.
RG
RF
R1
VOUT
VIN
C1
f-3 dB =
(
RF
VOUT
= 1+
RG
VIN
((
1
1 + sR1C1
1
2pR1C1
(
Figure 15. Single-Pole, Low-Pass Filter
If even more attenuation is needed, the device requires a multiple-pole filter. The Sallen-Key filter can be used
for this task, as shown in Figure 16. For best results, the amplifier must have a bandwidth that is eight to ten
times the filter frequency bandwidth. Failure to follow this guideline can result in a phase shift of the amplifier.
C1
R1
R1 = R2 = R
C1 = C2 = C
Q = Peaking factor
(Butterworth Q = 0.707)
R2
VIN
VOUT
C2
1
2pRC
f-3 dB =
RF
RF
RG =
RG
(
2-
1
Q
(
Figure 16. Two-Pole, Low-Pass, Sallen-Key Filter
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10 Power Supply Recommendations
The TLVx316-Q1 family is specified for operation from 1.8 V to 5.5 V (±0.9 V to ±2.75 V); many specifications
apply from –40°C to +125°C. The Typical Characteristics section presents parameters that can exhibit significant
variance with regard to operating voltage or temperature.
CAUTION
Supply voltages larger than 7 V can permanently damage the device; see the Absolute
Maximum Ratings table.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. For more detailed information on bypass capacitor placement, see the Layout
Guidelines section.
10.1 Input and ESD Protection
The TLVx316-Q1 incorporates internal ESD protection circuits on all pins. For input and output pins, this
protection primarily consists of current-steering diodes connected between the input and power-supply pins.
These ESD protection diodes provide in-circuit, input overdrive protection, as long as the current is limited to 10
mA, as stated in the Absolute Maximum Ratings table. Figure 17 shows how a series input resistor can be added
to the driven input to limit the input current. The added resistor contributes thermal noise at the amplifier input
and the value must be kept to a minimum in noise-sensitive applications.
V+
IOVERLOAD
10-mA max
Device
VOUT
VIN
5 kW
Figure 17. Input Current Protection
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11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the
operational amplifier. Bypass capacitors reduce the coupled noise by providing low-impedance power
sources local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.
• Separate grounding for analog and digital portions of the circuitry is one of the simplest and most
effective methods of noise suppression. One or more layers on multilayer PCBs are typically devoted to
ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Take care to
physically separate digital and analog grounds, paying attention to the flow of the ground current. For
more detailed information, see Circuit Board Layout Techniques.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicularly is much
better than crossing in parallel with the noisy trace.
• Place the external components as close to the device as possible. Keeping RF and RG close to the
inverting input minimizes parasitic capacitance, as shown in Figure 18.
• Keep the length of input traces as short as possible. Remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
11.2 Layout Example
Run the input traces
as far away from
the supply lines
VIN
as possible.
VS±
VS+
+IN
V+
GND
Use a low-ESR,
ceramic bypass
capacitor.
V±
Use a low-ESR,
ceramic bypass
capacitor.
RG
OUT
±IN
VOUT
GND
Place components
close to the device
and to each other to
reduce parasitic
errors.
RF
Copyright © 2016, Texas Instruments Incorporated
Figure 18. Operational Amplifier Board Layout for a Noninverting Configuration
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
TLVx313 Low-Power, Rail-to-Rail In/Out, 500-μV Typical Offset, 1-MHz Operational Amplifier for Cost-Sensitive
Systems
TLVx314 3-MHz, Low-Power, Internal EMI Filter, RRIO, Operational Amplifier
EMI Rejection Ratio of Operational Amplifiers
QFN/SON PCB Attachment
Quad Flatpack No-Lead Logic Packages
Circuit Board Layout Techniques
Single-Ended Input to Differential Output Conversion Circuit Reference Design
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 2. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TLV316-Q1
Click here
Click here
Click here
Click here
Click here
TLV2316-Q1
Click here
Click here
Click here
Click here
Click here
TLV4316-Q1
Click here
Click here
Click here
Click here
Click here
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
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SBOS845B – NOVEMBER 2016 – REVISED AUGUST 2017
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TLV2316QDGKRQ1
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
16M6
TLV2316QDGKTQ1
ACTIVE
VSSOP
DGK
8
250
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
16M6
TLV316QDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
16ND
TLV316QDBVTQ1
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
16ND
TLV4316QPWRQ1
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
V4316Q1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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