TLV320AIC3253
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SLOS631 – MARCH 2010
Ultra Low Power Stereo Audio Codec With Embedded miniDSP
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FEATURES
APPLICATIONS
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1
2
Stereo Audio DAC with 100dB SNR
4.1mW Stereo 48ksps Playback
PowerTune™
Extensive Signal Processing Options
Embedded miniDSP
Stereo Digital Microphone Input
Stereo Headphone Outputs
Low Power Analog Bypass Mode
Programmable PLL
Integrated LDO
2.7mm × 2.7mm WCSP or 4mm × 4mm QFN
Package
Mobile Handsets
Communication
Portable Computing
DESCRIPTION
The TLV320AIC3253 (sometimes referred to as the
AIC3253) is a flexible, low-power, low-voltage stereo
audio codec with digital microphone inputs and
programmable outputs, PowerTune capabilities,
fully-programmable miniDSP, fixed predefined and
parameterizable signal processing blocks, integrated
PLL, integrated LDO and flexible digital interfaces.
Extensive
register-based
control
of
power,
input/output channel configuration, gains, effects,
pin-multiplexing and clocks is included, allowing the
device to be precisely targeted to its application.
INL
DRC
INR
Vol. Ctrl
-6...+29dB
DAC Signal Proc.
ADC Signal Proc.
Dig.
Mic IF
DMCLK/
MFP4
miniDSP
Data Interface
DMDIN/
MFP3
*
Left
DAC
HPL
+
1dB steps
miniDSP
-6...+29dB
DAC Signal Proc.
Right
DAC
*
HPR
+
1dB steps
DRC
Vol. Ctrl
ALDO
LDOin
AVdd
SPI_Select
Interrupt Secondary
Ctrl
I2S IF
PLL
Primary
I2S Interface
IOVdd
Mic Bias
Pin Muxing/ Clock Routing
Ref
Supplies
Reset
SPI / I2C
Control Block
DVdd
IOVss
DVss
AVss
Ref
Micbias
BCLK
WCLK
DOUT/MFP2
DIN/MFP1
MCLK
GPIO
(YZK Pkg only)
SDA/MOSI
SCL/SS
Figure 1. Simplified Block Diagram
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerTune is a trademark of Texas Instruments.
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
TLV320AIC3253
SLOS631 – MARCH 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DESCRIPTION (CONTINUED)
Combined with the advanced PowerTune technology, the device can cover operations from 8kHz mono voice
playback to stereo 192kHz DAC playback, making it ideal for portable battery-powered audio and telephony
applications.
The record path of the TLV320AIC3253 consists of a stereo digital microphone PDM interface (not available
when using SPI control interface) typically used at 64Fs or 128Fs.
The playback path offers signal processing blocks for filtering and effects, true differential output signal, flexible
mixing of DAC and analog input signals as well as programmable volume controls. The TLV320AIC3253
contains two high-power output drivers which can be configured in multiple ways, including stereo, and mono
BTL. The integrated PowerTune technology allows the device to be tuned to just the right power-performance
trade-off. Mobile applications frequently have multiple use cases requiring very low-power operation while being
used in a mobile environment. When used in a docked environment power consumption typically is less of a
concern while lowest possible noise is important. With PowerTune the TLV320AIC3253 can address both cases.
The voltage supply range for the TLV320AIC3253 for analog is 1.5V–1.95V, and for digital it is 1.26V–1.95V. To
ease system-level design, a low-dropout regulator (LDO) is integrated to generate the appropriate analog supply
from input voltages ranging from 1.8V to 3.6V. Digital I/O voltages are supported in the range of 1.1V–3.6V.
The required internal clock of the TLV320AIC3253 can be derived from multiple sources, including the MCLK pin,
the BCLK pin, the GPIO pin or the output of the internal PLL, where the input to the PLL again can be derived
from the MCLK pin, the BCLK or GPIO pins. Although using the internal, fractional PLL ensures the availability of
a suitable clock signal, it is not recommended for the lowest power settings. The PLL is highly programmable and
can accept available input clocks in the range of 512kHz to 50MHz.
The device is available in the 2.7mm × 2.7mm WCSP or the 4mm × 4mm QFN package.
2
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SLOS631 – MARCH 2010
Package and Signal Descriptions
Packaging/Ordering Information
PRODUCT
TLV320AIC3253
PACKAGE
PACKAGE
DESIGNATOR
OPERATING
TEMPERATURE
RANGE
S-XBGA-N25
YZK
–40°C to 85°C
S-PQFP-N
RGE
ORDERING
NUMBER
–40°C to 85°C
TRANSPORT MEDIA,
QUANTITY
TLV320AIC3253IYZKT
Tape and Reel, 250
TLV320AIC3253IYZKR
Tape and Reel, 3000
TLV320AIC3253IRGET
Tape and Reel, 250
TLV320AIC3253IRGER
Tape and Reel, 3000
Pin Assignments
space
space
E
D
C
B
A
1
2
3
4
5
DMDIN/MFP3
DOUT/MFP2
DIN/MFP1
WCLK
BCLK
MCLK (1)
Figure 2. S-XBGA-N25 (YZK) Package, Bottom View
SCL/SS
IOVdd (24)
IOVss
SDA/MOSI
DVdd
DMCLK/MFP4
DVss
HPR
LDOin
RESET
HPL
SPI_SELECT
AVdd
AVss
INR
INL
REF
MICBIAS
Figure 3. S-PQFP-N (RGE) Package, Bottom View
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TERMINAL FUNCTIONS
TERMINAL
DESCRIPTION
(1) (2)
QFN PIN
WCSP
BALL
NAME
TYPE
1
A1
MCLK
I
2
B2
BCLK
IO
Audio serial data bus (primary) bit clock
3
B3
WCLK
IO
Audio serial data bus (primary) word clock
4
A2
DIN/MFP1
I
Master Clock Input
Primary function
Audio serial data bus data input
Secondary function
Digital Microphone Input
General Purpose Input
5
A3
DOUT/MFP2
O
Primary
Audio serial data bus data output
Secondary
General Purpose Output
Clock Output
INT1 Output
INT2 Output
Audio serial data bus (secondary) bit clock output
Audio serial data bus (secondary) word clock output
6
A5
DMDIN/
MFP3/
SCLK
I
Primary (SPI_Select = 1)
SPI serial clock
Secondary: (SPI_Select = 0)
Digital microphone input
Headset detect input
Audio serial data bus (secondary) bit clock input
Audio serial data bus (secondary) DAC/common word clock input
Audio serial data bus (secondary) ADC word clock input
Audio serial data bus (secondary) data input
General Purpose Input
7
A4
SCL/
SS
I
I2C interface serial clock (SPI_Select = 0)
SPI interface mode chip-select signal (SPI_Select = 1)
8
B4
SDA/ MOSI
I
I2C interface mode serial data input (SPI_Select = 0)
SPI interface mode serial data input (SPI_Select = 1)
9
B5
DMCLK/
MFP4/
MISO
O
Primary (SPI_Select = 1)
Serial data output
Secondary (SPI_Select = 0) Multifunction pin #4 (MFP4) options are only available
using I2C
Digital microphone clock output
General purpose output
CLKOUT output
INT1 output
INT2 output
Audio serial data bus (primary) ADC word clock output
Audio serial data bus (secondary) data output
Audio serial data bus (secondary) bit clock output
Audio serial data bus (secondary) word clock output
(1)
(2)
4
10
C5
HPR
O
11
D5
LDOIN/
HPVDD
Power
12
D4
HPL
O
Right high-power output driver
LDO Input supply and Headphone Power supply 1.9V– 3.6V
Left high power output driver
For multiple BGA Balls assigned to the same pin-name, it is necessary to connect them on the PCB.
For multiple BGA Balls assigned to the same pin-name, it is recommended to connect them on the PCB.
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TERMINAL FUNCTIONS (continued)
TERMINAL
(1) (2)
QFN PIN
WCSP
BALL
NAME
TYPE
DESCRIPTION
13
D3
AVDD
Power
Analog voltage supply 1.5V–1.95V
Input when A-LDO disabled,
Filtering output when A-LDO enabled
14
E4
AVSS
Ground
Analog ground supply
15
E5
INL
I
Left Analog Bypass Input
16
E3
INR
I
Right Analog Bypass Input
17
E2
REF
O
Reference voltage output for filtering
18
D2
MICBIAS
O
Microphone bias voltage output
19
E1
SPI_ SELECT
I
Control mode select pin ( 1 = SPI, 0 = I2C )
20
C2
RESET
I
Reset (active low)
21
D1
DVSS
Ground
Digital Ground and Chip-substrate
22
C1
DVDD
Power
Digital voltage supply 1.26V–1.95V
23
B1
IOVSS
Ground
I/O ground supply
24
C3
IOVDD
Power
I/O voltage supply 1.1V – 3.6V
n/a
C4
GPIO/MFP5
I
Primary
General Purpose digital IO
Secondary
CLKOUT Output
INT1 Output
INT2 Output
Audio serial data bus ADC word clock output
Audio serial data bus (secondary) bit clock output
Audio serial data bus (secondary) word clock output
Digital microphone clock output
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Electrical Characteristics
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
UNIT
AVdd to AVss
–0.3 to 2.2
V
DVdd to DVss
–0.3 to 2.2
V
IOVDD to IOVSS
–0.3 to 3.9
V
LDOIN to AVss
–0.3 to 3.9
V
Digital Input voltage
–0.3 to IOVDD + 0.3
V
Analog input voltage
–0.3 to AVdd + 0.3
V
Operating temperature range
–40 to 85
°C
Storage temperature range
–55 to 125
°C
105
°C
(TJ Max – TA)/ qJA
W
48
C/W
Junction temperature (TJ Max)
S-XBGA NanoFree
package (YZK)
(1)
Power dissipation
qJA Thermal impedance
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Recommended Operating Conditions
MIN NOM
LDOIN
(1)
Power Supply Voltage Range
Referenced to AVss
(2)
1.9
AVdd
1.5
IOVDD
Referenced to IOVSS (2)
DVdd
Referenced to DVss (2)
PLL Input Frequency
3.6
1.8
1.95
1.65
1.8
1.95
1.26
1.8
1.95
1.1
DVdd (3)
Clock divider uses fractional divide
(D > 0), P=1, DVdd ≥ 1.65V (See table in SLAU303,
Maximum TLV320AIC3253 Clock Frequencies)
Clock divider uses integer divide
(D = 0), P=1, DVdd ≥ 1.65V (Refer to table in
SLAU303, Maximum TLV320AIC3253 Clock
Frequencies)
MAX
UNIT
V
3.6
10
20
MHz
0.512
20
MHz
50
MHz
400
kHz
MCLK; Master Clock Frequency; DVdd ≥ 1.65V
MCLK
Master Clock Frequency
SCL
SCL Clock Frequency
HPL,
HPR
Stereo headphone output load
resistance
Single-ended configuration
14.4
16
Headphone output load resistance
Differential configuration
24.4
32
Ω
10
pF
10
µF
CLout
Digital output load capacitance
Cref
Reference decoupling capacitor
(1)
(2)
(3)
(4)
6
(4)
1
Ω
Minimum spec applies if LDO is used. Minimum is 1.5V if LDO is not enabled. Using the LDO below 1.9V degrades LDO performance.
All grounds on board are tied together, so they should not differ in voltage by more than 0.2V max, for any combination of ground
signals.
At DVdd values lower than 1.65V, the PLL does not function. Please see table in SLAU303, Maximum TLV320AIC3253 Clock
Frequencies for details on maximum clock frequencies.
For Cref< 10µF, performance may decrease. Electrical characteristics are based on Cref=10µF.
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Electrical Characteristics, Bypass Outputs
At 25°C, AVdd, DVdd, IOVDD = 1.8V, LDO_in = 1.8V, AVdd LDO disabled, fs (Audio) = 48kHz, Cref = 10 mF on REF PIN,
PLL disabled unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG BYPASS TO HEADPHONE AMPLIFIER, DIRECT MODE
Load = 16Ω (single-ended), 50pF;
Input and Output CM=0.9V;
Headphone Output on LDOIN Supply;
INL routed to HPL and INR routed to HPR;
Channel Gain=0dB
Device Setup
Gain Error
Noise, A-weighted
THD
(1)
±0.4
(1)
Total Harmonic Distortion
Idle Channel, INL and INR ac-shorted to
ground
dB
3
446mVrms, 1-kHz input signal
mVRMS
–82
dB
All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may
result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values
Electrical Characteristics, Microphone Interface
At 25°C, AVdd, DVdd, IOVDD = 1.8V, LDO_in = 1.8V, AVdd LDO disabled, Cref = 10 mF on REF PIN, PLL disabled unless
otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MICROPHONE BIAS
Bias voltage
Bias voltage CM=0.9V, LDOin = 3.3V, no load
Micbias Mode 0, Connect to AVdd or LDOin
1.25
V
Micbias Mode 1, Connect to LDOin
1.7
V
Micbias Mode 2, Connect to LDOin
2.5
V
Micbias Mode 3, Connect to AVdd
AVdd
V
Micbias Mode 3, Connect to LDOin
LDOin
V
Micbias Mode 0, Connect to AVdd or LDOin
1.04
V
Micbias Mode 1, Connect to AVdd or LDOin
1.42
V
Micbias Mode 2, Connect to LDOin
2.08
V
Micbias Mode 3, Connect to AVdd
AVdd
V
Micbias Mode 3, Connect to LDOin
LDOin
V
CM=0.75V, LDOin = 3.3V
Output Noise
Current Sourcing
Inline Resistance
CM=0.9V, Micbias Mode 2, A-weighted, 20Hz
to 20kHz bandwidth,
Current load = 0mA.
Micbias Mode 2, Connect to LDOin
10
mVRMS
3
Micbias Mode 3, Connect to AVdd
160
Micbias Mode 3, Connect to LDOin
110
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mA
Ω
7
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SLOS631 – MARCH 2010
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Electrical Characteristics, Audio Outputs
At 25°C, AVdd, DVdd, IOVDD = 1.8V, LDO_in = 1.8V, AVdd LDO disabled, fs (Audio) = 48kHz, Cref = 10 mF on REF PIN,
PLL disabled unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio DAC – Stereo Single-Ended Headphone Output
Load = 16Ω (single-ended), 50pF
Headphone Output on AVdd Supply,
Input & Output CM=0.9V, DOSR = 128,
MCLK=256* fs, Channel Gain=0dB
word length = 16 bits;
Processing Block = PRB_P1
Power Tune = PTM_P3
Device Setup
Full scale output voltage (0dB)
(1) (2)
88
VRMS
100
dB
99
dB
SNR
Signal-to-noise ratio, A-weighted
DR
Dynamic range, A-weighted
THD+N
Total Harmonic Distortion plus Noise
–3dB full-scale, 1-kHz input signal
–80
DAC Gain Error
0dB, 1kHz input full scale signal
±0.1
dB
DAC Mute Attenuation
Mute
127
dB
DAC channel separation
–1dB, 1kHz signal, between left and right HP
out
92
dB
100mVpp, 1kHz signal applied to AVdd
70
dB
100mVpp, 217Hz signal applied to AVdd
75
dB
RL=16Ω, Output Stage on AVdd = 1.8V
THDN < 1%, Input CM=0.9V,
Output CM=0.9V, Channel Gain=2dB
13
RL=16 Ω Output Stage on LDOIN = 3.3V,
THDN < 1% Input CM=0.9V,
Output CM=1.65V, Channel Gain=8dB
47
(1) (2)
All zeros fed to DAC input, modulator in
excited state
0.5
–60dB 1kHz input full-scale signal, Word
Length = 20 bits, Power Tune = PTM_P4
DAC PSRR
Power Delivered
–70
dB
mW
Audio DAC – Stereo Single-Ended Headphone Output
Load = 16Ω (single-ended), 50pF,
Headphone Output on AVdd Supply,
Input & Output CM=0.75V; AVdd=1.5V,
DOSR = 128, MCLK=256* fs,
Channel Gain = –2dB, word length=20-bits;
Processing Block = PRB_P1,
Power Tune = PTM_P4
Device Setup
Full scale output voltage (0dB)
0.375
SNR
Signal-to-noise ratio, A-weighted (1)
(2)
DR
Dynamic range, A-weighted
THD+N
Total Harmonic Distortion plus Noise
(1) (2)
VRMS
All zeros fed to DAC input, modulator in
excited state
99
dB
-60dB 1 kHz input full-scale signal
98
dB
–3dB full-scale, 1-kHz input signal
–84
dB
Audio DAC – Mono Differential Headphone Output
(1)
(2)
8
Ratio of output level with 1-kHz full-scale sine wave input, to the output level with the inputs short circuited, measured A-weighted over a
20-Hz to 20-kHz bandwidth using an audio analyzer.
All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may
result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values
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Electrical Characteristics, Audio Outputs (continued)
At 25°C, AVdd, DVdd, IOVDD = 1.8V, LDO_in = 1.8V, AVdd LDO disabled, fs (Audio) = 48kHz, Cref = 10 mF on REF PIN,
PLL disabled unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Load = 32 Ω (differential), 50pF,
Headphone Output on LDOIN Supply
Input CM = 0.75V, Output CM=1.5V,
AVdd=1.8V, LDOIN=3.0V, DOSR = 128
MCLK=256* fs, Channel (headphone driver)
Gain = 5dB for full scale output signal,
word length=16-bits,
Processing Block = PRB_P1,
Power Tune = PTM_P3
Device Setup
Full scale output voltage (0dB)
SNR
Signal-to-noise ratio, A-weighted (1)
DR
Dynamic range, A-weighted
THD
Total Harmonic Distortion
(2)
(1) (2)
Power Delivered
1778
mVRMS
101
dB
–60dB 1kHz input full-scale signal
98
dB
–3dB full-scale, 1-kHz input signal
–82
dB
RL=32Ω, Output Stage on LDOIN = 3.3V,
THDN < 1%, Input CM=0.9V,
Output CM=1.65V, Channel Gain=8dB
125
mW
RL=32Ω Output Stage on LDOIN = 3.0V,
THDN < 1% Input CM=0.9V,
Output CM=1.5V, Channel Gain=8dB
103
mW
All zeros fed to DAC input, modulator in
excited state
Electrical Characteristics, LDO
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LOW DROPOUT REGULATOR (AVdd)
Output Voltage
LDOMode = 1, LDOin > 1.95V,
IO = 15mA
1.63
LDOMode = 0, LDOin > 2.0V,
IO = 15mA
1.68
LDOMode = 2, LDOin > 2.05V,
IO = 15mA
1.73
Output Voltage Accuracy
Load Regulation
Load current range 0 to 50mA
Line Regulation
Input Supply Range 1.9V to 3.6V
Decoupling Capacitor
V
±2
%
26
mV
3
mV
50
mA
1
mF
Bias Current
Electrical Characteristics, Misc.
At 25°C, AVdd, DVdd, IOVDD = 1.8V, LDO_in = 3.3V, AVdd LDO disabled, fs (Audio) = 48kHz, Cref = 10 mF on REF PIN,
PLL disabled unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
REFERENCE
Reference Voltage Settings
Reference Noise
CMMode = 0 (0.9V)
0.9
CMMode = 1 (0.75V)
0.75
CM=0.9V, A-weighted, 20Hz to 20kHz bandwidth,
Cref = 10mF
Decoupling Capacitor
1
1
Bias Current
V
mVRfcMS
10
mF
120
µA
miniDSP
Maximum miniDSP clock frequency - ADC
DVdd = 1.65V
55.3
MHz
Maximum miniDSP clock frequency - DAC
DVdd = 1.65V
55.3
MHz
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Electrical Characteristics, Misc. (continued)
At 25°C, AVdd, DVdd, IOVDD = 1.8V, LDO_in = 3.3V, AVdd LDO disabled, fs (Audio) = 48kHz, Cref = 10 mF on REF PIN,
PLL disabled unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Shutdown Current
Coarse AVdd supply turned off, LDO_select held at
ground, No external digital input is toggled
Device Setup
IDVdd
1.4
IAVdd
1
ILDOin
1
IIOVDD
1.6V
0.7 × IOVDD
V
IIH = 5mA, 1.2V ≤ IOVDD 1.6V
–0.3
V
IIL = 5mA, 1.2V ≤ IOVDD