TLV712xx
www.ti.com
SBVS150A – SEPTEMBER 2010 – REVISED JANUARY 2011
300-mA, Sub-Bandgap Output Voltage, Low-IQ, Low-Dropout Regulator
FEATURES
DESCRIPTION
• 2% Accuracy
• Low IQ: 35 mA
• Fixed-Output Voltage Combinations Possible
from 0.7 V to 1.15 V(1)
• High PSRR: 68 dB at 1 kHz
• Stable with Effective Capacitance of 0.1 mF(2)
• Thermal Shutdown and Overcurrent Protection
• Packages: SOT23-5, 1,5-mm × 1,5-mm SON-6
The TLV712xx series of low-dropout linear regulators
(LDOs) are low quiescent current devices with
excellent line and load transient performance. These
devices provide sub-bandgap output voltages; that is,
output voltages less than 1.2 V all the way down to
0.7 V. Therefore, these LDOs can be used to power
processors with operating voltages less than 1.2 V.
These LDOs are designed for power-sensitive
applications. A precision bandgap and error amplifier
provides overall 2% accuracy. Low output noise, very
high power-supply rejection ratio (PSRR), and
low-dropout voltage make this series of devices ideal
for a wide selection of battery-operated handheld
equipment. All device versions have thermal
shutdown and current limit for safety.
1
234
(1)
For output voltage of 1.2 V and higher, see the TLV702 family
of devices.
(2)
See the Input and Output Capacitor Requirements in the
Application Information section.
APPLICATIONS
•
•
•
•
•
•
•
Wireless Handsets
Smart Phones, PDAs
MP3 Players
ZigBee® Networks
Bluetooth® Devices
Li-Ion Operated Handheld Products
WLAN and Other PC Add-on Cards
1
5
The TLV712xxP series also provides an active
pull-down circuit to quickly discharge the outputs.
The TLV712xx series of LDO linear regulators are
available in SOT23-5 and 1,5-mm x 1,5-mm SON-6
packages.
TLV712xxDBV
SOT23-5
(TOP VIEW)
IN
Furthermore, these devices are stable with an
effective output capacitance of only 0.1 mF. This
feature enables the use of cost-effective capacitors
that have higher bias voltages and temperature
derating. The devices regulate to specified accuracy
with no output load.
OUT
VIN
IN
OUT
CIN
COUT
2
GND
3
EN
VOUT
1 mF
Ceramic
TLV712xx
On
N/C
4
Off
EN
GND
TLV712xxDSE
SON-6
(TOP VIEW)
Typical Application Circuit
(Fixed-Voltage Versions)
IN 1
6
EN
GND 2
5
N/C
OUT 3
4
N/C
1
2
3
4
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Bluetooth is a registered trademark of Bluetooth SIG.
ZigBee is a registered trademark of the ZigBee Alliance.
All other trademarks are the property of their respective owners.
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2011, Texas Instruments Incorporated
TLV712xx
SBVS150A – SEPTEMBER 2010 – REVISED JANUARY 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
(1)
(2)
(1)
(2)
PRODUCT
VOUT
TLV712xx(x)Pyyyz
XX(X) is the nominal output voltage. For output voltages with a resolution of 100 mV, two
digits are used in the ordering number; otherwise, three digits are used (for example, 09 =
0.9 V; 085 = 0.85 V).
P is optional; devices with P have an LDO regulator with an active output discharge.
YYY is the package designator.
Z is package quantity. Use "R" for reel (3000 pieces), and "T" for tape (250 pieces).
For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
Output voltages from 0.7 V to 1.15 V in 50-mV increments are available. Contact factory for details and availability.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
VALUE
Voltage (2)
Current (source)
MIN
MAX
IN
–0.3
+6.0
V
EN
–0.3
+6.0
V
OUT
–0.3
+5.0
V
OUT
Internally limited
Output short-circuit duration
Indefinite
Temperature
Operating junction, TJ
–55
+150
Storage, Tstg
–55
+150
°C
2
kV
500
V
Human body model (HBM) QSS 009-105 (JESD22-A114A)
Electrostatic Discharge Rating (3)
(1)
(2)
(3)
UNIT
Charged device model (CDM) QSS 009-147
(JESD22-C101B.01)
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.
All voltages are with respect to network ground terminal.
ESD testing is performed according to the respective JESD22 JEDEC standard.
DISSIPATION RATINGS (1)
(1)
2
PACKAGE
RqJA
TA < +25°C
TA = +70°C
TA = +85°C
DBV
200°C/W
500 mW
275 mW
200 mW
DSE
180°C/W
555 mW
305 mW
222 mW
For board details, see the Thermal Information section.
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TLV712xx
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SBVS150A – SEPTEMBER 2010 – REVISED JANUARY 2011
ELECTRICAL CHARACTERISTICS
At VIN = 2.0 V, IOUT = 10 mA, VEN = 0.9 V, COUT = 1.0 mF, and TJ = –40°C to +125°C, unless otherwise noted. Typical values
are at TJ = +25°C.
SPACE
PARAMETER
TEST CONDITIONS
TYP
VIN
Input voltage range
2.0
VOUT
DC output accuracy
–20
ΔVO/ΔVIN
Line regulation
2 V ≤ VIN ≤ 5.5 V,
ΔVO/ΔIOUT
Load regulation
0 mA ≤ IOUT ≤ 300 mA
Output current limit
VOUT = 0.9 × VOUT(NOM)
ICL
IGND
Ground pin current
320
IOUT = 0 mA
MAX
UNIT
5.5
V
6
+20
mV
1
5
mV
1
15
mV
500
860
mA
35
55
mA
IOUT = 300 mA
370
mA
VEN ≤ 0.4 V
400
nA
ISHDN
Ground pin current (shutdown)
VEN ≤ 0.4 V, 2.0 V ≤ VIN ≤ 4.5 V,
TJ = –40°C to +85°C
PSRR
Power-supply rejection ratio
f = 1 kHz
68
dB
VN
Output noise voltage
BW = 100 Hz to 100 kHz,
VOUT = 0.7 V
30
mVRMS
tSTR
Startup time (1)
IOUT = 300 mA
1
2
ms
Enable pin high (enabled)
0.9
VIN
VEN(LO)
Enable pin low (disabled)
0
0.4
UVLO
RDISCHARGE
Enable pin current
VIN = VEN = 5.5 V
Undervoltage lockout
Active pull-down resistance
(TLV712xxP only)
TSD
Thermal shutdown temperature
TJ
Operating junction temperature
mA
100
VEN(HI)
IEN
(1)
MIN
V
V
0.04
mA
VIN rising
1.9
V
VEN = 0 V
120
Ω
Shutdown, temperature increasing
+165
°C
Reset, temperature decreasing
+145
–40
°C
+125
°C
Startup time = time from EN assertion to 0.98 × VOUT(NOM).
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FUNCTIONAL BLOCK DIAGRAMS
IN
OUT
Current
Limit
Thermal
Shutdown
UVLO
EN
Bandgap
LOGIC
TLV712xx Series
GND
Figure 1. TLV712xx
IN
OUT
Current
Limit
Thermal
Shutdown
UVLO
EN
120W
Bandgap
LOGIC
TLV712xxP Series
GND
Figure 2. TLV712xxP
4
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TLV712xx
www.ti.com
SBVS150A – SEPTEMBER 2010 – REVISED JANUARY 2011
PIN CONFIGURATIONS
DBV PACKAGE
SOT23-5
(TOP VIEW)
IN
1
GND
2
EN
3
5
4
DSE PACKAGE(1)
SON-6
(TOP VIEW)
OUT
NC
(1)
IN 1
6
EN
GND 2
5
N/C
OUT 3
4
N/C
Preview package option.
PIN DESCRIPTIONS
NAME
SOT23-5
DBV
SON-6
DSE
DESCRIPTION
IN
1
1
Input pin. A small 1-mF ceramic capacitor is recommended from this pin to ground to assure
stability and good transient performance. See Input and Output Capacitor Requirements in the
Application Information section for more details.
GND
2
2
Ground pin
Enable pin. Driving EN over 0.9 V turns on the regulator. Driving EN below 0.4 V puts the
regulator into shutdown mode and reduces operating current to 1 mA, nominal.
For TLV712xxP, output voltage is discharged through an internal 120-Ω resistor when device
is shut down.
EN
3
6
NC
4
4, 5
OUT
5
3
No connection. This pin can be tied to ground to improve thermal dissipation.
Regulated output voltage pin. A small 1-mF ceramic capacitor is needed from this pin to
ground to assure stability. See Input and Output Capacitor Requirements in the Application
Information section for more details.
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TYPICAL CHARACTERISTICS
Over operating temperature range (TJ = –40°C to +125°C), VIN = 2.0 V, IOUT = 10 mA, VEN = VIN, COUT = 1.0 mF, unless
otherwise noted. Typical values are at TJ = +25°C.
LINE REGULATION
LOAD REGULATION
0.80
VOUT = 0.7 V
0.78
0.76
0.76
0.74
0.74
0.72
0.72
0.70
0.68
0.66
0.62
0.68
+125°C
+85°C
+25°C
-40°C
0.64
0.62
0.60
0.60
2
2.5
3
4
3.5
VIN (V)
4.5
5
0
5.5
50
100
150
200
250
300
IOUT (mA)
Figure 3.
Figure 4.
OUTPUT VOLTAGE vs TEMPERATURE
GROUND PIN CURRENT vs INPUT VOLTAGE
0.80
50
VOUT = 0.7 V
0.78
0.76
40
0.74
35
0.72
30
0.70
0.68
VOUT = 0.7 V
45
IGND (mA)
VOUT (V)
0.70
0.66
+125°C
+85°C
+25°C
-40°C
0.64
VOUT = 0.7 V
0.78
VOUT (V)
VOUT (V)
0.80
25
20
15
0.66
10mA
150mA
300mA
0.64
0.62
+125°C
+85°C
+25°C
-40°C
10
5
0
0.60
-40 -25 -10
5
20 35 50 65
Temperature (°C)
80
95
2
110 125
2.5
3
Figure 5.
3.5
4
VIN (V)
4..5
5
5.5
Figure 6.
GROUND PIN CURRENT vs LOAD
GROUND PIN CURRENT vs TEMPERATURE
350
50
VOUT = 0.7 V
VOUT = 0.7 V
45
300
35
200
30
IGND (mA)
IGND (mA)
40
250
150
100
+125°C
+85°C
+25°C
-40°C
50
0
20
15
10
5
0
0
50
100
150
IOUT (mA)
Figure 7.
6
25
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200
250
300
-40 -25 -10
5
20 35 50 65
Temperature (°C)
80
95
110 125
Figure 8.
Copyright © 2010–2011, Texas Instruments Incorporated
TLV712xx
www.ti.com
SBVS150A – SEPTEMBER 2010 – REVISED JANUARY 2011
TYPICAL CHARACTERISTICS (continued)
Over operating temperature range (TJ = –40°C to +125°C), VIN = 2.0 V, IOUT = 10 mA, VEN = VIN, COUT = 1.0 mF, unless
otherwise noted. Typical values are at TJ = +25°C.
SHUTDOWN CURRENT vs INPUT VOLTAGE
CURRENT LIMIT vs INPUT VOLTAGE
700
2.5
VOUT = 0.7 V
VOUT = 0.7 V
600
2
1.5
ILIM (mA)
ISHDN (mA)
500
1
300
200
+125°C
+85°C
+25°C
-40°C
0.5
400
0
0
2
2.5
3
3.5
4
VIN (V)
4.5
5
2
5.5
2.5
3
3.5
4
VIN (V)
4.5
5
5.5
Figure 9.
Figure 10.
POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY
OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY
Output Spectral Noise Density (mV/ÖHz)
100
IOUT = 10 mA
90
80
IOUT = 150 mA
70
PSRR (dB)
+85°C
+25°C
-40°C
100
60
50
40
30
20
10
0
10
100
1k
10 k
100 k
1M
10
VOUT = 0.7 V
CIN = COUT = 1 mF
1
0.1
0.01
0.001
10
10 M
100
10 k
100 k
1M
Figure 12.
LOAD TRANSIENT RESPONSE
LOAD TRANSIENT RESPONSE
15 mA
IOUT
0 mA
50 mA/div
Figure 11.
20 mV/div
10 mA/div
10 mV/div
1k
10 M
Frequency (Hz)
Frequency (Hz)
VOUT
70 mA
IOUT
0 mA
VOUT
VOUT = 0.7 V
tR = tF = 1 ms
VOUT = 0.7 V
tR = tF = 1 ms
20 ms/div
20 ms/div
Figure 13.
Figure 14.
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TYPICAL CHARACTERISTICS (continued)
Over operating temperature range (TJ = –40°C to +125°C), VIN = 2.0 V, IOUT = 10 mA, VEN = VIN, COUT = 1.0 mF, unless
otherwise noted. Typical values are at TJ = +25°C.
LINE TRANSIENT RESPONSE
Slew Rate = 1 V/ms
0 mA
1 V/div
300 mA
IOUT
2.9 V
2.3 V
VOUT = 0.7 V
tR = tF = 1 ms
VOUT
VOUT = 0.7 V
IOUT = 300 mA
1 ms/div
Figure 15.
Figure 16.
LINE TRANSIENT RESPONSE
VIN RAMP UP, RAMP DOWN RESPONSE
Slew Rate = 1 V/ms
VOUT = 0.7 V
IOUT = 300 mA
5.5 V
10 mV/div
2.0 V
VIN
VOUT = 0.7 V
IOUT = 1 mA
VIN
1 V/div
2 V/div
20 ms/div
VOUT
VOUT
1 ms/div
Figure 17.
8
VIN
VOUT
2 mV/div
50 mV/div
200 mA/div
LOAD TRANSIENT RESPONSE
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100 ms/div
Figure 18.
Copyright © 2010–2011, Texas Instruments Incorporated
TLV712xx
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SBVS150A – SEPTEMBER 2010 – REVISED JANUARY 2011
APPLICATION INFORMATION
GENERAL DESCRIPTION
The TLV712xx belongs to a new family of
next-generation value LDO regulators. These devices
offer sub-bandgap output voltages; that is, output
voltages from 1.2 V all the way down to 0.7 V. These
devices consume low quiescent current and deliver
excellent line and load transient performance. These
characteristics, combined with low noise and very
good PSRR with little (VIN – VOUT) headroom, make
this family of devices ideal for portable RF
applications. This family of regulators offers current
limit and thermal protection, and is specified from
–40°C to +125°C.
BOARD LAYOUT RECOMMENDATIONS TO
IMPROVE PSRR AND NOISE PERFORMANCE
Input and output capacitors should be placed as
close to the device pins as possible. To improve ac
performance such as PSRR, output noise, and
transient response, it is recommended that the board
be designed with separate ground planes for VIN and
VOUT, with the ground plane connected only at the
GND pin of the device. In addition, the ground
connection for the output capacitor should be
connected directly to the GND pin of the device. High
ESR capacitors may degrade PSRR performance.
INTERNAL CURRENT LIMIT
INPUT AND OUTPUT CAPACITOR
REQUIREMENTS
1.0-mF X5R- and X7R-type ceramic capacitors are
recommended because these capacitors have
minimal variation in value and equivalent series
resistance (ESR) over temperature.
However, the TLV712xx is designed to be stable with
an effective capacitance of 0.1 mF or larger at the
output. Thus, the device is stable with capacitors of
other dielectric types as well, as long as the effective
capacitance under operating bias voltage and
temperature is greater than 0.1 mF. This effective
capacitance refers to the capacitance that the LDO
sees under operating bias voltage and temperature
conditions; that is, the capacitance after taking both
bias voltage and temperature derating into
consideration. In addition to allowing the use of
lower-cost dielectrics, this capability of being stable
with 0.1-mF effective capacitance also enables the
use of smaller footprint capacitors that have higher
derating in size- and space-constrained applications.
NOTE: Using a 0.1-mF rated capacitor at the output
of the LDO does not ensure stability because the
effective capacitance under the specified operating
conditions would be less than 0.1 mF. Maximum ESR
should be less than 200 mΩ.
Although an input capacitor is not required for
stability, it is good analog design practice to connect
a 0.1-mF to 1.0-mF, low ESR capacitor across the IN
pin and GND pin of the regulator. This capacitor
counteracts reactive input sources and improves
transient response, noise rejection, and ripple
rejection. A higher-value capacitor may be necessary
if large, fast rise-time load transients are anticipated,
or if the device is not located close to the power
source. If source impedance is more than 2 Ω, a
0.1-mF input capacitor may be necessary to ensure
stability.
Copyright © 2010–2011, Texas Instruments Incorporated
The TLV712xx internal current limit helps to protect
the regulator during fault conditions. During current
limit, the output sources a fixed amount of current
that is largely independent of the output voltage. In
such a case, the output voltage is not regulated, and
is VOUT = ILIMIT × RLOAD. The PMOS pass transistor
dissipates (VIN – VOUT) × ILIMIT until thermal shutdown
is triggered and the device turns off. As the device
cools, it is turned on by the internal thermal shutdown
circuit. If the fault condition continues, the device
cycles between current limit and thermal shutdown.
See the Thermal Information section for more details.
The PMOS pass element in the TLV712xx has a
built-in body diode that conducts current when the
voltage at OUT exceeds the voltage at IN. This
current is not limited, so if extended reverse voltage
operation is anticipated, external limiting to 5% of the
rated output current is recommended.
SHUTDOWN
The enable pin (EN) is active high. The device is
enabled when voltage at EN pin goes above 0.9 V.
This relatively lower voltage value required to turn on
the LDO can also be used to power the device when
it is connected to a GPIO of a newer processor,
where the GPIO Logic 1 voltage level is lower than
that of traditional microcontrollers. The device is
turned off when the EN pin is held at less than 0.4 V.
When shutdown capability is not required, EN can be
connected to the IN pin.
The TLV712xxP version has internal active pull-down
circuitry that discharges the output with a time
constant of:
(120 · RL)
t=
· COUT
(120 + RL)
where:
•
•
RL = Load resistance
COUT = Output capacitor
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DROPOUT VOLTAGE
The TLV712xx uses a PMOS pass transistor to
achieve low dropout. For the complete output voltage
range of 0.7 V to 1.2 V, the device can supply 300
mA with a rated minimum input voltage of 2.0 V. Note
that the dropout voltage specification is not relevant
for the TLV712xx family of devices because the
output voltage range of the device does not exceed
1.2 V and the minimum input voltage for the device is
2.0 V.
TRANSIENT RESPONSE
As with any regulator, increasing the size of the
output capacitor reduces over-/undershoot magnitude
but increases the duration of the transient response.
UNDERVOLTAGE LOCKOUT (UVLO)
The TLV712xx uses an undervoltage lockout circuit to
keep the output shut off until internal circuitry is
operating properly.
THERMAL INFORMATION
Thermal protection disables the output when the
junction temperature rises to approximately +165°C,
allowing the device to cool. When the junction
temperature cools to approximately +145°C, the
output circuitry is again enabled. Depending on power
dissipation, thermal resistance, and ambient
temperature, the thermal protection circuit may cycle
on and off. This cycling limits the dissipation of the
regulator, protecting it from damage as a result of
overheating.
Any tendency to activate the thermal protection circuit
indicates excessive power dissipation or an
inadequate heatsink. For reliable operation, junction
temperature should be limited to +125°C maximum.
To estimate the margin of safety in a complete design
(including
heatsink),
increase
the
ambient
temperature until the thermal protection is triggered;
use worst-case loads and signal conditions.
The internal protection circuitry of the TLV712xx has
been designed to protect against overload conditions.
It was not intended to replace proper heatsinking.
Continuously running the TLV712xx into thermal
shutdown degrades device reliability.
POWER DISSIPATION
The ability to remove heat from the die is different for
each
package
type,
presenting
different
considerations in the printed circuit board (PCB)
layout. The PCB area around the device that is free
of other components moves the heat from the device
to the ambient air.
Thermal performance data for TLV712xx were
gathered using the TLV700 evaluation module (EVM),
a two-layer board with two ounces of copper per side.
The dimensions and layout for the SOT23-5 package
EVM are shown in Figure 19 and Figure 20.
Corresponding thermal performance data are given in
Table 1. Note that this board has provision for
soldering not only the SOT23-5 package on the
bottom layer, but also an SC-70 package on the top
layer. The dimensions and layout of the SON-6 (DSE)
package EVM are shown in Figure 21 and Figure 22.
Corresponding thermal performance data are given in
Table 1. Using heavier copper increases the
effectiveness in removing heat from the device. The
addition of plated through-holes to heat-dissipating
layers also improves heatsink effectiveness.
Power dissipation depends on input voltage and load
conditions. Power dissipation (PD) is equal to the
product of the output current and the voltage drop
across the output pass element, as shown in
Equation 2.
PD = (VIN - VOUT) ´ IOUT
(2)
PACKAGE MOUNTING
Solder pad footprint recommendations for the
TLV712xx are available from the Texas Instruments
web site at www.ti.com. The recommended land
pattern for the DBV and DSE packages are shown in
Figure 23 and Figure 24 respectively.
Table 1. EVM Dissipation Ratings
10
PACKAGE
RqJA
TA < +25°C
TA = +70°C
TA = +85°C
DBV
200°C/W
500 mW
275 mW
200 mW
DSE
180°C/W
555 mW
305 mW
222 mW
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18.16 mm
20.7 mm
Figure 19. SOT23-5 EVM Top Layer
18.16 mm
20.7 mm
Figure 20. SOT23-5EVM Bottom Layer
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17 mm
20.5 mm
Figure 21. DSE EVM Top Layer
17 mm
20.5 mm
Figure 22. DSE EVM Bottom Layer
12
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Example Board Layout
Stencil Openings
Based on Stencil Thickness
of 0,127 mm (.005 in)
(1)
All linear dimensions are in millimeters.
(2)
Customers should place a note on the circuit board fabrication drawing not to alter the center solder mask defined
pad.
(3)
Publication IPC-7351 is recommended for alternate designs.
(4)
Laser-cutting apertures with trapedzoidal walls and also rounding corners will offer better paste release. Customers
should contact their board assembly site for stencil design recommendations. Example stencil design based on a 50%
volumetric load solder paste. Refer to IPC-7525 for other stencil recommendations.
Figure 23. Recommended Land Pattern for DBV Package
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(1)
Publication IPC-7351 is recommended for alternate designs.
(2)
For more information, refer to TI application notes SCBA017 and SLUA271 (Quad Flatpack No-Lead Logic Packages
and QFN/SON PCB Attachment, respectively) for specific thermal information, via requirements, and additional
recommendations for board layout. These documents are available at the Texas Instruments web site
(http://www.ti.com) by searching for the literature number.
(3)
Laser-cutting apertures with trapedzoidal walls and also rounding corners will offer better paste release. Customers
should contact their board assembly site for stencil design recommendations. Refer to IPC-7525 for stencil design
considerations.
(4)
Customers should contact their board fabrication site for minimum solder mask tolerances between signal pads.
Figure 24. Recommended Land Pattern for DSE Package
14
Submit Documentation Feedback
Copyright © 2010–2011, Texas Instruments Incorporated
TLV712xx
www.ti.com
SBVS150A – SEPTEMBER 2010 – REVISED JANUARY 2011
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (September, 2010) to Revision A
Page
•
Added SON package description to Features list ................................................................................................................. 1
•
Added SON-6 package (preview) pin drawing to front page ................................................................................................ 1
•
Revised last paragraph of Description section to include information about DSE package ................................................. 1
•
Updated Ordering Information table ..................................................................................................................................... 2
•
Revised Dissipation Ratings table to show DSE package information ................................................................................. 2
•
Added DSE package pinout (preview) and pin configuration information ............................................................................ 5
•
Updated Package Mounting and Power Dissipation sections to reflect DSE package information ................................... 10
•
Added Figure 21 and Figure 22 .......................................................................................................................................... 12
•
Added Figure 24 ................................................................................................................................................................. 14
Copyright © 2010–2011, Texas Instruments Incorporated
Submit Documentation Feedback
15
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TLV71209DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
QVO
TLV71209DBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
QVO
TLV71210DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
SAR
TLV71210DBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
SAR
TLV71210DSER
ACTIVE
WSON
DSE
6
3000
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
RX
TLV71210DSET
ACTIVE
WSON
DSE
6
250
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
RX
TLV71211DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
SDK
TLV71211DBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
SDK
TLV71211DSER
ACTIVE
WSON
DSE
6
3000
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
YI
TLV71211DSET
ACTIVE
WSON
DSE
6
250
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
YI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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