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TLV713
SBVS195F – SEPTEMBER 2012 – REVISED AUGUST 2019
TLV713 Capacitor-Free, 150-mA, Low-Dropout Regulator
With Foldback Current Limit for Portable Devices
1 Features
3 Description
•
•
•
The TLV713 series of low-dropout (LDO) linear
regulators are low quiescent current LDOs with
excellent line and load transient performance and are
designed for power-sensitive applications. These
devices provide a typical accuracy of 1%.
1
•
•
•
•
•
•
•
Stable Operation With or Without Capacitors
Foldback Overcurrent Protection
Packages:
– 1-mm × 1-mm 4-Pin X2SON
– 5-Pin SOT-23
Very Low Dropout: 230 mV at 150 mA
Accuracy: 1%
Low IQ: 50 µA
Input Voltage Range: 1.4 V to 5.5 V
Available in Fixed-Output Voltages:
1 V to 3.3 V
High PSRR: 65 dB at 1 kHz
Active Output Discharge (P Version Only)
The TLV713 series of devices is designed to be
stable without an output capacitor. The removal of the
output capacitor allows for a very small solution size.
However, the TLV713 series is also stable with any
output capacitor if an output capacitor is used.
The TLV713 also provides inrush current control
during device power up and enabling. The TLV713
limits the input current to the defined current limit to
avoid large currents from flowing from the input
power source. This functionality is especially
important in battery-operated devices.
2 Applications
•
•
•
PDAs and Battery-Powered Portable Devices
MP3 Players and Other Hand-Held Products
WLAN and Other PC Add-On Cards
The TLV713 series is available in standard DQN and
DBV packages. The TLV713P provides an active
pulldown circuit to quickly discharge output loads.
Device Information(1)
DEVICE NAME
PACKAGE
TLV713
BODY SIZE
X2SON (4)
1.00 mm × 1.00 mm
SOT-23 (5)
2.90 mm × 1.60 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
space
space
space
Typical Application Circuit
Dropout Voltage vs Output Current
350
IN
VOUT = 1.8V
VOUT = 3.3V
OUT
TLV713
CIN
EN
Optional
ON
OFF
COUT
GND
Optional
Dropout Voltage (mV)
300
250
200
150
100
50
0
0
15
30
45
60
75
90 105
Output Current (mA)
120
135
150
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV713
SBVS195F – SEPTEMBER 2012 – REVISED AUGUST 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configurations and Functions .......................
Specifications.........................................................
1
1
1
2
5
6
6.1
6.2
6.3
6.4
6.5
6.6
6
6
6
6
7
8
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 12
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagrams .....................................
Feature Description.................................................
Device Functional Modes........................................
12
12
13
15
8
Application and Implementation ........................ 16
8.1 Application Information............................................ 16
8.2 Typical Application .................................................. 17
8.3 What to Do and What Not to Do ............................. 18
9 Power Supply Recommendations...................... 18
10 Layout................................................................... 19
10.1 Layout Guidelines ................................................. 19
10.2 Layout Examples................................................... 20
11 Device and Documentation Support ................. 21
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
21
21
21
21
22
22
22
12 Mechanical, Packaging, and Orderable
Information ........................................................... 22
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (March 2015) to Revision F
Page
•
Added last sentence to Undervoltage Lockout (UVLO) section ........................................................................................... 13
•
Added UVLO Circuit Limitation section ............................................................................................................................... 16
Changes from Revision D (July 2013) to Revision E
Page
•
Changed format to meet latest data sheet standards; added new sections, and moved existing sections........................... 1
•
Changed Features bullet about device package options ...................................................................................................... 1
•
Changed front-page figure ..................................................................................................................................................... 1
•
Changed Pin Configuration and Functions section; updated table format ............................................................................. 5
•
Changed Absolute Maximum Ratings table conditions .......................................................................................................... 6
•
Changed Output voltage range and Junction temperature range parameter maximum specifications in Absolute
Maximum Ratings table ......................................................................................................................................................... 6
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 6
•
Corrected DBV data in Thermal Information table ................................................................................................................. 6
•
Changed conditions of Electrical Characteristics table: changed VIN to VIN(nom); changed TA to TJ; corrected operating
temperature range ................................................................................................................................................................. 7
•
Changed TA to TJ and 85°C to 125°C throughout Electrical Characteristics table ................................................................ 7
•
Added test conditions for line regulation parameter .............................................................................................................. 7
•
Changed VDO parameter in Electrical Characteristics table: all rows changed ..................................................................... 7
•
Changed Vn parameter typical specification in Electrical Characteristics table .................................................................... 7
•
Deleted TJ parameter from Electrical Characteristics table ................................................................................................... 7
•
Added TJ condiiton to ILIM parameter in Electrical Characteristics table for clarification ....................................................... 7
•
Changed Typical Characteristics conditions........................................................................................................................... 8
•
Changed Figure 1 through Figure 11 in Typical Characteristics to show improved performance definition ......................... 8
2
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SBVS195F – SEPTEMBER 2012 – REVISED AUGUST 2019
•
Added new Figure 3 ............................................................................................................................................................... 8
•
Changed Figure 4................................................................................................................................................................... 8
•
Changed Figure 5................................................................................................................................................................... 8
•
Changed Figure 9 graph and figure title................................................................................................................................. 8
•
Added new Figure 10 ............................................................................................................................................................ 8
•
Changed Figure 12; corrected notation on axis titles to show units per graph division (units/div) ........................................ 8
•
Changed Figure 13; corrected notation on axis titles to show units per graph division (units/div) ........................................ 9
•
Changed Figure 14; corrected notation on axis titles to show units per graph division (units/div) ........................................ 9
•
Changed Figure 15; corrected notation on axis titles to show units per graph division (units/div) ........................................ 9
•
Changed Figure 17; corrected notation on axis titles to show units per graph division (units/div) ........................................ 9
•
Changed Figure 19; corrected notation on axis titles to show units per graph division (units/div) ...................................... 10
•
Changed Figure 21; corrected notation on axis titles to show units per graph division (units/div) ...................................... 10
•
Changed Figure 22; corrected notation on axis titles to show units per graph division (units/div) ...................................... 10
•
Changed Figure 23; corrected notation on axis titles to show units per graph division (units/div) ...................................... 10
•
Changed Shutdown section: clarified description ................................................................................................................ 13
•
Changed Foldback Current Limit section: adjusted flow and clarified description ............................................................... 14
•
Changed paragraph 1 of Thermal Protection ...................................................................................................................... 14
•
Changed Table 2 ................................................................................................................................................................. 17
•
Moved Ordering Information to Device Nomenclature section ............................................................................................ 21
Changes from Revision C (July 2013) to Revision D
Page
•
Changed document status from Mixed Status to Production Data ........................................................................................ 1
•
Deleted DPW package from document .................................................................................................................................. 1
•
Deleted reference to DPW package from last sentence of Description section..................................................................... 1
•
Deleted DPW pin out drawing from front-page graphic.......................................................................................................... 1
•
Deleted footnote for page 1 graphic ....................................................................................................................................... 1
•
Deleted DPW pinout drawing from Pin Configurations section .............................................................................................. 5
•
Deleted reference to DPW package from Pin Descriptions table........................................................................................... 5
•
Deleted DPW data from Thermal Information table ............................................................................................................... 6
•
Deleted footnote 3 of Ordering Information table ................................................................................................................. 21
Changes from Revision B (December 2012) to Revision C
Page
•
Changed last Features bullet.................................................................................................................................................. 1
•
Added Typical Application Circuit ........................................................................................................................................... 1
•
Changed last two rows of the VDO parameter in the Electrical Characteristics table ............................................................. 7
Changes from Revision A (October 2012) to Revision B
Page
•
Changed footnote for page 1 graphic..................................................................................................................................... 1
•
Added DBV data to Thermal Information table....................................................................................................................... 6
•
Changed footnote 3 of Ordering Information table ............................................................................................................... 21
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SBVS195F – SEPTEMBER 2012 – REVISED AUGUST 2019
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Changes from Original (September 2012) to Revision A
Page
•
Reordered Features bullets .................................................................................................................................................... 1
•
Changed dropout range in fourth Features bullet................................................................................................................... 1
•
Changed Package and Fixed-Output Voltage Features bullets ............................................................................................. 1
•
Added second and third paragraphs to Description section................................................................................................... 1
•
Updated DQN pin out drawing................................................................................................................................................ 1
•
Changed DQN pinout caption in Pin Configurations section.................................................................................................. 5
•
Changed 1.2 V to 0.9 V in description of EN pin in Pin Descriptions table............................................................................ 5
•
Changed DQN header row in Thermal Information table ....................................................................................................... 6
•
Changed VOUT maximum specification in Electrical Characteristics table.............................................................................. 7
•
Combined all VDO rows together in Electrical Characteristics table ....................................................................................... 7
•
Changed VDO specifications in Electrical Characteristics table .............................................................................................. 7
•
Changed ISHDN test conditions in Electrical Characteristics table ........................................................................................... 7
•
Changed Typical Characteristics conditions........................................................................................................................... 8
•
Added curves.......................................................................................................................................................................... 8
•
Changed junction temperature range in second paragraph of Overview section ................................................................ 12
•
Updated Figure 24................................................................................................................................................................ 12
•
Deleted third paragraph from Thermal Information section.................................................................................................. 14
•
Changed second paragraph of Input and Output Capacitor Considerations section ........................................................... 16
•
Deleted curve reference from Dropout Voltage section ....................................................................................................... 16
4
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SBVS195F – SEPTEMBER 2012 – REVISED AUGUST 2019
5 Pin Configurations and Functions
DQN Package
4-Pin X2SON
Top View
IN
EN
4
3
1
2
OUT
GND
DBV Package
5-Pin SOT-23
Top View
IN
1
GND
2
EN
3
5
OUT
4
NC
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
X2SON
SOT-23
EN
3
3
I
GND
2
2
—
IN
4
1
I
NC
—
4
—
No internal connection
OUT
1
5
O
Regulated output voltage pin. For best transient response, a small 1-μF ceramic capacitor is
recommended from this pin to ground. See the Input and Output Capacitor Considerations
section in the Feature Description for more details.
Thermal pad
—
—
The thermal pad is electrically connected to the GND node. Connect to the GND plane for
improved thermal performance.
Enable pin. Driving EN over 0.9 V turns on the regulator.
Driving EN below 0.4 V puts the regulator into shutdown mode.
Ground pin
Input pin. A small capacitor is recommended from this pin to ground. See the Input and
Output Capacitor Considerations section in the Feature Description for more details.
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SBVS195F – SEPTEMBER 2012 – REVISED AUGUST 2019
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating junction temperature range (TJ = 25°C), unless otherwise noted. All voltages are with respect to GND. (1)
Voltage
Current
MIN
MAX
Input, VIN
–0.3
6
Enable, VEN
–0.3
VIN + 0.3
Output, VOUT
–0.3
3.6
Maximum output, IOUT(max)
Temperature
(1)
V
Internally limited
Output short-circuit duration
Total power dissipation
UNIT
Indefinite
Continuous, PD(tot)
See Thermal Information
Storage, Tstg
–55
150
°C
Junction, TJ
–55
125
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins (2)
±500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted).
MIN
NOM
MAX
5.5
UNIT
VIN
Input voltage
1.4
V
VEN
Enable range
0
VIN
V
IOUT
Output current
0
150
mA
CIN
Input capacitor
0
1
COUT
Output capacitor
0
0.1
TJ
Operating junction temperature range
µF
–40
100
µF
125
°C
6.4 Thermal Information
TLV713, TLV713P
THERMAL METRIC (1)
DQN (X2SON)
DBV (SOT23)
4 PINS
5 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
255.8
249
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
159.3
172.7
°C/W
RθJB
Junction-to-board thermal resistance
208.2
76.7
°C/W
ψJT
Junction-to-top characterization parameter
16.2
49.7
°C/W
ψJB
Junction-to-board characterization parameter
208.1
75.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
148.6
n/a
°C/W
(1)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SBVS195F – SEPTEMBER 2012 – REVISED AUGUST 2019
6.5 Electrical Characteristics
Over operating temperature range (TJ = –40°C to 125°C), VIN(nom) = VOUT(nom) + 0.5 V or VIN(nom) = 2 V (whichever is greater),
IOUT = 1 mA, VEN = VIN, and COUT = 0.47 µF, unless otherwise noted. Typical values are at TJ = 25°C.
PARAMETER
VIN
Input voltage range
VOUT
Output voltage
range
DC output accuracy
TEST CONDITIONS
TYP
MAX
UNIT
1.4
5.5
V
1
3.3
V
VOUT ≥ 1.8 V, TJ = 25°C
–1%
1%
VOUT < 1.8 V, TJ = 25°C
–20
20
VOUT ≥ 1.2 V, –40°C ≤ TJ ≤ 125°C
–1.5%
1.5%
VOUT < 1.2 V, –40°C ≤ TJ ≤ 125°C
–50
50
mV
5
mV
10
30
mV
1 V ≤ VOUT < 1.8 V, IOUT = 150 mA
600
900
VOUT = 1.1 V, IOUT = 100 mA
470
600
Line regulation
Max {VOUT(nom) + 0.5 V, VIN = 2.0 V} ≤ VIN ≤ 5.5 V
ΔVOUT(ΔIOUT)
Load regulation
0 mA ≤ IOUT ≤ 150 mA
VOUT = 0.98 × VOUT(nom),
TJ = –40°C to 85°C
Dropout voltage
VOUT = 0.98 × VOUT(nom),
TJ = –40°C to 125°C
mV
1
ΔVOUT(ΔVIN)
VDO
MIN
1.8 V ≤ VOUT < 2.1 V, IOUT = 30 mA
70
1.8 V ≤ VOUT < 2.1 V, IOUT = 150 mA
350
2.1 V ≤ VOUT < 2.5 V, IOUT = 30 mA
90
2.1 V ≤ VOUT < 2.5 V, IOUT = 150 mA
290
575
481
2.5 V ≤ VOUT < 3 V, IOUT = 30 mA
50
2.5 V ≤ VOUT < 3 V, IOUT = 150 mA
246
3 V ≤ VOUT < 3.6 V, IOUT = 30 mA
46
3 V ≤ VOUT < 3.6 V, IOUT = 150 mA
230
420
1 V ≤ VOUT < 1.8 V, IOUT = 150 mA
600
1020
VOUT = 1.1 V, IOUT = 100 mA
470
720
1.8 V ≤ VOUT < 2.1 V, IOUT = 150 mA
350
695
2.1 V ≤ VOUT < 2.5 V, IOUT = 150 mA
290
601
2.5 V ≤ VOUT < 3 V, IOUT = 150 mA
246
565
3 V ≤ VOUT < 3.6 V, IOUT = 150 mA
230
540
445
mV
IGND
Ground pin current
IOUT = 0 mA
50
75
µA
ISHUTDOWN
Shutdown current
VEN ≤ 0.4 V, 2.0 V ≤ VIN ≤ 5.5 V, TJ = 25°C
0.1
1
µA
PSRR
Power-supply
rejection ratio
VIN = 3.3 V,
VOUT = 2.8 V,
IOUT = 30 mA
f = 100 Hz
70
f = 10 kHz
55
f = 1 MHz
55
dB
Vn
Output noise voltage BW = 100 Hz to 100 kHz, VIN = 2.3 V, VOUT = 1.8 V, IOUT = 10 mA
tSTR
Start-up time (1)
VHI
Enable high
(enabled)
VLO
Enable low
(disabled)
IEN
EN pin current
EN = 5.5 V
0.01
µA
RPULLDOWN
Pulldown resistor
(TLV713P only)
VIN = 4 V
120
Ω
ILIM
Output current limit
ISC
TSD
(1)
Short-circuit current
Thermal shutdown
COUT = 1.0 μF, IOUT = 150 mA
µVRMS
µs
0.9
VIN
V
0
0.4
V
VIN = 3.8 V, VOUT = 3.3 V, TJ = –40 to 85°C
180
VIN = 2.25 V, VOUT = 1.8 V, TJ = –40 to 85°C
180
VIN = 2.0 V, VOUT = 1.2 V, TJ = –40 to 85°C
180
VOUT = 0 V
73
100
mA
40
Shutdown, temperature increasing
158
Reset, temperature decreasing
140
mA
°C
Start-up time is the time from EN assertion to (0.98 × VOUT(nom)).
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6.6 Typical Characteristics
Over operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT =
10 mA, VEN = VIN, COUT = 1 µF, and VOUT(nom) = 1.8 V, unless otherwise noted. Typical values are at TJ = 25°C.
1.8
1.802
Output Voltage (V)
1.8
1.799
1.798
1.797
1.796
TJ = -40qC
TJ = 0qC
TJ = 25qC
TJ = 85qC
TJ = 125qC
1.798
Output Voltage (V)
TJ = -40qC
TJ = 0qC
TJ = 25qC
TJ = 85qC
TJ = 125qC
1.801
1.796
1.794
1.792
1.79
1.795
1.788
1.794
1.786
1.793
2
2.5
3
3.5
4
Input Voltage (V)
4.5
5
0
5.5
Figure 1. 1.8-V Line Regulation vs
VIN and Temperature
40
60
80
100
Output Current (mA)
120
140
160
Figure 2. 1.8-V Load Regulation vs
IOUT and Temperature
1.798
500
TJ = -40qC
TJ = 0qC
TJ = 25qC
TJ = 85qC
TJ = 125qC
1.7975
400
Dropout Voltage (mV)
1.797
Output Voltage (V)
20
1.7965
1.796
1.7955
1.795
300
200
100
1.7945
1.794
-40
0
-20
0
20
40
60
80
Temperature (qC)
100
120
140
0
Figure 3. 1.8-V Output Voltage Over Temperature
300
Ground Pin Current (PA)
Dropout Voltage (mV)
350
250
200
150
100
50
0
0
25
50
75
100
Output Current (mA)
125
150
65
62.5
60
57.5
55
52.5
50
47.5
45
42.5
40
37.5
35
32.5
30
125
150
TJ = -40qC
TJ = 0qC
TJ = 25qC
TJ = 85qC
TJ = 125qC
2
Figure 5. 3.3-V Dropout Voltage vs
IOUT and Temperature
8
50
75
100
Output Current (mA)
Figure 4. 1.8-V Dropout Voltage vs
IOUT and Temperature
400
TJ = -40qC
TJ = 0qC
TJ = 25qC
TJ = 85qC
TJ = 125qC
25
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2.5
3
3.5
4
Input Voltage (V)
4.5
5
5.5
Figure 6. Ground Pin Current vs
VIN and Temperature
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Typical Characteristics (continued)
80
500
75
300
200
70
65
60
55
TJ = -40qC
TJ = 0qC
TJ = 25qC
TJ = 85qC
TJ = 125qC
50
45
40
Ground Pin Current (nA)
Ground Pin Current (PA)
Over operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT =
10 mA, VEN = VIN, COUT = 1 µF, and VOUT(nom) = 1.8 V, unless otherwise noted. Typical values are at TJ = 25°C.
100
50
30
20
10
TJ = -40qC
TJ = 0qC
TJ = 25qC
TJ = 85qC
TJ = 125qC
5
3
2
1
35
0
20
40
60
80
100
Output Current (mA)
120
140
2
160
Figure 7. Ground Pin Current vs
IOUT and Temperature
90
80
60
PSRR (dB)
PSRR (dB)
70
50
40
30
COUT = 0 PF, IOUT = 150 mA
COUT = 0 PF, IOUT = 30 mA
COUT = 1 PF, IOUT = 150 mA
COUT = 1 PF, IOUT = 30 mA
10
0
-10
1E+1
1E+2
1E+3
1E+4
1E+5
Frequency (Hz)
1E+6
1E+7
Figure 9. Power-Supply Rejection Ratio Over COUT
Voltage Noise (PV/—Hz)
5
3
2
3
3.5
4
Input Voltage (V)
4.5
5
5.5
1E+6
1E+7
Figure 8. Shutdown Current vs
VIN and Temperature
100
20
2.5
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
1E+1
IOUT = 10 mA
IOUT = 50 mA
IOUT = 100 mA
IOUT = 150 mA
1E+2
1E+3
1E+4
1E+5
Frequency (Hz)
Figure 10. Power-Supply Rejection Ratio Over IOUT
VIN
COUT = 0 PF
COUT = 1 PF
Channel 1
1 V/div
1
0.5
0.3
0.2
0.1
Channel 3
200 mV/div
0.05
0.03
0.02
VIN = 3 V to 4 V
VOUT = 1.8 V
IOUT = 0 mA
CIN = COUT = 0 mF
VOUT
0.01
0.005
1E+1
Time (200 ms/div)
1E+2
1E+3
1E+4
1E+5
Frequency (Hz)
1E+6
G016
1E+7
Figure 11. Output Spectral Noise Density
Figure 12. Line Transient
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Typical Characteristics (continued)
Over operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT =
10 mA, VEN = VIN, COUT = 1 µF, and VOUT(nom) = 1.8 V, unless otherwise noted. Typical values are at TJ = 25°C.
VIN = 5 V, VOUT = 1.8 V
CIN = COUT = 1 mF
VIN
Channel 1
1 V/div
Channel 3
0.5 V/div
Channel 1
20 mV/div
VOUT
VIN = 3 V to 4 V
VOUT = 1.8 V
IOUT = 150 mA
CIN = COUT = 0 mF
VOUT
IOUT
Channel 4
20 mA/div
Time (200 ms/div)
Time (200 ms/div)
G017
G012
Figure 13. Line Transient
Figure 14. 0-mA to 20-mA Load Transient
3.5
VIN = 5 V, VOUT = 1.8 V
CIN = COUT = 0 mF
3
Output Voltage (V)
Channel 3
200 mV/div
VOUT
IOUT
Channel 4
20 mA/div
2.5
2
1.5
1
0.5
TLV71333P
0
Time (200 ms/div)
0
50
G015
Figure 15. 0-mA to 20-mA Load Transient
300
G010
2
Output Voltage (V)
1.75
VOUT
IOUT
Channel 4
50 mA/div
250
Figure 16. 3.3-V Output Voltage vs Output Current
(Foldback Current Limit)
VIN = 5 V, VOUT = 1.8 V
CIN = COUT = 0 mF
Channel 3
0.5 V/div
100
150
200
Output Current (mA)
1.5
1.25
1
0.75
0.5
0.25
TLV71318P
0
Time (200 ms/div)
0
G013
Figure 17. 0-mA to 100-mA Load Transient
10
50
100
150
200
250
Output Current (mA)
300
350
G011
Figure 18. 1.8-V Output Voltage vs Output Current
(Foldback Current Limit)
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Typical Characteristics (continued)
Over operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT =
10 mA, VEN = VIN, COUT = 1 µF, and VOUT(nom) = 1.8 V, unless otherwise noted. Typical values are at TJ = 25°C.
4
VIN = 5 V, VOUT = 1.8 V
CIN = COUT = 0 mF
Channel 3
200 mV/div
IOUT = 150 mA
TPS71318P
VIN
VOUT
3
Voltage (V)
VOUT
2
IOUT
Channel 4
50 mA/div
1
0
Time (200 ms/div)
0
0.5
1
Time (s)
G014
Figure 19. 10-mA to 150-mA Load Transient
Channel 1
2 V/div
1.5
2
G020
Figure 20. VIN Power-Up and Power-Down
Channel 1
100 mV/div
VIN
VIN
EN
Channel 2
2 V/div
Channel 3
1 V/div
Channel 2
1 V/div
Channel 3
1 V/div
VOUT
VIN = 3 V
VOUT = 1.8 V
CIN = COUT = 0 mF
IOUT = 150 mA
TLV71318P
IOUT
Channel 4
50 mA/div
EN
VOUT
Channel 4
50 mA/div
ILOAD
Time (50 ms/div)
VIN = 2.3 V, VOUT = 1.8 V
CIN = 1 mF, COUT = 10 mF
IOUT = 90 mA
TLV71318P, From Design
Time (100 ms/div)
G021
G022
Figure 21. Start-up With EN
Figure 22. Start-up With EN
Channel 1
2 V/div
Channel 2
2 V/div
VIN
EN
VOUT
Channel 3
1 V/div
Channel 4
100 mA/div
VIN = 3 V
VOUT = 1.8 V
CIN = COUT = 1 mF
TPS71318P
No Load
IOUT
Time (50 ms/div)
G019
Figure 23. Shutdown Response With Enable
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7 Detailed Description
7.1 Overview
These devices belong to a new family of next-generation value low-dropout (LDO) regulators. These devices
consume low quiescent current and deliver excellent line and load transient performance. These characteristics,
combined with low noise, very good PSRR with little (VIN – VOUT) headroom, make this family of devices ideal for
RF portable applications.
This family of regulators offers current limit and thermal protection. Device operating junction temperature is
–40°C to 125°C.
7.2 Functional Block Diagrams
IN
OUT
Current
Limit
Thermal
Shutdown
UVLO
EN
Bandgap
Logic
TLV713
GND
Figure 24. TLV713 Block Diagram
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Functional Block Diagrams (continued)
IN
OUT
Current
Limit
Thermal
Shutdown
UVLO
EN
120 W
Bandgap
Logic
TLV713P
GND
Figure 25. TLV713P Block Diagram
7.3 Feature Description
7.3.1 Undervoltage Lockout (UVLO)
The TLV713 uses a UVLO circuit that disables the output until the input voltage is greater than the rising UVLO
voltage. This circuit ensures that the device does not exhibit any unpredictable behavior when the supply voltage
is lower than the operational range of the internal circuitry, VIN(min). During UVLO disable, the output of the
TLV713P version is connected to ground with a 120-Ω pulldown resistor. Fast rising and falling voltage changes
near UVLO levels require at least a 1-ms delay before the rising and falling edges; see the UVLO Circuit
Limitation section.
7.3.2 Shutdown
The enable pin (EN) is active high. Enable the device by forcing the EN pin to exceed VEN(high) (0.9 V, minimum).
Turn off the device by forcing the EN pin to drop below 0.4 V. If shutdown capability is not required, connect EN
to IN.
The TLV713P has an internal pulldown MOSFET that connects a 120-Ω resistor to ground when the device is
disabled. The discharge time after disabling depends on the output capacitance (COUT) and the load resistance
(RL) in parallel with the 120-Ω pulldown resistor. The time constant is calculated in Equation 1.
t=
120 · RL
120 + RL
· COUT
(1)
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Feature Description (continued)
7.3.3 Foldback Current Limit
The TLV713 has an internal foldback current limit that helps protect the regulator during fault conditions. The
current supplied by the device is gradually reducedwhile the output voltage decreases. When the output is
shorted, the LDO supplies a typical current of 40 mA. Output voltage is not regulated when the device is in
current limit, and is calculated by Equation 2:
VOUT = ILIMIT × RLOAD
(2)
The PMOS pass transistor dissipates [(VIN – VOUT) × ILIMIT] until thermal shutdown is triggered and the device
turns off. The device is turned on by the internal thermal shutdown circuit during cool down. If the fault condition
continues, the device cycles between current limit and thermal shutdown. See the Thermal Information section
for more details.
The TLV713 PMOS pass element has a built-in body diode that conducts current when the voltage at OUT
exceeds the voltage at IN. This current is not limited, so if extended reverse voltage operation is anticipated,
external limiting to 5% of the rated output current is recommended.
7.3.4 Thermal Protection
Thermal protection disables the output when the junction temperature rises to approximately 158°C, allowing the
device to cool. When the junction temperature cools to approximately 140°C, the output circuitry is again
enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection
circuit may cycle on and off. This cycling limits regulator dissipation, protecting the device from damage as a
result of overheating.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heatsink. For reliable operation, junction temperature must be limited to 125°C maximum. To estimate the margin
of safety in a complete design (including heatsink), increase the ambient temperature until the thermal protection
is triggered; use worst-case loads and signal conditions.
The TLV713 internal protection circuitry is designed to protect against overload conditions. This circuitry is not
intended to replace proper heatsinking. Continuously running the TLV713 into thermal shutdown degrades device
reliability.
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7.4 Device Functional Modes
7.4.1 Normal Operation
The device regulates to the nominal output voltage under the following conditions:
• The input voltage is at least as high as VIN(min).
• The input voltage is greater than the nominal output voltage added to the dropout voltage.
• The enable voltage has previously exceeded the enable rising threshold voltage and has not decreased
below the enable falling threshold.
• The output current is less than the current limit.
• The device junction temperature is less than the maximum specified junction temperature.
7.4.2 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this mode of operation, the
output voltage is the same as the input voltage minus the dropout voltage. The transient performance of the
device is significantly degraded because the pass device is in the linear region and no longer controls the current
through the LDO. Line or load transients in dropout can result in large output voltage deviations.
7.4.3 Disabled
The device is disabled under the following conditions:
• The enable voltage is less than the enable falling threshold voltage or has not yet exceeded the enable rising
threshold.
• The device junction temperature is greater than the thermal shutdown temperature.
Table 1 shows the conditions that lead to the different modes of operation.
Table 1. Device Functional Mode Comparison
PARAMETER
OPERATING MODE
VIN
VEN
IOUT
TJ
Normal mode
VIN > VOUT(nom) + VDO and
VIN > VIN(min)
VEN > VEN(high)
IOUT < ILIM
TJ < 125°C
Dropout mode
VIN(min) < VIN < VOUT(nom) + VDO
VEN > VEN(high)
—
TJ < 125°C
—
VEN < VEN(low)
—
TJ > 158°C
Disabled mode
(any true condition disables the
device)
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Input and Output Capacitor Considerations
The TLV713 uses an advanced internal control loop to obtain stable operation both with and without the use of
input or output capacitors. The TLV713 dynamic performance is improved with the use of an output capacitor. An
output capacitance of 0.1 μF or larger generally provides good dynamic response. X5R- and X7R-type ceramic
capacitors are recommended because these capacitors have minimal variation in value and equivalent series
resistance (ESR) over temperature.
Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1-µF to
1-µF capacitor from IN to GND. This capacitor counteracts reactive input sources and improves transient
response, input ripple, and PSRR. An input capacitor is recommended if the source impedance is more than
0.5 Ω. A higher-value capacitor may be necessary if large, fast, rise-time load transients are anticipated or if the
device is located several inches from the input power source.
8.1.2 Dropout Voltage
The TLV713 uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout
voltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-output resistance is the
RDS(on) of the PMOS pass element. VDO scales approximately with output current because the PMOS device
behaves like a resistor in dropout. As with any linear regulator, PSRR and transient response are degraded as
(VIN – VOUT) approaches dropout.
8.1.3 Transient Response
As with any regulator, increasing the size of the output capacitor reduces over- and undershoot magnitude but
increases the duration of the transient response.
8.1.4 UVLO Circuit Limitation
The TLV713 UVLO circuit is sensitive to fast rising and falling input voltage changes that result in the device
turning on and off. When the input voltage drops below the minimum VIN and the device is turned off, provide a
minimum 1-ms delay before turning on the device again. This minimum 1-ms delay allows the internal circuit to
reset to the correct state. If the TLV713 is turned on again before the delay elapses, an EN toggle is required for
the internal circuit to reset to the correct state.
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8.2 Typical Application
Several versions of the TPS713 are ideal for powering the MSP430 microcontroller.
Figure 26 shows a diagram of the TLV713 powering an MSP430 microcontroller. Table 2 shows potential
applications of some voltage versions.
VO
(1.8 V to 3.6 V)
VI
IN
0.1 mF
MSP430
OUT
0.1 mF
EN
GND
Figure 26. TLV713 Powering a Microcontroller
Table 2. Typical MSP430 Applications
DEVICE
VOUT (Typ)
TLV71318P
1.8 V
Allows for lowest power consumption with many MSP430s
APPLICATION
TLV71325P
2.5 V
2.2-V supply required by many MSP430s for flash programming and erasing
8.2.1 Design Requirements
Table 3 lists the design requirements.
Table 3. Design Parameters
PARAMETER
DESIGN REQUIREMENT
Input voltage
4.2 V to 3 V (Lithium Ion battery)
Output voltage
1.8 V, ±1%
DC output current
10 mA
Peak output current
75 mA
Maximum ambient temperature
65°C
8.2.2 Detailed Design Procedure
An input capacitor is not required for this design because of the low impedance connection directly to the battery.
No output capacitor allows for the minimal possible inrush current during start-up, ensuring the 180-mA
maximum input current limit is not exceeded.
Verify that the maximum junction temperature is not exceeded by referring to Figure 30.
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8.2.3 Application Curves
4
100
VOUT = 1.8 V
IOUT = 10 mA
90
Voltage ( µV / Hz )
80
PSRR (dB)
70
60
50
40
30
20
10
0
-10
1E+1
COUT = 0 PF, IOUT = 150 mA
COUT = 0 PF, IOUT = 30 mA
COUT = 1 PF, IOUT = 150 mA
COUT = 1 PF, IOUT = 30 mA
1E+2
3
2
1
0
1E+3
1E+4
1E+5
Frequency (Hz)
1E+6
10
100
1k
Frequency (Hz)
1E+7
Figure 27. Power-Supply Rejection Ratio vs Frequency
10k
100k
G009
Figure 28. Output Spectral Noise Density
4
IOUT = 150 mA
TPS71318P
VIN
VOUT
Voltage (V)
3
2
1
0
0
0.5
1
Time (s)
1.5
2
G020
Figure 29. VIN Power Up and Power Down
8.3 What to Do and What Not to Do
Place at least one 0.1-µF ceramic capacitor as close as possible to the OUT pin of the regulator for best
transient performance.
Place at least one 1-µF capacitor as close as possible to the IN pin for best transient performance.
Do not place the output capacitor more than 10 mm away from the regulator.
Do not exceed the absolute maximum ratings.
Do not continuously operate the device in current limit or near thermal shutdown.
9 Power Supply Recommendations
These devices are designed to operate from an input voltage supply range from 1.4 V to 5.5 V. The input voltage
range must provide adequate headroom for the device to have a regulated output. This input supply must be
well-regulated and stable. If the input supply is noisy, additional input capacitors with low ESR can help improve
the output noise performance.
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10 Layout
10.1 Layout Guidelines
10.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance
Input and output capacitors must be placed as close to the device pins as possible. To improve AC performance
(such as PSRR, output noise, and transient response), TI recommends that the board be designed with separate
ground planes for VIN and VOUT, with the ground plane connected only at the device GND pin. In addition, the
output capacitor ground connection must be connected directly to the device GND pin. High-ESR capacitors may
degrade PSRR performance.
10.1.2 Power Dissipation
The ability to remove heat from the die is different for each package type, presenting different considerations in
the printed-circuit-board (PCB) layout. The PCB area around the device that is free of other components moves
the heat from the device to the ambient air. Performance data for JEDEC low- and high-K boards are given in
Thermal Information. Using heavier copper increases the effectiveness in removing heat from the device. The
addition of plated through-holes to heat-dissipating layers also improves the heatsink effectiveness.
Power dissipation depends on input voltage and load conditions. Power dissipation (PD) can be approximated by
the product of the output current times the voltage drop across the output pass element (VIN to VOUT), as shown
in Equation 3.
PD = (VIN – VOUT) × IOUT
(3)
Figure 30 shows the maximum ambient temperature versus the power dissipation of the TLV713. This figure
assumes the device is soldered on a JEDEC standard, high-K layout with no airflow over the board. Actual board
thermal impedances vary widely. If the application requires high power dissipation, having a thorough
understanding of the board temperature and thermal impedances is helpful to ensure the TLV713 does not
operate above a junction temperature of 125°C.
Maximum Ambient Temperature (°C)
130
TLV713 DQN, High-K Layout
TLV713 DBV, High-K Layout
120
110
100
90
80
70
60
50
0
0.05
0.1
0.15
0.2
0.25
Power Dissipation (W)
0.3
0.35
Figure 30. Maximum Ambient Temperature vs Device Power Dissipation
Estimating the junction temperature can be done by using the thermal metrics ΨJT and ΨJB, shown in the Thermal
Information table. These metrics are a more accurate representation of the heat transfer characteristics of the die
and the package than RθJA. The junction temperature can be estimated with Equation 4.
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Layout Guidelines (continued)
YJT: TJ = TT + YJT · PD
YJB: TJ = TB + YJB · PD
where
•
•
•
PD is the power dissipation shown by Equation 3,
TT is the temperature at the center-top of the IC package,
TB is the PCB temperature measured 1 mm away from the IC package on the PCB surface.
(4)
NOTE
Both TT and TB can be measured on actual application boards using a thermo-gun (an
infrared thermometer).
For more information about measuring TT and TB, see the Using New Thermal Metrics application note, available
for download at www.ti.com.
10.2 Layout Examples
VOUT
OUT
TLV713
VIN
IN
COUT(1)
CIN(1)
GND
EN
GND PLANE
Represents via used for
application-specific connections
(1)
Not required.
Figure 31. X2SON Layout Example
VOUT
VIN
IN
CIN
OUT
COUT
GND
EN
NC
GND PLANE
Represents via used for
application-specific connections
(1)
Not required.
Figure 32. SOT-23 Layout Example
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Evaluation Modules
Three evaluation modules (EVMs) are available to assist in the initial circuit performance evaluation using the
TLV713:
• TLV71312PEVM-171
• TLV71318PEVM-171
• TLV71333PEVM-171
These EVMs can be requested at the Texas Instruments website through the device product folders or
purchased directly from the TI eStore.
11.1.1.2 Spice Models
Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of
analog circuits and systems. A SPICE model for the TLV713 is available through the product folders under Tools
& Software.
11.1.2 Device Nomenclature
Table 4. Ordering Information (1) (2)
(1)
(2)
PRODUCT
VO
TLV713xx(x)Pyyyz
XX(X) is the nominal output voltage. For output voltages with a resolution of 100 mV, two digits are used
in the ordering number; otherwise, three digits are used (for example, 28 = 2.8 V; 475 = 4.75 V).
P is optional; devices with P have an LDO regulator with an active output discharge.
YYY is the package designator.
Z is the package quantity. R is for reel (3000 pieces), T is for tape (250 pieces).
For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder on www.ti.com.
Output voltages from 1.0 V to 3.3 V in 50-mV increments are available. Contact the factory for details and availability.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Using New Thermal Metrics application report
• Texas Instruments, TLV713xxEVM-171 User's Guide user's guide
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
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11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TLV71310PDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
VUQI
Samples
TLV71310PDBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
VUQI
Samples
TLV71310PDQNR
ACTIVE
X2SON
DQN
4
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
ET
Samples
TLV71310PDQNT
ACTIVE
X2SON
DQN
4
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
ET
Samples
TLV71311PDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
VUPI
Samples
TLV71311PDBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
VUPI
Samples
TLV71312PDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
VUEI
Samples
TLV71312PDBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
VUEI
Samples
TLV71312PDQNR
ACTIVE
X2SON
DQN
4
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AF
Samples
TLV71312PDQNT
ACTIVE
X2SON
DQN
4
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AF
Samples
TLV71315PDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
VUGI
Samples
TLV71315PDBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
VUGI
Samples
TLV71315PDQNR
ACTIVE
X2SON
DQN
4
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AY
Samples
TLV71315PDQNT
ACTIVE
X2SON
DQN
4
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AY
Samples
TLV713185PDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
VUII
Samples
TLV713185PDBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
VUII
Samples
TLV713185PDQNR
ACTIVE
X2SON
DQN
4
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
A1
Samples
TLV713185PDQNT
ACTIVE
X2SON
DQN
4
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
A1
Samples
TLV71318PDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
VUDI
Samples
TLV71318PDBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
VUDI
Samples
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
6-Dec-2022
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TLV71318PDQNR
ACTIVE
X2SON
DQN
4
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AW
Samples
TLV71318PDQNT
ACTIVE
X2SON
DQN
4
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AW
Samples
TLV71320DQNR
ACTIVE
X2SON
DQN
4
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
B2
Samples
TLV71320DQNT
ACTIVE
X2SON
DQN
4
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
B2
Samples
TLV71325PDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
VUJI
Samples
TLV71325PDBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
VUJI
Samples
TLV71325PDQNR
ACTIVE
X2SON
DQN
4
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AZ
Samples
TLV71325PDQNT
ACTIVE
X2SON
DQN
4
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AZ
Samples
TLV713285PDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
VULI
Samples
TLV713285PDBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
VULI
Samples
TLV713285PDQNR
ACTIVE
X2SON
DQN
4
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
A2
Samples
TLV713285PDQNT
ACTIVE
X2SON
DQN
4
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
A2
Samples
TLV71328PDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
VUKI
Samples
TLV71328PDBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
VUKI
Samples
TLV71328PDQNR
ACTIVE
X2SON
DQN
4
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AK
Samples
TLV71328PDQNT
ACTIVE
X2SON
DQN
4
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AK
Samples
TLV71330PDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
VUMI
Samples
TLV71330PDBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
VUMI
Samples
TLV71330PDQNR
ACTIVE
X2SON
DQN
4
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AL
Samples
TLV71330PDQNT
ACTIVE
X2SON
DQN
4
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AL
Samples
TLV71333PDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
VUFI
Samples
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
6-Dec-2022
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TLV71333PDBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
VUFI
Samples
TLV71333PDQNR
ACTIVE
X2SON
DQN
4
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AH
Samples
TLV71333PDQNT
ACTIVE
X2SON
DQN
4
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AH
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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