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SLOS490TPA6205A1
SLOS490C – JULY 2006 – REVISED NOVEMBER 2015
TPA6205A1 1.25-W Mono Fully Differential Audio Power Amplifier
With 1.8-V Input logic Thresholds
1 Features
3 Description
•
The TPA6205A1 device is a 1.25-W mono fully
differential amplifier designed to drive a speaker with
at least 8-Ω impedance while consuming less than 37
mm2 (ZQV package option) total printed-circuit-board
(PCB) area in most applications. This device operates
from 2.5 V to 5.5 V, drawing only 1.7 mA of quiescent
supply current. The TPA6205A1 is available in the
space-saving 2-mm × 2-mm MicroStar Junior BGA
package, and the space saving 3-mm × 3-mm QFN
(DRB) package.
1
•
•
•
•
•
•
•
1.25 W Into 8-Ω From a 5-V Supply at THD = 1%
(Typical)
Shutdown Pin has 1.8-V Compatible Thresholds
Low Supply Current: 1.7 mA Typical
Shutdown Current < 10 µA
Only Five External Components
– Improved PSRR (90 dB) and Wide Supply
Voltage (2.5 V to 5.5 V) for Direct Battery
Operation
– Fully Differential Design Reduces RF
Rectification
– Improved CMRR Eliminates Two Input
Coupling Capacitors
– C(BYPASS) Is Optional Due to Fully Differential
Design and High PSRR
Available in 3-mm × 3-mm QFN Package (DRB)
Available in an 8-Pin PowerPAD™ MSOP (DGN)
Available in a 2-mm × 2-mm MicroStar Junior™
BGA Package (ZQV)
•
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
MSOP-PowerPAD (8) 3.00 mm × 3.00 mm
TPA6205A1
SON (8)
3.00 mm × 3.00 mm
BGA MICROSTAR
JUNIOR (8)
2.00 mm × 2.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
Features like 85-dB PSRR from 90 Hz to 5 kHz,
improved RF-rectification immunity, and small PCB
area makes the TPA6205A1 ideal for wireless
handsets. A fast start-up time of 4s with minimal pop
makes the TPA6205A1 ideal for PDA applications.
Designed for Wireless Handsets, PDAs, and
Other Mobile Devices
Compatible With Low Power (1.8-V Logic) I/O
Threshold Control Signals
Application Circuit
Example Solution Size
Actual Solution Size
VDD
RF
In From
DAC
RI
+ RI
ININ+
Cs
_
C(BYPASS)
(Optional)
VO+
CS
(1)C
B
VO+
RF
SHUTDOWN
RF
To Battery
GND
Bias
Circuitry
5,25 mm
RI
RI
RF
6,9 mm
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SLOS490TPA6205A1
SLOS490C – JULY 2006 – REVISED NOVEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
4
4
4
4
5
5
6
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Operating Characteristics..........................................
Dissipation Ratings ...................................................
Typical Characteristics ..............................................
Parameter Measurement Information ................ 11
Detailed Description ............................................ 11
9.1 Overview ................................................................. 11
9.2 Functional Block Diagram ....................................... 11
9.3 Feature Description................................................. 11
9.4 Device Functional Modes........................................ 15
10 Application and Implementation........................ 18
10.1 Application Information.......................................... 18
10.2 Typical Applications .............................................. 18
11 Power Supply Recommendations ..................... 22
11.1
Power Supply Decoupling Capacitors.................. 22
12 Layout................................................................... 23
12.1 Layout Guidelines ................................................. 23
12.2 Layout Example .................................................... 24
13 Device and Documentation Support ................. 26
13.1
13.2
13.3
13.4
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
26
26
26
26
14 Mechanical, Packaging, and Orderable
Information ........................................................... 26
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (June 2008) to Revision C
Page
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
•
Removed Ordering Information table .................................................................................................................................... 1
2
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Product Folder Links: SLOS490TPA6205A1
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SLOS490C – JULY 2006 – REVISED NOVEMBER 2015
5 Device Comparison Table
DEVICE NUMBER
SPEAKER
CHANNELS
SPEAKER AMP
TYPE
OUTPUT POWER (W)
PSRR (dB)
TPA6203A1
Mono
Class AB
1.25
90
TPA6204A1
Mono
Class AB
1.7
85
TPA6205A1 (1.8-V comp SD)
Mono
Class AB
1.25
90
TPA6211A1
Mono
Class AB
3.1
85
6 Pin Configuration and Functions
ZQV Package
8-Pin BGA MICROSTAR JUNIOR
Top View
VOSHUTDOWN
BYPASS
DRB Package
8-Pin SON
Top View
GND
1 2 3
A
B
C
SHUTDOWN
VDD
VO+
IN-
1
BYPASS 2
IN+
8 V
O7 GND
IN+
3
6 VDD
IN-
4
5 VO+
(SIDE VIEW)
DGN Package
8-Pin MSOP-PowerPAD
Top View
SHUTDOWN
1
8
VO-
BYPASS
2
7
GND
IN+
3
6
VDD
IN-
4
5
VO+
Pin Functions
PIN
BGA MICROSTAR
JUNIOR
SON,
MSOP-PowerPAD
I/O
C1
2
I
Mid-supply voltage. Adding a bypass capacitor improves PSRR.
GND
B2
7
I
High-current ground
IN–
C3
4
I
Negative differential input
IN+
C2
3
I
Positive differential input
SHUTDOWN
B1
1
I
Shutdown terminal (active low logic)
VDD
A3
6
I
Supply voltage terminal
VO+
B3
5
O
Positive BTL output
VO–
A1
8
O
Negative BTL output
Thermal Pad
N/A
—
—
Connect to ground. Thermal pad must be soldered down in all
applications to properly secure device on the PCB.
NAME
BYPASS
DESCRIPTION
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SLOS490C – JULY 2006 – REVISED NOVEMBER 2015
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VDD
Supply voltage
VI
Input voltage
INx and SHUTDOWN pins
MIN
MAX
UNIT
–0.3
6
V
–0.3
0.3
V
Continuous total power dissipation
See Dissipation
Ratings
TA
Operating free-air temperature
–40
85
ºC
TJ
Junction temperature
–40
125
ºC
260
ºC
150
°C
Lead temperature 1.6 mm (1/16 inch) from
ZQV, DRB, DGN
case for 10 seconds
Tstg
(1)
Storage temperature
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±4000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
V
±1500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
2.5
5.5
UNIT
VDD
Supply voltage
VIH
High-level input voltage
SHUTDOWN
VIL
Low-level input voltage
SHUTDOWN
VIC
Common-mode input voltage
VDD = 2.5 V, 5.5 V, CMRR ≤ –60 dB
0.5
VDD–0.8
V
TA
Operating free-air temperature
–40
85
°C
ZL
Load impedance
6.4
1.15
V
V
0.5
V
Ω
8
7.4 Thermal Information
TPA6205A1
THERMAL METRIC (1)
BGA MICROSTAR
JUNIOR
SON
MSOP
PowerPAD
UNIT
8 PINS
8 PINS
8 PINS
RθJA
Junction-to-ambient thermal resistance
134.4
57.3
109.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
79.8
84.0
67.8
°C/W
RθJB
Junction-to-board thermal resistance
71.1
32.2
47.6
°C/W
ψJT
Junction-to-top characterization parameter
5.3
3.7
4.7
°C/W
ψJB
Junction-to-board characterization parameter
71.0
32.2
47.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
11.8
15.9
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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SLOS490C – JULY 2006 – REVISED NOVEMBER 2015
7.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
[VOO]
Output offset voltage
(measured differentially)
VI = 0 V, VDD = 2.5 V to 5.5 V
PSRR
Power supply rejection ratio
VDD = 2.5 V to 5.5 V
VDD = 3.6 V to 5.5 V, VIC = 0.5 V to VDD – 0.8
VDD = 2.5 V, VIC = 0.5 V to 1.7 V
CMRR
Common-mode rejection ratio
VOL
Low-level output voltage
RL = 8 Ω, VIN+ = VDD, VIN– =
0 V or VIN+ = 0 V, VIN– = VDD
MIN
RL = 8 Ω, VIN+ = VDD, VIN– =
0 V or VIN+ = 0 V, VIN– = VDD
UNIT
mV
–90
–70
dB
–70
–65
–62
–55
VDD = 5.5 V
0.3
0.46
VDD = 3.6 V
0.22
VDD = 5.5 V
High-level output voltage
MAX
9
VDD = 2.5 V
VOH
TYP
0.19
4.8
VDD = 3.6 V
VDD = 2.5 V
dB
V
0.26
5.12
3.28
2.1
V
2.24
[IIH]
High-level input current
VDD = 5.5 V, VI = 5.8 V
1.2
[IIL]
Low-level input current
VDD = 5.5 V, VI = –0.3 V
1.2
µA
µA
IDD
Supply current
VDD = 2.5 V to 5.5 V, No load, SHUTDOWN = VIH
1.7
2
mA
IDD(SD)
Supply current in shutdown
mode
SHUTDOWN = VIL , VDD = 2.5 V to 5.5 V, No load
0.01
0.9
µA
TYP
MAX
7.6 Operating Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
PO
THD+N
kSVR
SNR
Output power
TEST CONDITIONS
THD + N = 1%, f = 1
kHz
MIN
VDD = 5 V
1.25
VDD = 3.6 V
0.63
VDD = 2.5 V
0.3
VDD = 5 V, PO = 1 W, f = 1 kHz
Total harmonic distortion plus
VDD = 3.6 V, PO = 0.5 W, f = 1 kHz
noise
VDD = 2.5 V, PO = 200 mW, f = 1 kHz
Supply ripple rejection ratio
Signal-to-noise ratio
0.07%
0.08%
f = 217 Hz to 2 kHz, VRIPPLE
= 200 mVPP
–87
C(BYPASS) = 0.47 F,
VDD = 2.5 V to 3.6 V,
Inputs AC-grounded
with CI = 2 F
f = 217 Hz to 2 kHz, VRIPPLE
= 200 mVPP
–82
C(BYPASS) = 0.47 F,
VDD = 2.5 V to 5.5 V,
Inputs AC-grounded
with CI = 2 F
f = 40 Hz to 20 kHz, VRIPPLE
= 200 mVPP
≤ –74
VDD = 5 V, PO= 1 W
dB
104
dB
No weighting
17
VRMS
A weighting
13
Vn
Output voltage noise
CMRR
Common-mode rejection ratio
ZI
Input impedance
ZO
Output impedance
Shutdown mode
Shutdown attenuation
f = 20 Hz to 20 kHz, RF = RI = 20 kΩ
VDD= 2.5 V to 5.5 V,
Resistor tolerance =
0.1%, Gain = 4V/V,
VICM = 200 mVPP
W
0.06%
C(BYPASS) = 0.47°F,
VDD = 3.6 V to 5.5 V,
Inputs AC-grounded
with CI = 2 F
f = 20 Hz to 20 kHz
UNIT
f = 20 Hz to 1 kHz
≤ –85
f = 20 Hz to 20 kHz
≤ –74
2
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>10
dB
MΩ
kΩ
–80
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dB
5
SLOS490TPA6205A1
SLOS490C – JULY 2006 – REVISED NOVEMBER 2015
www.ti.com
7.7 Dissipation Ratings
PACKAGE
TA ≤ 25°C POWER
RATING
DERATING
FACTOR
TA ≤ 70°C POWER RATING TA ≤ 85°C POWER RATING
ZQV
885 mW
8.8 mW/°C
486 mW
354 mW
DGN
2.13 W
17.1 mW/°C
1.36 W
1.11 W
DRB
2.7 W
21.8 mW/°C
1.7 W
1.4 W
7.8 Typical Characteristics
Table 1. Table of Graphs
FIGURE
vs Supply voltage
Figure 1
vs Load resistance
Figure 2, Figure 3
Figure 4, Figure 5
PO
Output power
PD
Power dissipation
vs Output power
Maximum ambient temperature
vs Power dissipation
Figure 6
vs Output power
Total harmonic distortion + noise
Figure 7, Figure 8
vs Frequency
Figure 9, Figure 10, Figure 11, Figure 12
vs Common-mode input voltage
CMRR
vs Frequency
Supply voltage rejection ratio
vs Common-mode input voltage
Figure 18
GSM Power supply rejection
vs Time
Figure 19
GSM Power supply rejection
vs Frequency
Figure 20
vs Frequency
Figure 21
vs Common-mode input voltage
Figure 22
Closed loop gain/phase
vs Frequency
Figure 23
Open loop gain/phase
vs Frequency
Figure 24
Supply current
vs Supply voltage
Figure 25
Start-up time
vs Bypass capacitor
Figure 26
Common-mode rejection ratio
IDD
Figure 13
Supply voltage rejection ratio
Figure 14, Figure 15, Figure 16, Figure 17
1.4
1.8
1.6
f = 1 kHz
THD+N = 1%
Gain = 1 V/V
1.2
1.2
PO - Output Power - W
PO - Output Power - W
1.4
THD+N = 10%
1
0.8
0.6
THD+N = 1%
0.4
VDD = 3.6 V
0.8
VDD = 2.5 V
0.6
0.4
0.2
0.2
0
VDD = 5 V
1
0
2.5
3
3.5
4
4.5
5
8
13
VDD - Supply V oltage - V
Figure 1. Output Power vs Supply Voltage
6
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18
23
28
32
RL - Load Resistance - W
Figure 2. Output Power vs Load Resistance
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1.8
0.4
f = 1 kHz
THD+N = 10%
Gain = 1 V/V
1.6
VDD = 5 V
PD - Power Dissipation - W
PO - Output Power - W
1.4
VDD = 3.6 V
0.35
1.2
VDD = 3.6 V
1
0.8
VDD = 2.5 V
0.6
0.4
0.2
0
8W
0.25
0.2
0.15
16 W
0.1
0.05
0
8
13
18
23
RL - Load Resistance - W
28
32
0
0.2
0.6
0.8
Figure 4. Power Dissipation vs Output Power
90
0.7
VDD = 5 V
80
Maximum Ambient Temperature - Co
0.6
8W
0.5
0.4
0.3
16 W
0.2
0.1
0
70
60
50
40
30
ZQV Package Only
20
10
0
0
0.2
0.4
0.6
0.8
1
1.2
0
1.4
0.1
Figure 5. Power Dissipation vs Output Power
0.3
0.4
0.5
0.6
0.7
0.8
Figure 6. Maximum Ambient Temperature vs Power
Dissipation
10
5
2.5 V
2
3.6 V
1
0.5
5V
0.2
0.1
0.05
RL = 8 W,f = 1 kHz
C(Bypass) = 0 to 1 mF
Gain = 1 V/V
0.01
10 m
100 m
1
2 3
THD+N - Total Harmonic Distortion + Noise - %
10
0.02
0.2
PD - Power Dissipation - W
PO - Output Power - W
THD+N - Total Harmonic Distortion + Noise - %
0.4
PO - Output Power - W
Figure 3. Output Power vs Load Resistance
PD - Power Dissipation - W
0.3
5
2
RL = 16 W
f = 1 kHz
C(Bypass) = 0 to 1 mF
Gain = 1 V/V
1
0.5
0.2
5V
3.6 V
0.1
0.05
0.02
0.01
10 m
PO - Output Power - W
Figure 7. Total Harmonic Distortion + Noise vs Output
Power
2.5 V
100 m
1
2
PO - Output Power - W
Figure 8. Total Harmonic Distortion + Noise vs Output
Power
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SLOS490TPA6205A1
0.5
VDD = 5 V
CI = 2 mF
RL = 8 W
C(Bypass) = 0 to 1 mF
Gain = 1 V/V
0.2
250 mW
2
1
50 mW
0.1
0.05
0.02
1W
0.01
0.005
0.002
0.001
20
100 200
1k 2k
f - Frequency - Hz
10 k 20 k
THD+N - Total Harmonic Distortion + Noise - %
Figure 9. Total Harmonic Distortion + Noise vs Frequency
10
5
VDD = 2.5 V
CI = 2 mF
RL = 8 W
C(Bypass) = 0 to 1 mF
Gain = 1 V/V
2
1
0.5
15 mW
0.2
0.1
75 mW
0.05
0.02
200 mW
0.01
0.005
0.002
0.001
20
50 100 200 500 1 k 2 k
f - Frequency - Hz
5 k 10 k 20 k
Figure 11. Total Harmonic Distortion + Noise vs Frequency
THD+N - Total Harmonic Distortion + Noise - %
10
5
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10
5
2
1
0.5
0.1
125 mW
0.05
0.02
500 mW
0.01
0.005
0.002
0.001
20
50 100 200 500 1 k 2 k
f - Frequency - Hz
5 k 10 k 20 k
10
5
VDD = 3.6 V
CI = 2 mF
RL = 16 W
C(Bypass) = 0 to 1 mF
Gain = 1 V/V
2
1
0.5
0.2
25 mW
125 mW
0.1
0.05
0.02
0.01
250 mW
0.005
0.002
0.001
20
50 100 200 500 1 k 2 k
f - Frequency - Hz
5 k 10 k 20 k
Figure 12. Total Harmonic Distortion + Noise vs Frequency
0
1
VDD = 2.5 V
0.10
VDD = 3.6 V
0.01
- Supply V oltage Rejection Ratio - dB
SVR
f = 1 kHz
PO = 200 mW
k
THD+N - Total Harmonic Distortion + Noise - %
25 mW
0.2
10
0
0.5
1
1.5
2
2.5
3
3.5
VIC - Common Mode Input V oltage - V
Figure 13. Total Harmonic Distortion + Noise vs CommonMode Input Voltage
8
VDD = 3.6 V
CI = 2 mF
RL = 8 W
C(Bypass) = 0 to 1 mF
Gain = 1 V/V
Figure 10. Total Harmonic Distortion + Noise vs Frequency
THD+N - Total Harmonic Distortion + Noise - %
THD+N - Total Harmonic Distortion + Noise - %
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CI = 2 mF
RL = 8 W
C(Bypass) = 0.47 mF
Vp-p = 200 mV
Inputs ac-Grounded
Gain = 1 V/V
-10
-20
-30
-40
-50
-60
VDD =2. 5 V
-70
VDD = 5 V
-80
-90
VDD = 3.6 V
-100
20
50 100 200
500 1 k 2 k
5 k 10 k 20 k
f - Frequency - Hz
Figure 14. Supply Voltage Rejection Ratio vs Frequency
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0
-20
-30
-40
-50
- Supply V oltage Rejection Ratio - dB
SVR
Gain = 5 V/V
CI = 2 mF
RL = 8 W
C(Bypass) = 0.47 mF
Vp-p = 200 mV
Inputs ac-Grounded
-10
VDD =2. 5 V
-60
VDD = 5 V
-70
-80
VDD = 3.6 V
-90
-100
k
k
- Supply V oltage Rejection Ratio - dB
SVR
0
20
50 100 200
500 1 k 2 k
CI = 2 mF
RL = 8 W
Inputs Floating
Gain = 1 V/V
-10
-20
-30
-40
-50
VDD =2. 5 V
-60
VDD = 5 V
-70
VDD = 3.6 V
-80
-90
-100
5 k 10 k 20 k
20
50 100 200
500 1 k 2 k
5 k 10 k 20 k
f - Frequency - Hz
f - Frequency - Hz
Figure 15. Supply Voltage Rejection Ratio vs Frequency
Figure 16. Supply Voltage Rejection Ratio vs Frequency
-10
-30
-40
-50
C(Bypass) = 0
C(Bypass) = 0.47 mF
-60
C(Bypass) = 1 mF
-70
-80
-30
-90
-100
20
50 100 200
500 1 k 2 k
VDD = 2.5 V
-40
VDD = 3.6 V
-50
-60
-70
SVR
C(Bypass) = 0.1 mF
f = 217 Hz
C(Bypass) = 0.47 mF
RL = 8 W
Gain = 1 V/V
-20
5 k 10 k 20 k
-80
VDD = 5 V
-90
0
f - Frequency - Hz
1
2
3
4
VIC - Common Mode Input V oltage - V
5
Figure 18. Supply Voltage Rejection Ratio vs CommonMode Input Voltage
Figure 17. Supply Voltage Rejection Ratio vs Frequency
0
C1
Frequency
217.41 Hz
-50
C1 - Duty
20 %
-100
C1 High
3.598 V
C1 Pk-Pk
504 mV
VO
Ch1 100 mV/div
Ch4 10 mV/div
t - Time - ms
2 ms/div
VO - Output V oltage - dBV
Voltage - V
VDD
0
-150
VDD Shown in Figure 19
CI = 2 mF,
C(Bypass) = 0.47 mF,
Inputs ac-Grounded
Gain = 1V/V
-50
-100
V DD - Supply V oltage - dBV
-20
- Supply V oltage Rejection Ratio - dB
VDD = 3.6 V
CI = 2 mF
RL = 8 W
Inputs ac-Grounded
Gain = 1 V/V
-10
k
k
- Supply V oltage Rejection Ratio - dB
SVR
0
-150
0 200 400 600 800 1k 1.2k 1.4k 1.6k 1.8k 2k
f - Frequency - Hz
Figure 19. GSM Power Supply Rejection vs Time
Figure 20. GSM Power Supply Rejection vs Frequency
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0
VDD = 2.5 V to 5 V
VIC = 200 mVp-p
RL = 8 W
Gain = 1 V/V
-30
-40
-50
-60
-70
-80
-90
-100
20
50 100 200 500 1 k 2 k
5 k 10 k 20 k
RL = 8W
Gain = 1 V/V
-10
-20
-30
-40
VDD = 2.5 V
-50
VDD = 5 V
-60
-70
-80
-90
VDD = 3.6 V
-100
40
10
20
-20
-20
-30
-60
-100
-40
50
0
0
-50
-50
Phase
-100
-180
-150
-150
-220
10 M
-200
-140
-70
1k
50
-100
VDD = 3.6 V
RL = 8 W
Gain = 1 V/V
100
100
Gain
Gain - dB
60
-10
150
100
Phase - Degrees
Gain - dB
150
100
Gain
10
4.5 5
200
VDD = 3.6 V
RL = 8 W
140
-60
3.5 4
200
180
20
-50
2.5 3
Figure 22. Common-Mode Rejection Ratio vs CommonMode Input Voltage
220
Phase
0
1.5 2
VIC - Common Mode Input Voltage - V
Figure 21. Common-Mode Rejection Ratio vs Frequency
30
0.5 1
0
f - Frequency - Hz
Phase - Degrees
-20
CMRR - Common Mode Rejection Ratio - dB
CMRR - Common Mode Rejection Ratio - dB
0
-10
10 k
100 k 1 M
100
1k
f - Frequency - Hz
10 k
100 k
1M
-200
10 M
f - Frequency - Hz
Figure 23. Closed-Loop Gain / Phase vs Frequency
Figure 24. Open-Loop Gain / Phase vs Frequency
6
1.8
1.6
5
1.2
Start-Up Time - ms
I DD - Supply Current - mA
1.4
1
0.8
0.6
0.4
4
3
2
1
0.2
0
0
0 0.5 1
1.5 2 2.5 3 3.5
4 4.5 5
5.5
VDD - Supply V oltage - V
Figure 25. Supply Current vs Supply Voltage
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0
0.5
1
1.5
C(Bypass) - Bypass Capacitor - mF
2
Start-Up time is the time it takes (from a low-to-high transition on
SHUTDOWN) for the gain of the amplifier to reach –3 dB of the
final gain
Figure 26. Start-Up Time vs Bypass Capacitor
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8 Parameter Measurement Information
All parameters are measured according to the conditions described in the Specifications section.
9 Detailed Description
9.1 Overview
The TPA6205A1 is a 1.25-W mono fully differential amplifier. The devices operates in the range of 2.5 V to 5.5 V
and with at least 8-Ω impedance load. It's fully differential input allows it to avoid using input coupling capacitors
and improves its RF-immunity.
9.2 Functional Block Diagram
VDD
RF
RI
IN-
+ RI
IN+
In From
DAC
Cs
_
VO+
VO-
+
RF
SHUTDOWN
To Battery
GND
Bias
Circuitry
C(BYPASS)
(Optional)
9.3 Feature Description
9.3.1 Fully Differential Amplifiers
The TPA6205A1 is a fully differential amplifier with differential inputs and outputs. The fully differential amplifier
consists of a differential amplifier and a common-mode amplifier. The differential amplifier ensures that the
amplifier outputs a differential voltage that is equal to the differential input times the gain. The common-mode
feedback ensures that the common-mode voltage at the output is biased around VDD/2 regardless of the
common-mode voltage at the input.
9.3.1.1 Advantages of Fully Differential Amplifiers
• Input coupling capacitors not required: A fully differential amplifier with good CMRR, like the TPA6205A1,
allows the inputs to be biased at voltage other than mid-supply. For example, if a DAC has mid-supply lower
than the mid-supply of the TPA6205A1, the common-mode feedback circuit adjusts for that, and the
TPA6205A1 outputs are still biased at mid-supply of the TPA6205A1. The inputs of the TPA6205A1 can be
biased from 0.5 V to VDD – 0.8 V. If the inputs are biased outside of that range, input coupling capacitors are
required.
• Mid-supply bypass capacitor, C(BYPASS), not required: The fully differential amplifier does not require a bypass
capacitor. This is because any shift in the mid-supply affects both positive and negative channels equally and
cancels at the differential output. However, removing the bypass capacitor slightly worsens power supply
rejection ratio (kSVR), but a slight decrease of kSVR may be acceptable when an additional component can be
eliminated (see Figure 17).
• Better RF-immunity: GSM handsets save power by turning on and shutting off the RF transmitter at a rate of
217 Hz. The transmitted signal is picked-up on input and output traces. The fully differential amplifier cancels
the signal much better than the typical audio amplifier.
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Feature Description (continued)
9.3.2 Fully Differential Amplifier Efficiency and Thermal Information
Class-AB amplifiers are inefficient. The primary cause of these inefficiencies is voltage drop across the output
stage transistors. There are two components of the internal voltage drop. One is the headroom or DC voltage
drop that varies inversely to output power. The second component is due to the sinewave nature of the output.
The total voltage drop can be calculated by subtracting the RMS value of the output voltage from VDD. The
internal voltage drop multiplied by the average value of the supply current, IDD(avg), determines the internal power
dissipation of the amplifier.
An easy-to-use equation to calculate efficiency starts Although the voltages and currents for SE and BTL out as
being equal to the ratio of power from the are sinusoidal in the load, currents from the supply power supply to the
power delivered to the load. To are very different between SE and BTL accurately calculate the RMS and
average values of configurations. In an SE application the current power in the load and in the amplifier, the
current and waveform is a half-wave rectified shape, whereas in voltage waveform shapes must first be
understood BTL it is a full-wave rectified waveform. This means (see Figure 27). RMS conversion factors are
different. Keep in mind that for most of the waveform both the push and pull transistors are not on at the same
time, which supports the fact that each amplifier in the BTL device only draws current from the supply for half the
waveform. Equation 1 through Equation 7 are the basis for calculating amplifier efficiency.
VO
V(LRMS)
IDD
IDD(avg)
Figure 27. Voltage and Current Waveforms for BTL Amplifiers
Efficiency a BTL amplifier =
PL
PSUP
where
PL =
•
VLrms2
RL
VLRMS =
•
•
•
•
•
•
VP
2
PL = Power delivered to load
PSUP = Power drawn from power supply
VLRMS = RMS voltage on BTL load
RL = Load resistance
VP = Peak voltage on BTL load
(1)
Therefore, PL is calculated by Equation 2:
PL =
VL 2
2RL
(2)
And PSUP is calculated by Equation 3:
PSUP = VDDIDDavg
where
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Feature Description (continued)
•
•
•
PSUP = Power drawn from power supply
IDDavg = Average current drawn from the power supply
VDD = Power supply voltage
(3)
IDDavg can be found in Equation 4:
2VP
1 p VP
1 V
p
IDDavg =
sin(t) dt = - ´ P [cos(t)] 0 =
0
p RL
p RL
pRL
(4)
Therefore PSUP is calculated by Equation 5:
2V V
PSUP = DD P
pRL
(5)
ò
substituting PL and PSUP into Equation 6,
VP2
2RL
pVP
Efficiency of a BTL amplifier =
=
2VDD VP 4VDD
pRL
where
VP = 2PLRL
•
(6)
Therefore:
h BTL =
p 2PLRL
4 VDD
where
•
ηBTL = Efficiency of a BTL amplifier
(7)
Table 2. Efficiency and Maximum Ambient Temperature vs Output Power in 5-V 8- Ω BTL Systems
OUTPUT POWER
(W)
EFFICIENCY (%)
INTERNAL
DISSIPATION (W)
POWER FROM SUPPLY (W)
MAX AMBIENT
TEMPERATURE (°C)
0.25
31.4
0.55
0.75
62
0.5
44.4
0.62
1.12
54
1
62.8
0.59
1.59
58
1.25
70.2
0.53
1.78
65
Table 2 employs Equation 7 to calculate efficiencies for four different output power levels. Note that the efficiency
of the amplifier is quite low for lower power levels and rises sharply as power to the load is increased resulting in
a nearly flat internal power dissipation over the normal operating range. Note that the internal dissipation at full
output power is less than in the half power range. Calculating the efficiency for a specific system is the key to
proper power supply design. For a 1.25-W audio system with 8-Ω loads and a 5-V supply, the maximum draw on
the power supply is almost 1.8 W.
A final point to remember about Class-AB amplifiers is how to manipulate the terms in the efficiency equation to
the utmost advantage when possible. Note that in Equation 7, VDD is in the denominator. This indicates that as
VDD goes down, efficiency goes up.
Equation 8 is a simple formula for calculating the maximum power dissipated, PDmax, may be used for a
differential output application:
PDmax =
2 V 2DD
p2RL
(8)
PDmax for a 5-V, 8-Ω system is 634 mW.
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The maximum ambient temperature depends on the heat sinking ability of the PCB system. The derating factor
for the 2 mm × 2 mm Microstar Junior package is shown in the dissipation rating table. Converting this to θJA is
shown in Equation 9:
1
1
QJA =
=
= 113°C / W
Derating Factor 0.0088
(9)
Given θJA, the maximum allowable junction temperature, and the maximum internal dissipation, the maximum
ambient temperature can be calculated with Equation 10. The maximum recommended junction temperature for
the TPA6205A1 is 125°C.
TA Max = TJMax - QJA PDmax
= 125 - 113(0.634) = 53.3°C
(10)
Equation 10 shows that the maximum ambient temperature is 53.3°C at maximum power dissipation with a 5-V
supply. Table 2 shows that for most applications no airflow is required to keep junction temperatures in the
specified range. The TPA6205A1 is designed with thermal protection that turns the device off when the junction
temperature surpasses 150°C to prevent damage to the IC. Also, using more resistive than 8-Ω packages, it is
good practice minimize the speakers dramatically increases the thermal performance by reducing the output
current.
9.3.3 Differential Output Versus Single-Ended Output
Figure 28 shows a Class-AB audio power amplifier (APA) in a fully differential configuration. The TPA6205A1
amplifier has differential outputs driving both ends of the load. There are several potential benefits to this
differential drive configuration, but initially consider power to the load. The differential drive to the speaker means
that as one side is slewing up, the other side is slewing down, and vice versa. This in effect doubles the voltage
swing on the load as compared to a ground referenced load. Plugging 2 × VO(PP) into the power equation, where
voltage is squared, yields 4× the output power from the same supply rail and load impedance (see Equation 11).
VO(PP )
V(rms ) =
2 2
Power =
V(rms)2
RL
(11)
VDD
VO(PP)
RL
VDD
2x VO(PP)
–VO(PP)
Figure 28. Differential Output Configuration
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In a typical wireless handset operating at 3.6 V, bridging raises the power into an 8-Ω speaker from a singledended (SE, ground reference) limit of 200 mW to 800 mW. In sound power that is a 6-dB improvement—which is
loudness that can be heard. In addition to increased power there are frequency response concerns. Consider the
single-supply SE configuration shown in Figure 29. A coupling capacitor is required to block the DC offset voltage
from reaching the load. This capacitor can be quite large (approximately 33 μF to 1000 μF) so it tends to be
expensive, heavy, occupy valuable PCB area, and have the additional drawback of limiting low-frequency
performance of the system. This frequency-limiting effect is due to the high pass filter network created with the
speaker impedance and the coupling capacitance and is calculated with Equation 12.
1
fc =
2pRL CC
(12)
For example, a 68-μF capacitor with an 8-Ω speaker would attenuate low frequencies below 293 Hz. The BTL
configuration cancels the DC offsets, which eliminates the need for the blocking capacitors. Low-frequency
performance is then limited only by the input network and speaker response. Cost and PCB space are also
minimized by eliminating the bulky coupling capacitor.
VDD
VO(PP)
CC
RL
VO(PP)
–3 dB
fc
Figure 29. Single-Ended Output and Frequency Response
Increasing power to the load does carry a penalty of increased internal power dissipation. The increased
dissipation is understandable considering that the BTL configuration produces 4× the output power of the SE
configuration.
9.4 Device Functional Modes
9.4.1 Summing Input Signals With The TPA6205A1
Most wireless phones or PDAs need to sum signals at the audio power amplifier or just have two signal sources
that need separate gain. The TPA6205A1 makes it easy to sum signals or use separate signal sources with
different gains. Many phones now use the same speaker for the earpiece and ringer, where the wireless phone
would require a much lower gain for the phone earpiece than for the ringer. PDAs and phones that have stereo
headphones require summing of the right and left channels to output the stereo signal to the mono speaker.
9.4.1.1 Summing Two Differential Input Signals
Two extra resistors are needed for summing differential signals (a total of 10 components). The gain for each
input source can be set independently (see Equation 13 and Equation 14, and Figure 30).
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Device Functional Modes (continued)
Gain 1 =
VO
R æVö
=- Fç ÷
VI1
RI1 è V ø
(13)
V
R æVö
Gain 2 = O = - F ç ÷
VI2
RI2 è V ø
Differential
Input 2
Differential
Input 1
(14)
-
CI2
RI2
+
CI2
RI2
-
CI1
RI1
IN-
CI1
RI1
IN+
+
VDD
RF
To Battery
CS
_
VO+
RF
SHUTDOWN
VO+
GND
Bias
Circuitry
C(BYPASS)
(Optional)
Figure 30. Application Schematic With TPA6205A1 Summing Two Differential Inputs
9.4.1.2 Summing a Differential Input Signal and a Single-Ended Input Signal
Figure 31 shows how to sum a differential input signal and a single-ended input signal. Ground noise can couple
in through IN+ with this method. It is better to use differential inputs. To assure that each input is balanced, the
single-ended input must be driven by a low-impedance source even if the input is not in use. Both input nodes
must see the same impedance for optimum performance, thus the use of RP and CP.
V
R æVö
Gain 1 = O = - F ç ÷
VI1
RI1 è V ø
(15)
Gain 2 =
VO
R æVö
=- Fç ÷
VI2
RI2 è V ø
(16)
9.4.1.3 Summing Two Single-Ended Input Signals
Four resistors and three capacitors are needed for summing single-ended input signals. The gain and corner
frequencies (fc1 and fc2) for each input source can be set independently. Resistor, RP, and capacitor, CP, are
needed on the IN+ terminal to match the impedance on the IN- terminal. The single-ended inputs must be driven
by low impedance sources even if one of the inputs is not outputting an AC signal.
V
2 ´ 150 k W
Gain 1 = o =
VI1
RI 2
(17)
Gain 2 =
CI1
Vo
2 ´ 150 k W
=
VI 2
RI 2
(18)
1
=
2pRI1FC1
CI2 =
(19)
1
2pRI 2FC 2
(20)
CP = CI1 + CI2
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Device Functional Modes (continued)
RP =
RI1 ´ RI2
RI1 + RI2
(22)
CI2
Single Ended
Input 2
RI2
CI1
RI1
Single Ended
Input 1
IN-
RP
CP
VDD
RF
IN+
Cs
_
VO+
VO-
+
RF
SHUTDOWN
To Battery
GND
Bias
Circuitry
C(BYPASS)
(Optional)
Figure 31. Application Schematic With TPA6205A1 Summing Two Single-Ended Inputs
9.4.2 Shutdown Mode
The TPA6205A1 can be put in shutdown mode when asserting SHUTDOWN pin to a logic LOW. While in
shutdown mode, the device output stage is turned off, making the current consumption very low. The device exits
shutdown mode when a HIGH logic level is applied to SHUTDOWN pin. SHUTDOWN pin is 1.8-V compatible.
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
These typical connection diagrams highlight the required external components and system level connections for
proper operation of the device in several popular cases. Each of these configurations can be realized using the
Evaluation Modules (EVMs) for the device. These flexible modules allow full evaluation of the device in the most
common modes of operation. Any design variation can be supported by TI through schematic and layout reviews.
Visit http://e2e.ti.com for design assistance and join the audio amplifier discussion forum for additional
information.
10.2 Typical Applications
Figure 32 through Figure 31 show application schematics for differential and single-ended inputs.
10.2.1 TPA6205A1 With Differential Input
The TPA6205A1 can be used with differential input without input capacitors. This section describes the design
considerations for this application.
VDD
RF
In From
DAC
- RI
IN-
+ RI
IN+
Cs
_
VO+
VO-
+
RF
SHUTDOWN
To Battery
GND
Bias
Circuitry
C(BYPASS)
(Optional)
Figure 32. Typical Differential Input Application Schematic
10.2.1.1 Design Requirements
Table 3 lists the design parameters of the device.
Table 3. Design Parameters
PARAMETER
Power Supply
Shutdown Input
Speaker
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EXAMPLE VALUE
5V
High > 2 V
Low < 0.8 V
8Ω
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10.2.1.2 Detailed Design Procedure
10.2.1.2.1 Selecting Components
Typical values are shown in Table 4.
Table 4. Typical Component Values
COMPONENT
VALUE
RI
10 kΩ
RF
C(BYPASS)
(1)
10 kΩ
(1)
0.22 µF
CS
1 µF
CI
0.22 µF
C(BYPASS) is optional
10.2.1.2.1.1 Resistors (RF and RI)
The input (RI) and feedback resistors (RF) set the gain of the amplifier according to Equation 23.
Gain - RF / RI
(23)
RF and RI should range from 1 kΩ to 100 kΩ. Most graphs were taken with RF = RI = 20 kΩ.
Resistor matching is very important in fully differential amplifiers. The balance of the output on the reference
voltage depends on matched ratios of the resistors. CMRR, PSRR, and the cancellation of the second harmonic
distortion diminishes if resistor mismatch occurs. Therefore, it is recommended to use 1% tolerance resistors or
better to keep the performance optimized.
10.2.1.2.1.2 Bypass Capacitor (CBYPASS) and Start-Up Time
The internal voltage divider at the BYPASS pin of this device sets a mid-supply voltage for internal references
and sets the output common mode voltage to VDD/2. Adding a capacitor to this pin filters any noise into this pin
and increases the kSVR. C(BYPASS)also determines the rise time of VO+ and VO– when the device is taken out of
shutdown. The larger the capacitor, the slower the rise time. Although the output rise time depends on the
bypass capacitor value, the device passes audio 4 μs after taken out of shutdown and the gain is slowly ramped
up based on C(BYPASS).
To minimize pops and clicks, design the circuit so the impedance (resistance and capacitance) detected by both
inputs, IN+ and IN–, is equal.
10.2.1.2.1.3 Input Capacitor (CI)
The TPA6205A1 does not require input coupling capacitors if using a differential input source that is biased from
0.5 V to VDD – 0.8 V. Use 1% tolerance or better gain-setting resistors if not using input coupling capacitors.
In the single-ended input application an input capacitor, CI, is required to allow the amplifier to bias the input
signal to the proper DC level. In this case, CI and RI form a high-pass filter with the corner frequency determined
in Equation 24.
1
fc =
2pRICI
(24)
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–3 dB
fc
Figure 33. CI and RI High-Pass Filter Cutoff Frequency
The value of CI is important to consider as it directly affects the bass (low frequency) performance of the circuit.
Consider the example where RI is 10 kΩ and the specification calls for a flat bass response down to 100 Hz.
Equation 24 is reconfigured as Equation 25.
1
CI =
2pRIfc
(25)
In this example, CI is 0.16 μF, so one would likely choose a value in the range of 0.22 μF to 0.47 μF. A further
consideration for this capacitor is the leakage path from the input source through the input network
(RI , CI) and the feedback resistor (RF ) to the load. This leakage current creates a DC offset voltage at the input
to the amplifier that reduces useful headroom, especially in high gain applications. For this reason, a ceramic
capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor should face
the amplifier input in most applications, as the dc level there is held at VDD/2, which is likely higher than the
source dc level. It is important to confirm the capacitor polarity in the application.
10.2.1.2.1.4 Decoupling Capacitor (CS)
The TPA6205A1 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to
ensure the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also prevents
oscillations for long lead lengths between the amplifier and the speaker. For higher frequency transients, spikes,
or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1 μF to 1
μF, placed as close as possible to the device VDD lead works best. For filtering lower frequency noise signals, a
10-μF or greater capacitor placed near the audio power amplifier also helps, but is not required in most
applications because of the high PSRR of this device.
10.2.1.2.2 Using Low-ESR Capacitors
Low-ESR capacitors are recommended throughout this applications section. A real (as opposed to ideal)
capacitor can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this
resistor minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this
resistance the more the real capacitor behaves like an ideal capacitor.
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1.8
1.8
1.6
1.6
1.4
1.4
1.2
I DD - Supply Current - mA
PO - Output Power - W
10.2.1.3 Application Curves
THD+N = 10%
1
0.8
0.6
THD+N = 1%
0.4
0.2
0
1.2
1
0.8
0.6
0.4
0.2
0
2.5
3
3.5
4
4.5
0 0.5 1
5
1.5 2 2.5 3 3.5
4 4.5 5
5.5
VDD - Supply V oltage - V
VDD - Supply V oltage - V
Figure 34. Output Power vs Supply Voltage
Figure 35. Supply Current vs Supply Voltage
10.2.2 TPA6205A1 With Differential Input and Input Capacitors
The TPA6205A1 supports differential input operation with input capacitors. This section describes the design
considerations for this application.
VDD
RF
CI
IN
+
RI
IN-
RI
IN+
CI
Cs
_
VO+
VO-
+
RF
SHUTDOWN
To Battery
GND
Bias
Circuitry
C(BYPASS)
(Optional)
Figure 36. Differential Input Application Schematic Optimized With Input Capacitors
10.2.2.1 Design Requirements
Refer to the Design Requirements.
10.2.2.2 Detailed Design Procedure
Refer to the Detailed Design Procedure.
10.2.2.3 Application Curves
Refer to the Application Curves.
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10.2.3 TPA6205A1 With Single-Ended Input
The TPA6205A1 can be used with single-ended inputs, using Input capacitors. This section describes the design
considerations for this application.
VDD
RF
CI
RI
IN-
IN
RI
CI
IN+
Cs
_
VO+
VO-
+
RF
SHUTDOWN
To Battery
GND
Bias
Circuitry
C(BYPASS)
(Optional)
Figure 37. Single-Ended Input Application Schematic
10.2.3.1 Design Requirements
Refer to the Design Requirements.
10.2.3.2 Detailed Design Procedure
Refer to the Detailed Design Procedure.
10.2.3.3 Application Curves
Refer to the Application Curves.
11 Power Supply Recommendations
The TPA6205A1 is designed to operate from an input voltage supply range between 2.5-V and 5.5-V. Therefore,
the output voltage range of power supply should be within this range and well regulated. The current capability of
upper power should not exceed the maximum current limit of the power switch.
11.1
Power Supply Decoupling Capacitors
The TPA6205A1 requires adequate power supply decoupling to ensure a high efficiency operation with low total
harmonic distortion (THD). Place a low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1 μF,
within 2 mm of the VDD pin. This choice of capacitor and placement helps with higher frequency transients,
spikes, or digital hash on the line. In addition to the 0.1 μF ceramic capacitor, is recommended to place a 2.2 μF
to 10 μF capacitor on the VDD supply trace. This larger capacitor acts as a charge reservoir, providing energy
faster than the board supply, thus helping to prevent any drop in the supply voltage.
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12 Layout
12.1 Layout Guidelines
Placing the decoupling capacitors as close as possible to the device is important for the efficiency of the class-D
amplifier. Any resistance or inductance in the trace between the device and the capacitor can cause a loss in
efficiency.
For the DRB (QFN/SON) and DGN (MSOP) to presence of voids within the exposed thermal pad
interconnection. Total elimination is difficult, but the design of the exposed pad stencil is key. The stencil design
proposed in the Texas Instruments application note QFN/SON PCB Attachment (SLUA271) enables out-gassing
of the solder paste during reflow as well as regulating the finished solder thickness. Typically the solder paste
coverage is approximately 50% of the pad area.
In making the pad size for the BGA balls, it is recommended that the layout use soldermask-defined (SMD) land.
With this method, the copper pad is made larger than the desired land area, and the opening size is defined by
the opening in the solder mask material. The advantages normally associated with this technique include more
closely controlled size and better copper adhesion to the laminate. Increased copper also increases the thermal
performance of the IC. Better size control is the result of photo imaging the stencils for masks. Small plated vias
should be placed near the center ball connecting ball B2 to the ground plane. Added plated vias and ground
plane act as a heatsink and increase the thermal performance of the device. Figure 38 shows the appropriate
diameters for a 2 mm × 2 mm MicroStar Junior™ BGA layout.
It is very important to keep the TPA6205A1 external components very close to the TPA6205A1 to limit noise
pickup. The TPA6205A1 layout is shown in the next section as a layout example.
0.38 mm
0.25 mm
0.28 mm
C1
B1
C2
B2
C3
B3
A1
VIAS to Ground Plane
A3
Solder Mask
Paste Mask (Stencil)
Copper Trace
Figure 38. MicroStar Junior™ BGA Recommended Layout
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12.2 Layout Example
SHUTDOWN
IN+
OUT C1
B1
C2
B2
C3
B3
A1
Decoupling capacitor
placed as close as
possible to the device
A3
TPA6205A1
IN -
OUT +
Top Layer Ground Plane
Top Layer Traces
Pad to Top Layer Ground Plane
Via to Power Supply
Via to Bottom Layer Ground Plane
Figure 39. TPA6205A1 BGA Layout
OUT -
SHUTDOWN
IN+
1
8
2
7
3
6
4
5
IN -
TPA6205A1
Top Layer Ground Plane
Top Layer Traces
Pad to Top Layer Ground Plane
Thermal Pad
Via to Bottom Layer Ground Plane
Via to Power Supply
Decoupling capacitor
placed as close as
possible to the device
OUT +
Figure 40. TPA6205A1 HVSSOP Layout
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Layout Example (continued)
SHUTDOWN
2
7
IN +
3
6
-
4
5
IN
OUT -
8
1
Decoupling capacitor
placed as close as
possible to the device
OUT +
TPA6205A1
Top Layer Ground Plane
Top Layer Traces
Pad to Top Layer Ground Plane
Thermal Pad
Via to Bottom Ground Plane
Via to Power Supply
Figure 41. TPA6205A1 VSON Layout
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13 Device and Documentation Support
13.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.2 Trademarks
MicroStar Junior, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
13.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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19-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPA6205A1DGN
ACTIVE
HVSSOP
DGN
8
80
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
AAPI
Samples
TPA6205A1DGNG4
ACTIVE
HVSSOP
DGN
8
80
RoHS & Green
Level-1-260C-UNLIM
-40 to 85
AAPI
Samples
TPA6205A1DGNR
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
AAPI
Samples
TPA6205A1DGNRG4
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AAPI
Samples
TPA6205A1DRBR
ACTIVE
SON
DRB
8
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
AAOI
Samples
TPA6205A1DRBT
ACTIVE
SON
DRB
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
AAOI
Samples
TPA6205A1NMBR
ACTIVE
NFBGA
NMB
8
2500
RoHS & Green
SNAGCU
Level-2-260C-1 YEAR
-40 to 85
AANI
Samples
NIPDAU
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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