Order
Now
Product
Folder
Support &
Community
Tools &
Software
Technical
Documents
Reference
Design
TPS1H100-Q1
SLVSCM2D – OCTOBER 2014 – REVISED DECEMBER 2019
TPS1H100-Q1 40-V, 100-mΩ Single-Channel Smart High-Side Power Switch
1 Features
•
•
1
•
•
•
•
•
•
•
•
•
•
•
•
Qualified for automotive applications
AEC-Q100 Qualified with the following results:
– Device temperature grade 1: –40°C to 125°C
ambient operating temperature range
– Device HBM ESD classification level H3A
– Device CDM ESD classification level C4B
Functional safety capable
– Documentation available to aid functional
safety system design
Single-channel smart high-side power switch with
full diagnostics
– Version A: open-drain status output
– Version B: current sense analog output
Wide operating voltage 3.5 to 40 V
Very-low standby current, VS,UVR, device turn on
VS,UVF
Undervoltage shutdown
VS falls down, VS < VS,UVF, device shuts off
VUV,hys
Undervoltage shutdown, hysteresis
5
40
V
3.5
5
V
3.5
3.7
4
V
3
3.2
3.5
V
0.5
V
OPERATING CURRENT
Inom
VIN = 5 V, VDIAG_EN = 0 V, no load
Nominal operating current
Ioff
Standby current
Ioff,diag
5
mA
VIN = 5 V, VDIAG_EN = 0 V, 10-Ω load
10
mA
VS = 13.5 V, VIN = VDIAG_EN = VCS = VCL =
VOUTPUT = 0 V, TJ = 25°C
0.5
µA
VS = 13.5 V, VIN = VDIAG_EN = VCS = VCL =
VOUTPUT = 0 V, TJ = 125°C
5
µA
1.2
mA
Standby current with diagnostic enabled VIN = 0 V, VDIAG_EN = 5 V
IN from high to low, if deglitch time > toff,deg,
enters into standby mode.
(1)
toff,deg
Standby mode deglitch time
Ileak,out
Off-state output leakage current
2
VS = 13.5 V, VIN = VOUTPUT = 0, TJ = 25°C
ms
0.5
µA
3
µA
100
mΩ
VS > 5 V, TJ = 150°C
166
mΩ
VS = 3.5 V, TJ = 25°C
120
mΩ
13
A
VS = 13.5 V, VIN = VOUTPUT = 0, TJ = 125°C
POWER STAGE
VS > 5 V, TJ = 25°C
RDS-ON
On-state resistance
Ilim,nom
Internal current limit
Ilim,tsd
Current limit during thermal shutdown
VDS
Clamp drain-to-source voltage internally
clamped
80
7
Internal current limit, thermal cycling condition
5
External current limit, thermal cycling
condition; Percentage of current limit set
value
A
50%
50
70
V
OUTPUT DIODE CHARACTERISTICS
VF
Drain-to-source diode voltage
VIN = 0, IOUT = −0.2 A
Irev1
Continuous reverse current when
reverse polarity (2)
Irev2
Continuous reverse current when
VOUT > VS + Vdiode (2)
0.7
V
t < 60 s, VS = 13.5 V, GND pin 1-kΩ resistor
in parallel with diode. TJ = 25°C. See Irev1 test
condition (Figure 6).
4
A
t < 60 s, VS = 13.5 V. TJ = 25°C. See Irev2
test condition (Figure 7).
2
A
LOGIC INPUT (IN AND DIAG_EN)
Vlogic,h
Input or DIAG_EN high-level voltage
Vlogic,l
Input or DIAG_EN low-level voltage
Vlogic,hys
Input or DIAG_EN hysteresis voltage
250
mV
Rpd,in
Input pulldown resistor
500
kΩ
Rpd,diag
Diag pulldown resistor
150
kΩ
(1)
(2)
6
2
V
0.8
V
Value is specified by design, not subject to production test.
Value is based on the minimum value of the 10 pcs/3 lots samples.
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Product Folder Links: TPS1H100-Q1
TPS1H100-Q1
www.ti.com
SLVSCM2D – OCTOBER 2014 – REVISED DECEMBER 2019
Electrical Characteristics (continued)
5 V < VS < 40 V; –40°C < TJ < 150°C unless otherwise specified
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
100
µA
2.6
V
–50
µA
DIAGNOSTICS
Iloss,gnd
Loss-of-ground output leakage current
Vol,off
Open-load detection threshold in offstate
VIN = 0 V, When VS – VOUT < Vol,off, duration
longer than tol,off. Open load detected.
Iol,off
Off-state output sink current with open
load
VIN = 0 V, VS = VOUT = 13.5 V, TJ = 125°C.
tol,off
Open-load detection-threshold deglitch
time in off state
VIN = 0 V, When VS – VOUT < Vol,off, duration
longer than tol,off. Open load detected.
Iol,on
Open-load detection threshold in on
state
VIN = 5 V, when IOUT < Iol,on, duration longer
than tol,on. Open load detected.
Version A only
tol,on
Open-load detection-threshold deglitch
time in on-state
VIN = 5 V, when IOUT < Iol,on, duration longer
than tol,on. Open load detected.
Version A only
VST
Status low output voltage
IST = 2 mA
Version A only
TSD
Thermal shutdown threshold
175
TSD,rst
Thermal shutdown status reset
155
Tsw
Thermal swing shutdown threshold
60
Thys
Hysteresis for resetting the thermal
shutdown and swing
10
1.4
1.8
600
2
6
µs
10
700
mA
µs
0.4
V
°C
CURRENT SENSE (VERSION B) AND CURRENT LIMIT
K
Current sense current ratio
KCL
Current limit current ratio
dK/K
500
2000
Current-sense accuracy
Iload ≥ 5 mA
–80
80
Iload ≥ 25 mA
–10
10
Iload ≥ 50 mA
–7
7
Iload ≥ 0.1 A
–5
5
Iload ≥ 1 A
dKCL/KCL
External current-limit accuracy (3) (4)
VCS,lin
Linear current sense voltage range (1)
IOUT,lin
Linear output current range
3
–20
20
Ilimit ≥ 1.6 A
–14
14
0
4
V
4
A
VS ≥ 5 V, VCS,lin ≤ 4 V
VCS,H
Current-sense fault high voltage
ICS,H
Current sense fault condition current
VCL,th
Current limit internal threshold voltage (1)
ICS,leak
Current sense leakage current in
disabled mode
(3)
(4)
–3
Ilimit ≥ 0.5 A
VS ≥ 5 V
(1)
%
0
VS ≥ 7 V
4.3
VS ≥ 5 V
Min(VS –
0.8, 4.3)
VCS = 4.3 V, VS > 7 V
4.75
%
4.9
4.9
10
V
mA
1.233
V
VIN = 5 V, Rload = 10 Ω, VDIAG_EN = 0 V, TJ =
125°C
1
µA
VIN = 0 V, VDIAG_EN = 0 V, TJ = 125°C
1
µA
External current-limit accuracy is only applicable to overload conditions greater than 1.5× the current-limit setting.
External current-limit setting is recommended to be higher than 500 mA.
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Product Folder Links: TPS1H100-Q1
7
TPS1H100-Q1
SLVSCM2D – OCTOBER 2014 – REVISED DECEMBER 2019
www.ti.com
6.6 Timing Requirements – Current Sense Characteristics (1)
MIN
NOM
MAX
UNIT
tCS,off1
CS settling time
from DIAG disabled
VIN = 5 V, Iload ≥ 5 mA. VDIAG_EN from 5 to 0 V. CS to 10% of sense
value.
10
µs
tCS,on1
CS settling time
from DIAG enabled
VIN = 5 V, Iload ≥ 5 mA. VDIAG_EN from 0 to 5 V. CS to 90% of sense
value.
10
µs
tCS,off2
CS settling time
from IN falling edge
VDIAG_EN = 5 V, Iload ≥ 5 mA. IN from 5 to 0 V. CS to 10% of sense
value.
10
µs
VDIAG_EN = 5 V, Iload ≥ 5 mA. IN from 5 to 0 V. Current limit triggered.
180
µs
tCS,on2
CS settling time
from IN rising edge
VVS = 13.5 V, VDIAG_EN = 5 V, Iload ≥ 100 mA. VIN from 0 to 5 V. CS to
90% of sense value.
150
µs
(1)
Value specified by design, not subject to production test.
In
Iout
Diag-En
CS
Tcs, on2
Tcs, off1
Tcs, on1
Tcs, off2
Figure 2. CS Delay Characteristics
Open
Load
Open Load
In
Vcs,H
CS
Tol,off
ST
Tol,on
Tol,off
Figure 3. Open-Load Blanking Time Characteristics
VS
IS
IN
IIN
ST
IST
DIAG_EN
CL
CS
ICS
GND
Vout
ICL
IGND
VCS
VCL
VDIAG
VST
VIN
IOUT
Vs
OUT
IDIAG
Figure 4. Pin Current and Voltage Conventions
8
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Product Folder Links: TPS1H100-Q1
TPS1H100-Q1
www.ti.com
SLVSCM2D – OCTOBER 2014 – REVISED DECEMBER 2019
6.7 Switching Characteristics
VVS = 13.5 V, Rload = 10 Ω, over operating free-air temperature range (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
td,ON
Turn-on delay time
IN rising edge to VOUT = 10%, DIAG_EN high
20
50
td,OFF
Turn-off delay time
IN falling edge to VOUT = 90%, DIAG_EN high
20
50
µs
dV/dtON
Slew rate on
VOUT = 10% to 90%, DIAG_EN high
0.1
0.5
V/µs
dV/dtOFF
Slew rate off
VOUT = 90% to 10%, DIAG_EN high
0.1
0.5
V/µs
–0.15
0.15
V/µs
Slew rate on and off matching
(1)
µs
Value specified by design, not subject to production test.
In
90%
Vout
90%
10%
10%
Td,ON dV/dtON
Td,OFF dV/dtOFF
Figure 5. Switching Characteristics Diagram
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Product Folder Links: TPS1H100-Q1
9
TPS1H100-Q1
SLVSCM2D – OCTOBER 2014 – REVISED DECEMBER 2019
www.ti.com
DRAIN
Output
Clamp
SOURCE
Load
GND
VBAT
Rgnd
Dgnd
Figure 6. Irev1 Test Condition
Output
Clamp
DRAIN
VBAT
SOURCE
Load
GND
Rgnd
Dgnd
Figure 7. Irev2 Test Condition
10
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Product Folder Links: TPS1H100-Q1
TPS1H100-Q1
www.ti.com
SLVSCM2D – OCTOBER 2014 – REVISED DECEMBER 2019
6.8 Typical Characteristics
All the following data are based on the mean value of the three lots samples, VVS = 13.5 V if not specified.
4
10
Vs,uvr
Vs,uvf
Inom(no load)
Inom(10-O load)
8
Current (mA)
Voltage (V)
3.8
3.6
3.4
3.2
3
-40
6
4
2
-15
10
35
60
Temperature (°C)
85
0
-40
110 125
Figure 8. VVS,UVR and VVS,UVF
Ioff
Ileak,out
85
110 125
D002
1
Current (mA)
Current (µA)
35
60
Temperature (°C)
1.2
0.2
0.15
0.1
0.05
0
-40
10
Figure 9. Inom With No Load and 10-Ω Load
0.3
0.25
-15
D001
0.8
0.6
0.4
0.2
-15
10
35
60
Temperature (°C)
85
0
-40
110 125
-15
10
D003
Figure 10. Ioff and Ileak,out
35
60
Temperature (°C)
85
110 125
D004
Figure 11. Ioff,diag
0.9
1.8
Vlogic,h
Vlogic,l
1.6
0.8
Voltage (V)
Voltage (V)
1.4
1.2
0.7
1
0.6
0.8
0.6
-40
-15
10
35
60
Temperature (°C)
85
110 125
0.5
-40
-15
D005
Figure 12. Vlogic,h and Vlogic,l
10
35
60
Temperature (°C)
85
110 125
Figure 13. VF
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Product Folder Links: TPS1H100-Q1
D006
11
TPS1H100-Q1
SLVSCM2D – OCTOBER 2014 – REVISED DECEMBER 2019
www.ti.com
Typical Characteristics (continued)
All the following data are based on the mean value of the three lots samples, VVS = 13.5 V if not specified.
65
130
Resistance (mO)
115
Voltage (V)
60
55
Rdson_VS_3P5V
Rdson_VS_5V
Rdson_VS_13P5
Rdson_VS_40V
100
85
70
50
-40
-15
10
35
60
Temperature (°C)
85
55
-40
110 125
-15
10
D007
Figure 14. VDS, clamp
35
60
Temperature (°C)
85
110 125
D008
Figure 15. RDSON
11
45
40
Time (µs)
Current (A)
10.5
10
35
30
9.5
25
TD_On
TD_Off
9
-40
-15
10
35
60
Temperature (°C)
85
20
-40
110 125
-15
10
D009
Figure 16. Ilim,nom
35
60
Temperature (°C)
85
110 125
D010
Figure 17. TDon and TDoff
0.4
5
dV/dtON
dV/dtOFF
4.9
4.8
Voltage (V)
Slew Rate (V/µS)
0.38
0.36
0.34
4.7
4.6
4.5
0.32
4.4
0.3
-40
-15
10
35
60
Temperature (°C)
85
110 125
4.3
-40
-15
D011
Figure 18. dV/dtON and dV/dtOFF
12
Submit Documentation Feedback
10
35
60
Temperature (°C)
85
110 125
D012
Figure 19. VCS,h
Copyright © 2014–2019, Texas Instruments Incorporated
Product Folder Links: TPS1H100-Q1
TPS1H100-Q1
www.ti.com
SLVSCM2D – OCTOBER 2014 – REVISED DECEMBER 2019
Typical Characteristics (continued)
All the following data are based on the mean value of the three lots samples, VVS = 13.5 V if not specified.
9
1.95
1.9
Current (mA)
Voltage (V)
8
1.85
1.8
7
6
1.75
1.7
-40
-15
10
35
60
Temperature (°C)
85
110 125
5
-40
-15
D013
Figure 20. Vol,off
10
35
60
Temperature (°C)
85
110 125
D014
Figure 21. Iol,on
20%
10%
15%
8%
6%
10%
4%
5%
2%
0
0
-5%
-2%
-4%
-10%
-6%
-15%
-20%
-40
-8%
-10
20
50
Temperature (°C)
80
110 125
-10%
-40
-10
D015
Figure 22. KCS = 5 mA, 13.5 V
10%
8%
8%
6%
6%
4%
4%
2%
2%
0
0
-2%
-2%
-4%
-4%
-6%
-6%
-8%
-8%
-10
20
50
Temperature (°C)
80
80
110 125
D017
Figure 23. KCS = 25 mA, 13.5 V
10%
-10%
-40
20
50
Temperature (°C)
110 125
-10%
-40
D019
Figure 24. KCS = 50 mA, 13.5 V
-10
20
50
Temperature (°C)
80
110 125
Figure 25. KCS = 100 mA, 13.5 V
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Product Folder Links: TPS1H100-Q1
D016
13
TPS1H100-Q1
SLVSCM2D – OCTOBER 2014 – REVISED DECEMBER 2019
www.ti.com
Typical Characteristics (continued)
All the following data are based on the mean value of the three lots samples, VVS = 13.5 V if not specified.
10%
10%
8%
8%
6%
6%
4%
4%
2%
2%
0
0
-2%
-2%
-4%
-4%
-6%
-6%
-8%
-8%
-10%
-40
-10
20
50
Temperature (°C)
80
110 125
-10%
-40
-10
D018
Figure 26. KCS = 1 A, 13.5 V
20
50
Temperature (°C)
80
110 125
D020
Figure 27. KCL = 0.5 A, 13.5 V
10%
8%
6%
4%
2%
0
-2%
-4%
-6%
-8%
-10%
-40
-10
20
50
Temperature (°C)
80
110 125
D021
Figure 28. KCL = 1.6 A, 13.5 V
14
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Product Folder Links: TPS1H100-Q1
TPS1H100-Q1
www.ti.com
SLVSCM2D – OCTOBER 2014 – REVISED DECEMBER 2019
7 Detailed Description
7.1 Overview
The TPS1H100-Q1 is a single-channel, fully-protected, high-side power switch with an integrated NMOS power
FET and charge pump. Full diagnostics and high-accuracy current-sense features enable intelligent control of the
load. A programmable current-limit function greatly improves the reliability of the whole system. The device
diagnostic reporting has two versions to support both digital status and analog current-sense output, both of
which can be set to the high-impedance state when diagnostics are disabled, for multiplexing the MCU analog or
digital interface among devices.
For version A, the digital status report is implemented with an open-drain structure. When a fault condition
occurs, it pulls down to GND. A 3.3- or 5-V external pullup is required to match the microcontroller supply level.
For version B, high-accuracy current sensing allows a better real-time monitoring effect and more-accurate
diagnostics without further calibration. A current mirror is used to source 1 / K of the load current, which is
reflected as voltage on the CS pin. K is a constant value across the temperature and supply voltage. The currentsensing function operates normally within a wide linear region from 0 to 4 V. The CS pin can also report a fault
by pulling up the voltage of VCS,h.
The external high-accuracy current limit allows setting the current limit value by application. It highly improves the
reliability of the system by clamping the inrush current effectively under start-up or short-circuit conditions. Also, it
can save system costs by reducing PCB trace, connector size, and the preceding power-stage capacity. An
internal current limit is also implemented in this device. The lower value of the external or internal current-limit
value is applied.
An active drain and source voltage clamp is built in to address switching off the energy of inductive loads, such
as relays, solenoids, pumps, motors, and so forth. During the inductive switching-off cycle, both the energy of the
power supply (EBAT) and the load (ELOAD) are dissipated on the high-side power switch itself. With the benefits of
process technology and excellent IC layout, the TPS1H100-Q1 device can achieve excellent power dissipation
capacity, which can help save the external free-wheeling circuitry in most cases. See Inductive-Load SwitchingOff Clamp for more details.
Short-circuit reliability is critical for smart high-side power-switch devices. The standard of AEC-Q100-012 is to
determine the reliability of the devices when operating in a continuous short-circuit condition. Different grade
levels are specified according to the pass cycles. This device is qualified with the highest level, Grade A, 1
million times short-to-GND certification.
The TPS1H100-Q1 device can be used as a high-side power switch for a wide variety of resistive, inductive, and
capacitive loads, including the low-wattage bulbs, LEDs, relays, solenoids, and heaters.
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Product Folder Links: TPS1H100-Q1
15
TPS1H100-Q1
SLVSCM2D – OCTOBER 2014 – REVISED DECEMBER 2019
www.ti.com
7.2 Functional Block Diagram
DRAIN (VS)
Internal LDO
Charge Pump
VDS Clamp
IN
Internal
Reference
Gate Driver
DIAG_EN
ST
Diagnostics
and Protection
Open Load
Detection
Current Limit
CL
Thermal
Monitor
Current Sense
SOURCE(OUT)
CS
GND
7.3 Feature Description
7.3.1 Accurate Current Sense
For version B, the high-accuracy current-sense function is internally implemented, which allows a better real-time
monitoring effect and more-accurate diagnostics without further calibration. A current mirror is used to source
1 / K of the load current, flowing out to the external resistor between the CS pin and GND, and reflected as
voltage on the CS pin.
K is the ratio of the output current and the sense current. It is a constant value across the temperature and
supply voltage. Each device was internally calibrated while in production, so post-calibration by users is not
required in most cases.
16
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Product Folder Links: TPS1H100-Q1
TPS1H100-Q1
www.ti.com
SLVSCM2D – OCTOBER 2014 – REVISED DECEMBER 2019
Feature Description (continued)
4A
1A
100 mA
50 mA
25 mA
5 mA
dK/K = ±3%
dK/K = ±5%
dK/K = ±7%
dK/K = ±10%
dK/K = ±80%
0A
Figure 29. Current-Sense Accuracy
Ensure the CS voltage is in the linear region (0 to 4 V) during normal operation. Calculate RCS with Equation 1.
VCS VCS u K
RCS
ICS
Iout
(1)
Also, when a fault condition occurs, CS works as a diagnostics report pin. When an open load or short to battery
occurs in the on-state, VCS almost equals 0. When current limit, thermal shutdown/swing, open load, or short to
battery in the off-state occurs, the voltage is pulled up to VCS,h. Figure 30 shows a typical current-sense voltage
according to the operating conditions, including fault conditions.
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Product Folder Links: TPS1H100-Q1
17
TPS1H100-Q1
SLVSCM2D – OCTOBER 2014 – REVISED DECEMBER 2019
www.ti.com
Feature Description (continued)
Current Sense
Voltage
Vcs,H
ADC Full Scale
Range
Max Normal
Operating Current
Operating
Range
Open Load Current
On-state:
open load/short to battery
Normal
Over
current
On-state: Current limit, thermal fault
Off-state: Open load/ short to battery
Figure 30. Voltage Indication on the Current-Sense Pin
VBAT
VS
Iout/K
Iout/Kcl
CURRENT
CLAMP
FAULT
Iout
t
Vcs,H
+
CS
CL
Vcl,th
OUT
Rcs
RCL
Figure 31. Current-Sense and Current-Limit Block Diagram
7.3.2 Programmable Current Limit
A high-accuracy current limit allows higher reliability, which protects the power supply during short circuit or
power up. Also, it can save system costs by reducing PCB traces, connector size, and the capacity of the
preceding power stage.
Current limit offers protection from overstressing to the load and integrated power FET. Current limit holds the
current at the set value, and pulls up the CS pin to VCS,h as a diagnostic report. The two current-limit thresholds
are:
• External programmable current limit -- An external resistor is used to convert a proportional load current into a
voltage, which is compared with an internal reference voltage, Vth,cl. When the voltage on the CL pin exceeds
Vth.cl, a closed loop steps in immediately. VGS voltage regulates accordingly, leading to the Vds voltage
regulation. When the closed loop is set up, the current is clamped at the set value. The external
programmable current limit provides the capability to set the current-limit value by application.
18
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Product Folder Links: TPS1H100-Q1
TPS1H100-Q1
www.ti.com
SLVSCM2D – OCTOBER 2014 – REVISED DECEMBER 2019
Feature Description (continued)
•
Internal current limit -- The internal current limit is fixed and typically 10 A. To use the internal current limit for
large-current applications, tie the CL pin directly to the device GND.
Both the internal current limit (Ilim,nom) and external programmable current limit are always active when VVS is
powered and IN is high. The lower one (of Ilim,nom and the external programmable current limit) is applied as the
actual current limit.
Note that if a GND network is used (which leads to the level shift between the device GND and board GND), the
CL pin must be connected with device GND. Calculate RCL with Equation 2.
VCL,th Iout
VCL,th u K CL
o RCL
ICL
RCL
K CL
Iout
(2)
For better protection from a hard short-to-GND condition (when VS and input are high and a short to GND
happens suddenly), an open-loop fast-response behavior is set to turn off the channel, before the current-limit
closed loop is set up. The open-loop response time is around 1 µs. With this fast response, the device can
achieve better inrush-suppression performance.
7.3.3 Inductive-Load Switching-Off Clamp
When an inductive load is switching off, the output voltage is pulled down to negative, due to the inductance
characteristics. The power FET may break down if the voltage is not clamped during the current-decay period. To
protect the power FET in this situation, internally clamp the drain-to-source voltage, namely VDS,clamp, the clamp
diode between the drain and gate.
9DS,clamp 9BAT ± 9OUT
(3)
During the current-decay period (TDECAY), the power FET is turned on for inductance-energy dissipation. Both the
energy of the power supply (EBAT) and the load (ELOAD) are dissipated on the high-side power switch itself, which
is called EHSD. If resistance is in series with inductance, some of the load energy is dissipated in the resistance.
(HSD (BAT (LOAD (BAT (L ± (R
(4)
From the high-side power switch’s view, EHSD equals the integration value during the current-decay period.
TDECAY
EHSD
³0
TDECAY
§ R u IOUT(MAX)
L
u ln ¨
¨
R
VOUT
©
(HSD
/u
VDS,clamp u IOUT (t)dt
VBAT
VOUT
R2
(5)
VOUT ·
¸
¸
¹
(6)
ª
§ R u IOUT(MAX)
u «5 u ,OUT(MAX) ± 9OUT OQ ¨
¨
VOUT
«¬
©
VOUT · º
¸¸ »
¹ »¼
(7)
When R approximately equals 0, EHSD can be given simply as:
EHSD
VBAT
VOUT
1
2
u L u I OUT(MAX)
2
2
R
(8)
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Product Folder Links: TPS1H100-Q1
19
TPS1H100-Q1
SLVSCM2D – OCTOBER 2014 – REVISED DECEMBER 2019
www.ti.com
Feature Description (continued)
VBAT
DRAIN
IN
-
L
+
R
SOURCE
GND
Figure 32. Driving Inductive Load
INPUT
VBAT
VOUT
VDS, clamp
EHSD
IOUT
tDECAY
Figure 33. Inductive-Load Switching-Off Diagram
As discussed previously, when switching off, battery energy and load energy are dissipated on the high-side
power switch, which leads to the large thermal variation. For each high-side power switch, the upper limit of the
maximum safe power dissipation depends on the device intrinsic capacity, ambient temperature, and board
dissipation condition. TI provides the upper limit of single-pulse energy that devices can tolerate under the test
condition: VVS = 13.5 V, inductance from 0.1 mH to 400 mH, R = 0 Ω, FR4 2s2p board, 2- × 70-μm copper, 2- ×
35-μm copper, thermal pad copper area 600 mm2.
For one dedicated inductance, see Figure 34. If the maximum switching-off current is lower than the current
value shown on the curve, the internal clamp function can be used for the demagnetization energy dissipation. If
not, external free-wheeling circuitry is necessary for device protection.
20
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Product Folder Links: TPS1H100-Q1
TPS1H100-Q1
www.ti.com
SLVSCM2D – OCTOBER 2014 – REVISED DECEMBER 2019
Feature Description (continued)
12
TA = 25°C
TA = 125°C
11
Maximum Current (A)
10
9
8
7
6
5
4
3
2
1
0
0.1 0.2
0.5
1
2 3 4 5 7 10 20 30 50 100 200 400
Inductance Range (mH)
D026
Figure 34. Maximum Current vs Inductance Range
7.3.4 Full Protections and Diagnostics
Table 1 is when DIAG_EN enabled. When DIAG_EN is low, current sense or ST is disabled accordingly. The
output is in high-impedance mode. Refer to Table 2 for details.
Table 1. Fault Table
CONDITIONS
Normal
Short to GND
Open load (1)
Short to battery
Reverse polarity
IN
OUT
ST
(Version A)
CRITERION
CS
(Version B)
Diagnostics Recovery
L
L
H
0
H
H
H
In linear region
H
L
Current limit triggered.
L
VCS,h
AUTO
H
H
Version A: Output current < Iol,on
Version B: Judged by users
L (deglitch)
Almost 0
AUTO
L
H
VVS – VOUT < Vol,off
L (deglitch)
VCS,h (deglitch)
AUTO
Thermal shutdown
H
TSD triggered
L
VCS,h
Recovery when
temp < TSD,rst
Thermal swing
H
Tsw triggered
L
VCS,h
AUTO
(1)
Need external pullup resistor during off-state
Table 2. DIAG_EN Logic Table
DIAG_EN
IN Condition
HIGH
Protections and Diagnostics
ON
See Table 1
OFF
See Table 1
ON
Diagnostics disabled, protection normal
CS or ST is high Impedance
OFF
Diagnostics disabled, no protections
CS or ST is high impedance
LOW
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Product Folder Links: TPS1H100-Q1
21
TPS1H100-Q1
SLVSCM2D – OCTOBER 2014 – REVISED DECEMBER 2019
www.ti.com
7.3.4.1 Short-to-GND and Overload Detection
In the on state, the short-to-GND fault is reported as the low status output or VCS,h on CS, when a current limit is
triggered. The lower one of the internal and external set values is applied for the actual current limit. It is in autorecovery when the fault condition is cleared. If not cleared, thermal shutdown triggers to protect the power FET.
7.3.4.2 Open-Load Detection
In the on state for version A, if the current flowing through the output is less than Iol,on, the device recognizes an
open-load fault. For version B, faults are diagnosed by reading the voltage on the CS pin and judged by the user.
A benefit of high-accuracy current sense down to a verylow current range, this device can achieve a very low
open-load detection threshold, which correspondingly expands the normal operation region. TI suggests 10 mA
as the upper limit for the open-load detection threshold and 25 mA as the lower limit for the normal operation
current. In Figure 35, the recommended open-load detection region is shown as the dark-shaded region and the
light-shaded region is for normal operation. As a guideline, do not overlap these two regions.
Normal Operation
Region
27.5 mA
25 mA
10% Tolerance
22.5 mA
18 mA
80% Tolerance
On State, Open Load/
Short to Battery
10 mA
2 mA
Figure 35. On-State Open-Load Detection and Normal-Operation Diagram
In the off state, if a load is connected, the output voltage is pulled to 0 V. In the case of an open load, the output
voltage is close to the supply voltage, VS – VOUT < Vol,off. For version A, the ST pin goes low to indicate the fault
to the MCU. For version B, the CS pin is pulled up to VCS,h. There is always a leakage current Iol,off present on
the output, due to the internal logic control path or external humidity, corrosion, and so forth. Thus, TI
recommends an external pullup resistor to offset the leakage current. This pullup current should be less than the
output load current to avoid false detection in the normal operation mode. To reduce the standby current, TI
recommends always to use a switch in series with? the pullup resistor. TI recommends Rpu ≤ 15 kΩ.
VBAT
VS
OPEN LOAD
ST/CS
Vol,off
FAULT
Rpu
OUT
Figure 36. Open-Load Detection Circuit
22
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Product Folder Links: TPS1H100-Q1
TPS1H100-Q1
www.ti.com
SLVSCM2D – OCTOBER 2014 – REVISED DECEMBER 2019
7.3.4.3 Short-to-Battery Detection
Short-to-battery detectioin has the same detection mechanism and behavior as open-load detection, both in the
on-state and off-state. See the fault truth table, Table 1, for more details. In the on-state, the reverse current
flows through the FET instead of the body diode, leading to less power dissipation. Thus, the worst case for offstate is when reverse current occurs. In the off-state, if VOUT – VVS < VF, short to battery can be detected. (VF is
the body diode forward voltage and typically 0.7 V.) However, the reverse current does not occur. If VOUT – VVS >
VF, short to battery can be detected, and the reverse current should be lower than Irev2 to ensure the survival of
the device. TI recommends switching on the input for lower power dissipation or the reverse block circuitry for the
supply. See Reverse Current Protection for more external protection circuitry information.
7.3.4.4 Reverse-Polarity Detection
Reverse-polarity detection has the same detection mechanism and behavior as open-load detection, both in the
on-state and off-state. See the fault truth table, Table 1, for more details. In the on-state, the reverse current
flows through the FET instead of the body diode, leading to less power dissipation. Thus, the worst case off-state
is when reverse current occurs. In off-state, the reverse current should be lower than Irev1 to ensure the survival
of the device. See Reverse Current Protection for more external protection circuitry information.
7.3.4.5 Thermal Protection Behavior
Both the absolute temperature thermal shutdown and the dynamic temperature thermal swing diagnostic and
protection are built into the device to increase the maximum reliability of the power FET. Thermal swing is active
when the temperature of the power FET is increasing sharply, that is ΔT = TDMOS – TLogic > Tsw, then the output is
shut down, and the ST pin goes low, or the CS pin is pulled up to VCS,h. It auto-recovers and clears the fault
signal until ΔT = TDMOS – TLogic < Tsw – Thys. Thermal swing function improves device reliability against repetitive
fast thermal variation, as shown in Figure 37. Multiple thermal swings are triggered before thermal shutdown
happens. Thermal shutdown is active when absolute temperature T > TSD. When active, the output is shut down,
and the ST pin goes low, or the CS pin is pulled up to VCS,h. The output is auto-recovered when T < TSD – Thys;
the current limit is reduced to Ilim,tsd, or half of the programmable current limit value, to avoid repeated thermal
shutdown. However, the thermal shutdown fault signal and half-current limit value are not cleared until the
junction temperature decreases to less than TSD,rst.
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Product Folder Links: TPS1H100-Q1
23
TPS1H100-Q1
SLVSCM2D – OCTOBER 2014 – REVISED DECEMBER 2019
www.ti.com
In
TSD
TSD
Thys
Thys
TSD,r
TSD,rst
st
Thys
Tsw
Junction
Temperature
Ilim
1/2Ilim
Output
Current
Vcs,H
VCS
ST
Figure 37. Thermal Behavior
7.3.4.6 UVLO Protection
The device monitors the supply voltage VVS to prevent unpredicted behaviors in the event that the supply voltage
is too low. When the supply voltage falls down to VVS,UVF, the output stage is shut down automatically. When the
supply rises up to VVS,UVR, the device turns on.
24
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Product Folder Links: TPS1H100-Q1
TPS1H100-Q1
www.ti.com
SLVSCM2D – OCTOBER 2014 – REVISED DECEMBER 2019
7.3.4.7 Loss of GND Protection
When loss of GND occurs, output is turned off regardless of whether the input signal is high or low.
Case 1 (loss of device GND): Loss of GND protection is active when the Tab, IC_GND, and current limit GND are
one trace connected to the board GND, as shown in Figure 38. Tab floating is also a choice.
VBAT
DRAIN
IN
5V
ST
Version A
MCU
DIAG_EN
SOURCE
CS
Version B
Load
NC
(Floating)
CL
Tab
GND
Figure 38. Loss of Device GND
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Product Folder Links: TPS1H100-Q1
25
TPS1H100-Q1
SLVSCM2D – OCTOBER 2014 – REVISED DECEMBER 2019
www.ti.com
Case 2 (loss of module GND): When the whole ECU module GND is lost, protections are also active. At this
condition, the load GND remains connected.
VBAT
DRAIN
IN
5V
ST
Version A
MCU
DIAG_EN
SOURCE
CS
Version B
NC
(Floating)
CL
Load
Tab
GND
Figure 39. Loss of Module GND
26
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Product Folder Links: TPS1H100-Q1
TPS1H100-Q1
www.ti.com
SLVSCM2D – OCTOBER 2014 – REVISED DECEMBER 2019
7.3.4.8 Loss of Power Supply Protection
When loss of supply occurs, output is turned off regardless of whether the input is high or low. For a resistive or
capacitive load, loss-o-supply protection is easy to achieve due to no more power. The worst case is a charged
inductive load. In this case, the current is driven from all of the IOs to maintain the inductance output loop. TI
recommends either the MCU serial resistor plus the GND network (diode and resistor in parallel) or external freewheeling circuitry.
VBAT
IN
DRAIN
5V
ST
DIAG_EN
SOURCE
MCU
CS
D
L
NC
(Floating)
CL
Z
GND
Rgnd
Dgnd
Figure 40. Loss of Battery
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Product Folder Links: TPS1H100-Q1
27
TPS1H100-Q1
SLVSCM2D – OCTOBER 2014 – REVISED DECEMBER 2019
www.ti.com
7.3.4.9 Reverse Current Protection
Method 1: Block diode connected with VS. Both the device and load are protected when in reverse polarity.
VBAT
IN
Gate drive
and Clamp
STATUS
Version A
Output
Clamp
DRAIN
Logic and
Protection
DIAG_EN
SOURCE
CS
Version B
Current Sense/
Current Limit
Load
NC
(Floating)
CURRENT LIMIT
GND
Figure 41. Reverse Protection With Block Diode
28
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Product Folder Links: TPS1H100-Q1
TPS1H100-Q1
www.ti.com
SLVSCM2D – OCTOBER 2014 – REVISED DECEMBER 2019
Method 2 (GND network protection): Only the high-side device is protected under this connection. The load
reverse loop is limited by the load itself. Note when reverse polarity happens, the continuous reverse current
through the power FET should be less than Irev. Of the three types of ground pin networks, TI strongly
recommends type 3 (the resistor and diode in parallel). No matter what types of connection are between the
device GND and the board GND, if a GND voltage shift happens, ensure the following proper connections for the
normal operation:
• Leave the NC pin floating or connect to the device GND. TI recommends to leave floating.
• Connect the current limit programmable resistor to the device GND.
IN
Output
Clamp
Gate drive
and Clamp
STATUS
Version A
DRAIN
Logic and
Protection
DIAG_EN
SOURCE
CS
Version B
Current Sense/
Current Limit
Load
NC
(Floating)
CURRENT LIMIT
GND
Rgnd
GND
Network
VBAT
Dgnd
Figure 42. Reverse Protection With GND Network
•
Type 1 (resistor): The higher resistor value contributes to a better current limit effect when the reverse
battery or negative ISO pulses. However, it leads to higher GND shift during normal operation mode. Also,
consider the resistor’s power dissipation.
V
RGND d GNDshift
Inom
(9)
RGND t
±9CC
±,GND
where
•
•
•
•
•
VGNDshift is the maximum value for the GND shift, determined by the HSD and microcontroller. TI suggests a
value ≤ 0.6 V.
Inom is the nominal operating current.
–VCC is the maximum reverse voltage seen on the battery line.
–IGND is the maximum reverse current the ground pin can withstand, which is available in the Absolute
Maximum Ratings.
(10)
If multiple high-side power switches are used, the resistor can be shared among devices.
Type 2 (diode): A diode is needed to block the reverse voltage, which also brings a ground shift (≈ 600 mV).
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Product Folder Links: TPS1H100-Q1
29
TPS1H100-Q1
SLVSCM2D – OCTOBER 2014 – REVISED DECEMBER 2019
•
www.ti.com
However, an inductive load is not acceptable to avoid an abnormal status when switching off.
Type 3 (resistor and diode in parallel (recommended)): A peak negative spike may occur when the
inductive load is switching off, which may damage the HSD or the diode. So, TI recommends a resistor in
parallel with the diode when driving an inductive load. The recommended selection are 1-kΩ resistor in
parallel with an IF > 100-mA diode. If multiple high-side switches are used, the resistor and diode can be
shared among devices.
7.3.4.10 Protection for MCU I/Os
In many conditions, such as the negative ISO pulse, or the loss of battery with an inductive load, a negative
potential on the device GND pin may damage the MCU I/O pins [more likely, the internal circuitry connected to
the pins]. Therefore, the serial resistors between MCU and HSD are required.
Also, for proper protection against loss of GND, TI recommends 4.7 kΩ when using 3.3-V MCU I/Os; 10 kΩ is for
5-V applications.
VBAT
IN
5V
STATUS
Version A
MCU
Output
Clamp
Gate drive
and Clamp
Logic and
Protection
DIAG_EN
CS
Version B
DRAIN
SOURCE
Current Sense/
Current Limit
Load
NC
(Floating)
CURRENT
LIMIT
GND
Rgnd
Dgnd
Figure 43. MCU IO Protections
7.3.5 Diagnostic Enable Function
The diagnostic enable pin, DIAG_EN, offers multiplexing of the microcontroller diagnostic input for current sense
or digital status, by sharing the same sense resistor and ADC line or I/O port among multiple devices.
30
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Product Folder Links: TPS1H100-Q1
TPS1H100-Q1
www.ti.com
SLVSCM2D – OCTOBER 2014 – REVISED DECEMBER 2019
In addition, during the output-off period, the diagnostic disable function lowers the current consumption for the
standby condition. The three working modes in the device are normal mode, standby mode, and standby mode
with diagnostic. If off-state power saving is required in the system, the standby current is toff,deg. toff,deg is the standby-mode deglitch time, which is
used to avoid false triggering. Figure 44 shows a work-mode state-machine state diagram.
Standby Mode
(IN low, DIAG low)
DIAG_EN
high to low
DIAG_EN
low to high
Standby mode
with diagnostic
(IN low, DIAG high)
IN low to high
DIAG_EN low and
IN high to low and
t > toff,deg
IN high to low and
DIAG_EN high and
t > toff,deg
Normal Mode
(IN high)
IN low to high
Figure 44. Work-Mode State Machine
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Product Folder Links: TPS1H100-Q1
31
TPS1H100-Q1
SLVSCM2D – OCTOBER 2014 – REVISED DECEMBER 2019
www.ti.com
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The following discussion notes how to implement the device to distinguish the different fault modes and
implement a ? transient-pulse immunity test.
In some applications, open load, short to battery, and short to GND must be distinguished from each other. This
requires two steps.
8.2 Typical Application
Figure 45 shows an example of how to design the external circuitry parameters.
VBAT
RSER
IN
Output
Clamp
Gate drive
and Clamp
5V
ST
Version A
Logic and
Protection
DIAG_EN
MCU
RCS
CS
Version B
DRAIN
SOURCE
Current Sense/
Current Limit
Load
NC
(Floating)
CL
GND
RCL
GND Network
Rgnd
Dgnd
Figure 45. Typical Application Circuitry
32
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Product Folder Links: TPS1H100-Q1
TPS1H100-Q1
www.ti.com
SLVSCM2D – OCTOBER 2014 – REVISED DECEMBER 2019
Typical Application (continued)
8.2.1 Design Requirements
• VS range from 9 V to 16 V
• Nominal current of 2 A
• Current sense for fault monitoring
• Expected current limit value of 5 A
• Full diagnostics with 5-V MCU
• Reverse protection with GND network
8.2.2 Detailed Design Procedure
The RCS, VCS linear region is from 0 to 4 V. To keep the 2-A nominal current in the 0- to 3-V range, calculate the
RCS as in Equation 11. To achieve better current sense accuracy, a 1% accuracy or better resistor is preferred.
VCS VCS u K 3 u 500
RCS
750 :
ICS
IOUT
2
(11)
RCL, VCL,th is the current-limit internal threshold, 1.233 V. To set the programmable current limit value at 5 A,
calculate the RCL as in Equation 12.
Vcl,th u K CL 1.233 u 2000
RCL
493.2 :
IOUT
5
(12)
TI recommends RSER = 10 kΩ for 5-V MCU.
TI recommends a 1-kΩ resistor and 200-V, 0.2-A diode for the GND network.
8.2.2.1 Distinguishing of Different Fault Modes
Some applications require that open load, short to battery, and short to GND can be distinguished from each
other. This requires two steps:
1. In the on-state, for the current-sense version device (version B), on-state open load and short to battery are
recognized as an extremely-low voltage level on the current-sense pin, whereas short to GND is reported as
a pulled-up voltage VCS,h. Therefore, the user can find a short to GND (see Figure 46).
2. If reported as an on-state open-load or short-to-battery fault in the first step, turn off the input signal. In the
off-state, with an external pulldown resistor, open load and short to battery can be easily distinguished. When
the output pulls down, the short to battery is still reported as an off-state fault condition, whereas the open
load is ignored.
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Product Folder Links: TPS1H100-Q1
33
TPS1H100-Q1
SLVSCM2D – OCTOBER 2014 – REVISED DECEMBER 2019
www.ti.com
Typical Application (continued)
Current Sense
Voltage
Vcs,H
ADC Full Scale
Range
Max Normal
Operating Current
Operating
Range
Open Load Current
On-state:
Normal
open load/short to battery
Over
current
On-state: Current limit, thermal fault
Off-state: Open load/ short to battery
Figure 46. Step 1: Short-to-GND Detection in the On-State
VBAT
VS
OPEN LOAD
Vol,off
ST/CS
FAULT
OUT
Rpd
Figure 47. Step 2: Short-to-Battery Detection in the Off-State
8.2.2.2 AEC Q100-012 Test Grade A Certification
Short-circuit reliability is critical for smart high-side power switch devices. The AEC-Q100-012 standard is used to
determine the reliability of the devices when operating in a continuous short-circuit condition. Different grade
levels are specified according to the pass cycles. This device is qualified with the highest level, Grade A, 1
million times short-to-GND certification.
Three test modes are defined in the AEC Q100-012 standard. See Table 3 for cold repetitive short-circuit test –
long pulse, cold repetitive short-circuit test – short pulse, and hot repetitive short-circuit test.
34
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Product Folder Links: TPS1H100-Q1
TPS1H100-Q1
www.ti.com
SLVSCM2D – OCTOBER 2014 – REVISED DECEMBER 2019
Typical Application (continued)
Table 3. Tests
Test Items
Test Condition
Test Cycles
Cold repetitive short-circuit test – short pulse
–40°C, 10-ms pulse, cool down
1M
Cold repetitive short-circuit test – long pulse
–40°C, 300-ms pulse, cool down
1M
Hot repetitive short-circuit test
25°C, continuous short
1M
Different grade levels are specified according to the pass cycles. The TPS1H100-Q1 device gets the certification
of Grade A level, 1 million short-to-GND cycles, which is the highest test standard in the market.
Table 4. Grade Levels
Grade
Number of Cycles
Lots,Samples Per Lot
Number of Fails
A
>1000000
3, 10
0
B
>300000 to 1000000
3, 10
0
C
>100000 to 300000
3, 10
0
D
>30000 to 100000
3, 10
0
E
>10000 to 30000
3, 10
0
F
>3000 to 10000
3, 10
0
G
>1000 to 3000
3, 10
0
H
300 to 1000
3, 10
0
O
工商网监
湘ICP备2023018690号
