Sample &
Buy
Product
Folder
Support &
Community
Tools &
Software
Technical
Documents
TPS24740
TPS24741
TPS24742
SLVSCV6A – JANUARY 2015 – REVISED FEBRUARY 2015
TPS2474x 2.5-V to 18-V High Performance Hot Swap and ORing Controller
Check for Samples: TPS24740, TPS24741, TPS24742
1 Features
3 Description
•
•
The TPS2474x is an integrated ORing and Hot Swap
controller for 2.5 V to 18 V systems. It's precise and
programmable protection settings aid in the design of
high power, high availability systems where isolating
faults is critical.
1
•
•
•
•
•
•
•
•
•
•
2.5V to 18V Bus Operation (30V abs max)
Programmable Protection Settings:
– Current Limit: ±5% at 10mV
– Fast Trip: ±10% at 20mV
– Reverse Voltage: ±1mV at –1 mV
Programable Response Time for Fast Trip and
Reverse Voltage
Programmable FET SOA Protection
Dual Timer (Inrush/Fault)
Interchangeable Hot Swap and ORing
Analog Current Monitor (1% at 25mV)
Status Flags for Faults and Power Good
UV and OV Protection
Independent EN for Hot Swap and ORing
4mm × 4mm 24-pin QFN
40 = Latch, 41 = Retry, 42 = Fast Latch Off
Programmable current limit, fast shut down, and fault
timer protect the load and supply during fault
conditions such as a hot - short. The fast shutdown
threshold and response time can be tuned to ensure
a fast response to real faults, while avoiding nuisance
trips. Programmable SOA (Safe Operating Area)
protection and the inrush timer keep the MOSFET
safe under all operating conditions. After asserting a
power good, TPS2474x runs the fault timer during
over-current events, but doesn't current limit. It shuts
down after the fault timer expires. Two independent
timers (inrush/fault) allow the user to customize
protection based on system requirements. The ORing
function of the TPS2474x allows the user to program
the reverse voltage threshold and response time to
aid in the design of redundant power supply systems.
2 Applications
•
•
•
•
Device Information(1)
Enterprise Storage
Power Muxing
Redundant Power Supplies
Battery Back Up
PART NUMBER
PACKAGE
TPS24740
TPS24741
TPS24742
VQFN (24)
BODY SIZE (NOM)
4.00 mm x 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
4 Simplified Schematics
sp
HS FET
BS FET
VOUT
RSENS
VIN
TPS2474x in Priority Muxing
RBG
RFSTP
CRV
RSET
C1
RRV
COUT
CFST
RHG
MAIN
Hotswap
OR
TPS2474x
BGATE
CP
C RVSNM RVSNP VDD SET FSTP
SENM
HGATE
A
OUTH
PGHS
CP
TPS2474x
ENOR
FLTb
IMONBUF
ENHS
AUX
Hotswap
OR
TPS2474x
STAT
OV
PLIM
IMON
RIMON
RPLIM
To Load
OFF if
VMAIN > 11 V
GND
TINR
CINR
TFLT
CFLT
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS24740
TPS24741
TPS24742
SLVSCV6A – JANUARY 2015 – REVISED FEBRUARY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematics...........................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
8.1
8.2
8.3
8.4
8.5
8.6
8.7
9
1
1
1
1
2
3
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings ............................................................ 5
Recommended Operating Conditions....................... 5
Thermal Information ................................................. 5
Electrical Characteristics........................................... 6
Timing Requirements ............................................... 9
Typical Characteristics ............................................ 10
Detailed Description ............................................ 13
9.1 Overview ................................................................. 13
9.2 Functional Block Diagram ....................................... 13
9.3 Feature Description................................................. 14
9.4 Device Functional Modes........................................ 20
10 Application and Implementation........................ 23
10.1 Application Information.......................................... 23
10.2 Typical Application ............................................... 23
10.3 System Examples ................................................ 41
11 Power Supply Recommendations ..................... 51
12 Layout................................................................... 51
12.1 Layout Guidelines ................................................. 51
12.2 Layout Example .................................................... 52
13 Device and Documentation Support ................. 53
13.1
13.2
13.3
13.4
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
53
53
53
53
14 Mechanical, Packaging, and Orderable
Information ........................................................... 53
5 Revision History
Changes from Original (January 2015) to Revision A
•
2
Page
Published full Production Data sheet to include Specification tables, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 4
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: TPS24740 TPS24741 TPS24742
TPS24740
TPS24741
TPS24742
www.ti.com
SLVSCV6A – JANUARY 2015 – REVISED FEBRUARY 2015
6 Device Comparison Table
PART NUMBER (1)
(1)
LATCH / RETRY OPTION
TPS24740
Latch
TPS24741
Auto – Retry
TPS24742
Fast Latch Off
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
7 Pin Configuration and Functions
FSTP
4
SET
5
VDD
ENOR
3
SENM
ENHS
2
18
19
17
20
16
OUTH
21
15
C
22
14
RVSNP
23
HGATE
1
CP
BGATE
24
A
RVSNM
QFN 24-Pin with Thermal Pad
RGE Package
Top View
8
9
10
11
12
PLIM
IMON
TINR
7
GND
6
STAT
OV
PGHS
TFLT
FLTb
13
TPS2474x
IMONBUF
Table 1. Pin Functions
PIN
NAME
NO.
TYPE (1)
DESCRIPTION
A
23
I/P
Voltage sense input that connects to the OR MOSFET's body diode's anode. Connect to the OR
MOSFET source in the typical configuration. A pin is used to supply power to the ORing block of the
TPS2474x under certain biasing conditions.
BGATE
22
O
Connect to the gate of the external OR MOSFET. Controls the OR MOSFET to emulate a low forwardvoltage diode.
C
20
I/P
Voltage sense input that connects to the OR MOSFET's body diode's cathode. Connect to the OR
MOSFET drain in the typical configuration. C pin is used to supply power to the ORing block of the
TPS2474x under certain biasing conditions.
CP
1
I/O
Connect a storage capacitor from CP to A for fast turn-on of blocking Gate.
ENHS
2
I
Active-high enable input of Hot-swap. Logic input. Connects to resistor divider.
ENOR
3
I
Active-high enable input of Oring. Logic input. Connects to resistor divider.
(1)
I = Input; O = Output ; P = Power
Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: TPS24740 TPS24741 TPS24742
Submit Documentation Feedback
3
TPS24740
TPS24741
TPS24742
SLVSCV6A – JANUARY 2015 – REVISED FEBRUARY 2015
www.ti.com
Table 1. Pin Functions (continued)
PIN
NAME
NO.
TYPE (1)
DESCRIPTION
FLTb
4
O
Active-low, open-drain output indicating various faults.
FSTP
16
I
Fast trip programming set pin for hot-swap. Connect RFSTP from the positive terminal of the Hot Swap
sense resistor to the FSTP pin.
GND
10
–
Ground.
HGATE
18
O
Gate driver output for external Hot Swap MOSFET.
IMON
12
I/O
Analog current monitor and load current limit program point. Connect RIMON to ground.
IMONBUF
13
O
Voltage output proportional to the load current (0V–3.0V).
OUTH
19
I
Output voltage sensor for monitoring Hot Swap MOSFET power. Connects to the source terminal of the
hot-swap N channel MOSFET.
OV
9
I
Overvoltage comparator input. Connects to resistor divider. HGATE and BGATE are pulled low when
OV exceeds the threshold. Connect to ground when not used.
PGHS
5
O
Active-high, open-drain power-good indicator.
PLIM
11
I
Power-limiting programming pin. A resistor from this pin to GND sets the maximum power dissipation for
the Hot Swap FET.
RVSNP
21
I
Positive input of the reverse voltage comparator. Connect a resistor from RVSNP to C to set the reverse
voltage trip point of the blocking FET.
RVSNM
24
I
Negative input of the reverse voltage comparator.
SENM
17
I
Current-sensing input for the sensing resistor. Directly connects to the negative terminal of the sensing
resistor.
SET
15
I
Current-limit programming set pin for hot-swap. A resistor is connected from positive terminal of the
sensing resistor.
STAT
6
O
High when BGATE is ON.
TFLT
8
I/O
Fault timer, which runs when the device goes from regular operation to an over-current condition.
TINR
7
I/O
Inrush timer, which runs during the inrush operation (start-up) if the part is in current limit or power limit.
VDD
14
P
Power Supply.
8 Specifications
8.1 Absolute Maximum Ratings
Unless otherwise noted, these apply over recommended operating junction temperature: -40°C ≤ TJ ≤ 125°C.
Input Voltage
Sink Current
MIN
MAX
UNIT
CP, BGATE
–0.3
40
V
VDD,SET, FSTP,SENM, OUTH, C, RVSNP, RVSNM, A, ENHS, ENOR, FLTb, PGHS, OV,
STAT
–0.3
30
V
CP, BGATE to A
–0.3
12
V
HGATE to OUTH
–0.3
15
V
SET to VDD
–0.3
0.3
V
SENM, FSTP to VDD
–0.6
0.3
V
A to C
–30
7
V
RVSNM, to A, C, RVSNP
RVSNP to A, C, RVSNM
–30
30
V
TINR, TFLT, PLIM, IMON,
–0.3
3.6
V
IMONBUF
–0.3
7
V
5
mA
5
mA
150
°C
FLTb, PGHS, STAT
Source Current IMON, IMONBUF
Storage temperature range, Tstg
(1)
4
(1)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: TPS24740 TPS24741 TPS24742
TPS24740
TPS24741
TPS24742
www.ti.com
SLVSCV6A – JANUARY 2015 – REVISED FEBRUARY 2015
8.2 ESD Ratings
VALUE
V(ESD) (1)
(1)
(2)
(3)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (2)
±1500
Charged-device model (CDM), per JEDEC specification JESD22-C101 (3)
±500
UNIT
V
Electrostatic discharge (ESD) measures device sensitivity and immunity to damage caused by assembly line electrostatic discharges
into the device.
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
These apply over recommended operating junction temperature: -40°C ≤ TJ ≤ 125°C.
VDD, SENM, SET (1), FSTP
Input voltage
MIN
MAX
2.5
18
0
18
ENHS, ENOR, FLTb, PGHS, STAT, OUTH
A, C, RVSNM, RVSNP;
(2)
UNIT
V
0.7
18
Sink current
FLTb, PGHS, STAT
0
2
mA
Source current
IMON
0
1
mA
PLIM
4.99
500
kΩ
IMON
1
6
kΩ
RVSNP
10
1000
Ω
FSTP
10
4000
Ω
SET
10
400
Ω
w/o RSTBL (3)
10
70
With appropriate RSTBL
3
10
CP, FSTP, RVSNP
1
1000
nF
(4)
0
1
µF
External resistance
RIMON / RSET
HGATE, BGATE
External capacitor
TINR, TFLT
1
IMON
IMONBUF
Operating junction temperature, TJ
(1)
(2)
(3)
(4)
–40
nF
30
pF
100
pF
125
°C
Do not apply voltage to these pins.
For the HS then ORing application these pins may be below the recommended minimum during start-up. The part is designed to
function properly under these scenarios. However the part should not be used with a bus voltage below the recommended voltage.
Refer to RSTBL Requirement for RIMON / RSET < 10 describe in section Select RSNS and VSNS,CL Setting.
External capacitance tied to HGATE, BGATE should be in series with a resistor no less than 1kΩ.
8.4 Thermal Information
THERMAL METRIC (1)
TPS24740, TPS24741,
TPS24742
UNIT
RGE (24 PINS)
RθJA
Junction-to-ambient thermal resistance
34.6
RθJC(top)
Junction-to-case (top) thermal resistance
38.4
RθJB
Junction-to-board thermal resistance
12.9
ψJT
Junction-to-top characterization parameter
0.5
ψJB
Junction-to-board characterization parameter
12.9
RθJC(bot)
Junction-to-case (bottom) thermal resistance
3.2
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: TPS24740 TPS24741 TPS24742
Submit Documentation Feedback
5
TPS24740
TPS24741
TPS24742
SLVSCV6A – JANUARY 2015 – REVISED FEBRUARY 2015
www.ti.com
8.5 Electrical Characteristics
Unless otherwise noted these limits apply to the following: -40°C ≤ TJ ≤ 125°C; 2.5V < VVDD , VOUTH < 18V; 0.7 V < VA , VC ,
VRVSNM < 18 V; VENHS = VENOR = 2 V, VOV = 0 V; VBGATE, VHGATE, VPGHS, VSTAT, VFLTb, and VIMONBUF are floating; CCP = 100 nF,
CINR = 1 nF, CFLT = 1 nF, RSET = 44.2 Ω, RIMON = 2.98 kΩ, RFSTP = 200 Ω, RRV = 200 Ω, and RPLIM = 52 kΩ.
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
2.2
2.32
2.45
V
INPUT SUPPLY (VDD)
VUVR
UVLO threshold, rising
VUVhyst
UVLO hysteresis
IQON
Supply current: IVDD+IA+IC+ IOUTH
0.1
Device on, VENHS = VENOR = 2V
V
4.2
6
1.35
1.4
mA
HOT SWAP FET ENABLE (ENHS)
VENHS
Threshold voltage, rising
VENHShyst
Hysteresis
IENHS
Input Leakage Current
1.3
50
0 ≤ VENHS ≤ 30V
–1
V
mV
1
µA
BLOCKING (ORING) FET ENABLE (ENOR)
VENOR
Threshold voltage, rising
VENORhyst
Hysteresis
IENOR
Input leakage current
1.3
1.35
1.4
50
0 V ≤ VENOR ≤ 30V
V
mV
–1
0
1
µA
1.3
1.35
1.4
mV
OVER VOLTAGE (OV)
VOVR
Threshold voltage, rising
VOVhyst
Hysteresis
IOV
Input leakage current
50
0 ≤ VOV ≤ 30V
–1
mV
1
µA
V
POWER LIMIT PROGRAMING (PLIM)
VPLIM,BIAS
VIMON,PL
Bias voltage
Sourcing 10μA
Regulated IMON voltage during power limit
0.66
0.675
0.69
RPLIM = 52 kΩ; VSENM-OUTH=12V;
114.75
135
155.25
RPLIM = 105 kΩ; VSENM-OUTH=12V;
56.95
67
77.05
RPLIM = 261 kΩ; VSENM-OUTH=12V;
18.9
27
35.1
RPLIM = 105 kΩ; VSENM-OUTH=2V;
341.7
402
462.3
RPLIM = 105 kΩ; VSENM-OUTH=18V;
38.25
45
51.75
mV
SLOW TRIP THRESHOLD (SET)
VOS_SET
Input referred offset (VSNS to VIMON scaling)
VGE_SET
Gain error (VSNS to VIMON scaling) (1)
RSET = 44.2Ω; RIMON=3kΩ to 1.2kΩ (corresponds to
VSNS,CL=10mV to 25mV)
–150
150
–0.4%
0.4%
µV
FAST TRIP THRESHOLD PROGRAMMING (FSTP)
IFSTP
FSTP input bias current
VFASTRIP
Fast trip threshold
VFSTP=12V
95
100
105
RFSTP = 200 Ω, VSNS when VHGATE ↓
18
20
22
µA
RFSTP = 1 kΩ, VSNS when VHGATE ↓
95
100
105
RFSTP = 4 kΩ, VSNS when VHGATE ↓
380
400
420
660
675
690
mV
mV
mV
CURRENT MONITOR and CURRENT LIMIT PROGRAMING (IMON)
VIMON,CL
Slow trip threshold at summing node
VIMON↑, when ITFLT starts sourcing
CURRENT MONITOR (IMONBUF)
VOS_IMONBUF
Buffer offset
VIMON = 50mV to 675mV, Input referred
GAINIMONBUF
Buffer voltage gain
ΔVIMONBUFF / ΔVIMON
BWIMONBUF
Buffer closed loop bandwidth
CIMONBUF = 75pF
(1)
6
–3
0
3
2.97
2.99
3.01
1
V
MHz
Specified by characterization, not production tested.
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: TPS24740 TPS24741 TPS24742
TPS24740
TPS24741
TPS24742
www.ti.com
SLVSCV6A – JANUARY 2015 – REVISED FEBRUARY 2015
Electrical Characteristics (continued)
Unless otherwise noted these limits apply to the following: -40°C ≤ TJ ≤ 125°C; 2.5V < VVDD , VOUTH < 18V; 0.7 V < VA , VC ,
VRVSNM < 18 V; VENHS = VENOR = 2 V, VOV = 0 V; VBGATE, VHGATE, VPGHS, VSTAT, VFLTb, and VIMONBUF are floating; CCP = 100 nF,
CINR = 1 nF, CFLT = 1 nF, RSET = 44.2 Ω, RIMON = 2.98 kΩ, RFSTP = 200 Ω, RRV = 200 Ω, and RPLIM = 52 kΩ.
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
12
13.6
15.5
V
7
7.95
15
V
HOT SWAP GATE DRIVER (HGATE)
5 ≤ VVDD ≤ 16V; measure VHGATE-OUTH
VHGATE
HGATE output voltage
2.5V Max(VA, VC, VVDD) > 4V, Measure VCP-A
5
5.9
11
Max(VA, VC, VVDD) = 2.5 V, Measure VCP-A
8
9.8
11
VAC = 20mV, sustained
0.2
0.3
0.4
Fast turnoff, VBGATE-A = 7V
0.4
0.9
1.4
A
Sustained, VBGATE-A = 2V to 11V
19
35
65
mA
V
BLOCKING/ORING GATE DRIVER (BGATE)
IBGATE_CHRG
IBGATEsustSink
(2)
VAC = 20mV, pulse
BGATE Pull up current
BGATE Sinking current
30
mA
mA
For more detail on the definition and usage of these parameters refer to section Using SoftStart – IHGATE and TINR Considerations.
Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: TPS24740 TPS24741 TPS24742
Submit Documentation Feedback
7
TPS24740
TPS24741
TPS24742
SLVSCV6A – JANUARY 2015 – REVISED FEBRUARY 2015
www.ti.com
Electrical Characteristics (continued)
Unless otherwise noted these limits apply to the following: -40°C ≤ TJ ≤ 125°C; 2.5V < VVDD , VOUTH < 18V; 0.7 V < VA , VC ,
VRVSNM < 18 V; VENHS = VENOR = 2 V, VOV = 0 V; VBGATE, VHGATE, VPGHS, VSTAT, VFLTb, and VIMONBUF are floating; CCP = 100 nF,
CINR = 1 nF, CFLT = 1 nF, RSET = 44.2 Ω, RIMON = 2.98 kΩ, RFSTP = 200 Ω, RRV = 200 Ω, and RPLIM = 52 kΩ.
PARAMETER
TEST CONDITION
MIN
TYP
MAX
1.85
1.93
2.05
UNIT
BLOCKING/ORing ANODE (A)
IA
Input current (3)
2.5 V ≤ VA ≤ 18V
VA_UVLO
Undervoltage lockout
VA increasing and VVDD=VC=0.7V
VA_UVLO_hyst
Undervoltage lockout hysteresis
3
0.1
mA
V
V
BLOCKING/ORing CATHODE (C)
IC
Input current (3)
2.5 V ≤ VC ≤ 18V
VC_UVLO
Undervoltage lockout
VC increasing and VDD=VA=0.7V
VC_UVHyst
Hysteresis
VFWDTH
Forward turn-on voltage
3
1.85
1.93
2.05
100
Measure VAC when VBGATE ↑
mA
V
mV
7.5
10
12.5
mV
POSITIVE INPUT OF REVERSE VOLTAGE COMPARATOR (RVSNP)
IRVSNP
RVSNP Input bias current
VRVSNP = 12V, sinking current; 0.7V < VA,
VRVSNM < 20V
93
99
105
µA
VRVTRIP1
Reverse Comparator Offset
RRV=10Ω, Measure VRVSNP-RVSNM, when BGATE↓
-1
0
1
mV
2
µA
NEGATIVE INPUT OF REVERSE VOLTAGE COMPARATOR (RVSNM)
IRVSNM
Leakage current
–2
FAULT INDICATOR (FLTb)
VOL_FLTb
Output low voltage
Sinking 2 mA
0.11
0.25
V
IFLTb
Input Leakage Current
VFLTb = 0V, 30V
–1
0
1
µA
VHSFLT_IMON
VIMON threshold to detect Hot Swap FET short
VENHS = 0V, Measured VIMON ↑ to GND when FLTb ↓
88
101
115
mV
VHSFL_hyst
Hysteresis
VBFET, OPEN, FLT
A-C threshold to detect OPEN Blocking/ORing
VENOR=3V, Measure VA-C to FLTb↓, VCP-A > 7V
FET fault
VCP_FLT
CP fault threshold
VCP, FLT, hyst
Hysteresis
25
Measure VCP-A ↓ when FLTb↓, 4V ≤ VVDD < 18V
Measure VCP-A ↓ when FLTb↓, 2.5V < VVDD < 4V
350
410
mV
490
mV
5
5.5
6
V
3.3
3.75
4.2
V
4V ≤ VVDD < 18V
1.5
V
2.5V < VVDD < 4V
1.1
V
HOT SWAP POWER GOOD OUTPUT (PGHS)
VPGHSth
PGHS Threshold
Measure VSENM-OUTH ↓ when PGHS↑
VPGHShyst
PGHS hysteresis
VSENM-OUTH ↑
80
VOL_PGHS
PGHS Output low voltage
Sinking 2mA
0.11
0.25
V
IPGHS
PHGS Input leakage current
VPGHS=0V to 30V
–1
0
1
µA
5
6
7
V
2.5V < VVDD < 4V , Measure VBGATE – A ↑, when
STAT↑
3.6
4
4.4
V
4V < VVDD < 20V , Measure VBGATE – A ↓, when
STAT↓
4
5
6
V
2.5V PLIM so the Hot Swap will start in power limit and transition
into current limit. In that case the maximum start time can be computed as seen in Equation 63:
t start,max =
2
COUT é VIN,MAX PLIM ù 10000 mF é (13 V)2
39 W ù
´ê
+ 2 ú=
´ê
+
ú = 21.76 ms
2
2
êë PLIM
ILIM úû
(45 A)2 ûú
êë 39 W
(63)
Note that the above start time is based on typical current limit and power limit values. To ensure that the timer
never times out during start-up it is recommended to set the fault time (TINR) to be 1.5x tstart,max or 32.6 ms. This
will account for the variation in power limit, timer current, and timer capacitance.
Next the designer should decide if having equal TINR and TFLT is acceptable. Note that to pass the load
transient the fault timer needs to be longer than 200 ms. If the inrush time is this long, it will place too much
stress on the MOSFET during a start into short. For this reason, it’s ideal to have two separate timers. To ensure
proper start up and to pass the load transient a target inrush time (TINR,TGT) of 32.6 ms and a target fault time
(TFLT,TGT) of 250ms is used. CINR,CLC and CFLT,CLC is computed as seen in Equation 64 and Equation 65 :
CINR,CLC = 7.59 mF ´ TINR,TGT = 7.59 mF ´ 32.6 ms = 247 nF
(64)
Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: TPS24740 TPS24741 TPS24742
Submit Documentation Feedback
37
TPS24740
TPS24741
TPS24742
SLVSCV6A – JANUARY 2015 – REVISED FEBRUARY 2015
www.ti.com
sp
CFLT,CLC = 7.59 mF ´ TFLT,TGT = 7.59 mF ´ 250 ms = 1898 nF
(65)
The next largest available CINR is chosen as 330nF and the next largest available CFLT is chosen as 2.2µF
Next, the actual TINR and TFLT can be computed as shown below: Once CTMR and CFLT is chosen the actual
programmed time out can be computed as shown in Equation 66 and Equation 67.
CINR
330 nF
TINR =
=
= 43.5 ms
7.407 mF 7.59 mF
(66)
sp
TFLT =
CFLT
2.2 mF
=
= 290 ms
7.407 mF 7.59 mF
(67)
10.2.5.2.6 Check MOSFET SOA
Once the power limit and fault timer are chosen, it’s critical to check that the FET will stay within its SOA during
all test conditions. For this design example the TPS24742 is used, which does not retry during a hot-short. Thus
the worst condition is a start-up with output shorted to GND. In this case the TPS24742 will start into a power
limit and regulate at that point for 43.5 ms (TINR). Based on the SOA of the CSD16415Q, it can handle 13 V, 15
A for 10 ms and it can handle 13 V, 4 A for 100 ms. The SOA for 43.5 ms can be extrapolated by approximating
SOA vs time as a power function as shown in Equation 68:
ISOA (t ) = a ´ tm
m=
a=
(
æ 15 A ö
ln ç
÷
è 4 A ø = -0.57
æ 10 ms ö
ln ç
÷
è 100 ms ø
)=
ln ISOA (t1 ) / ISOA (t 2 )
ln (t1 / t 2 )
ISOA (t1 )
=
15 A
-0.57
= 56.25 A ´ (ms )
0.57
(10 ms )
ISOA (43.5 ms ) = 56.25 A ´ (ms)0.57 ´ (43.5 ms)-0.57 = 6.55 A
t1m
(68)
Note that the SOA of a MOSFET is specified at a case temperature of 25°C, while the case temperature can be
hotter during a start into a short. It is important to understand the hottest temperature that a MOSFET can be
during a start-up (TC, MAX, START). If a board has been off for a while and then it’s turned on TA, MAX is a good
estimate for TC,MAX, START. However, if a board is on and then gets power cycled TC,MAX should be used for
TC,MAX,START. This will depend on system requirements. For this design example it is assumed that the board can
only be plugged in cold and TA,MAX is used to estimate TC,MAX,START.
TJ,ABSMAX - TA,MAX
ISOA (43.5 ms, TC,MAX,START ) = ISOA (43.5 ms, 25°C )´
TJ,ABSMAX - 25°C
= 6.55 A ´
150°C - 55°C
= 4.98 A
150°C - 25°C
(69)
Based on this calculation the MOSFET can handle 4.98 A, 13 V for 43.5 ms at 55°C elevated case temperature,
but is only required to handle 3A during a hot-short. Thus there is good margin and this will be a robust design.
In general, it is recommended that the MOSFET can handle 1.3x more than what is required during a worst case
operating condition. This provides margin to cover the variance of the power limit and fault time.
10.2.5.2.7 Checking Stability of Hot Swap Loop
Using the same method as shown for the OR then Hot Swap example, Ensuring Stability, the minimum required
CGS is computed to be 0.6 nF. Again the CISS is 3.1nF and there is plenty of margin to ensure stability.
38
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: TPS24740 TPS24741 TPS24742
TPS24740
TPS24741
TPS24742
www.ti.com
SLVSCV6A – JANUARY 2015 – REVISED FEBRUARY 2015
10.2.5.2.8 Choose ORing MOSFET
When selecting the ORing MOSFET, the considerations are similar to the Hot Swap MOSFET, but the SOA is no
longer critical. In addition the lower RDSON is not always ideal, because that would result in a larger reverse
current for the same reverse voltage threshold. Of course a lower RDSON would provide better efficiency. For
consistency sake a single CSD16415Q FET was used for the ORing section as well. It’s important to check its
steady state temperature at max load using the same equation that was used for the Hot Swap.
C
2
TC,MAX = 55°C + 30°
´ (40 A ) ´ (1.4 ´ 1 mW ) = 122.2°C
(70)
W
10.2.5.2.9 Choose Reverse Current Threshold and Filtering
Same settings were used as the previous design example.
10.2.5.2.10 Choose Under Voltage and Over Voltage Settings
Same settings were used as the previous design example.
10.2.5.2.11 Selecting CIN, COUT, CMIDDLE, and Transient Protection
Same settings were used as the previous design example
10.2.5.2.12 Adding CENHS
When the ENHS pulled below its threshold and raised back up the IC will reset. Note that during a hot short the
input voltage can easily droop below the UV threshold and cycle the ENHS pin. For the TPS24740 and
TPS24741 IC’s this will not cause any issues. However, when using the TPS24742 the cycling of the ENHS will
result in the IC attempting to restart, which is undesired (this is the main reason why someone would use the
TPS24742). To avoid this behavior a capacitor should be added to the ENHS to provide filtering. For this
example 33 nF was chosen.
10.2.5.3 Application Curves
Figure 46. Start up (COUT=440µF)
Figure 47. Start up (COUT=10,000µF, VIN = 13V)
Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: TPS24740 TPS24741 TPS24742
Submit Documentation Feedback
39
TPS24740
TPS24741
TPS24742
SLVSCV6A – JANUARY 2015 – REVISED FEBRUARY 2015
40
www.ti.com
Figure 48. Start up Into Short on VOUT
Figure 49. Hot Short on VOUT
Figure 50. Hot – Short on VOUT(zoomed in)
Figure 51. Under/Over Voltage with VIN Rising
Figure 52. Short Vin (ILOAD = 10A)
Figure 53. Gradual Reverse Current
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: TPS24740 TPS24741 TPS24742
TPS24740
TPS24741
TPS24742
www.ti.com
SLVSCV6A – JANUARY 2015 – REVISED FEBRUARY 2015
Figure 54. 60A Load Step for 200 ms
Figure 55. Load Step 40A to 60A
Figure 56. Gradual Overcurrent
10.3 System Examples
The TPS2474x is a flexible Hot Swap and ORing controller that can supports many redundant configurations.
The following section goes through the various system level configurations and the advantages of each one. It
also shows how the TPS2474x will behave under system level tests.
10.3.1 TPS2474x in Battery Back Up
Some battery back-up units are set up to support both charging and discharging from the same terminal. In this
case a configuration shown in Figure 57 can be used. In normal operation the load is power from the AC/DC,
while the BBU is charged from the mid-point. The Hot Swap will provide inrush and fault protection to the load. If
the AC/DC fails the ORing will prevent the reverse current to the AC/DC and the load will get powered from the
BBU.
Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: TPS24740 TPS24741 TPS24742
Submit Documentation Feedback
41
TPS24740
TPS24741
TPS24742
SLVSCV6A – JANUARY 2015 – REVISED FEBRUARY 2015
www.ti.com
System Examples (continued)
AC/DC
Hotswap
OR
To Load
TPS2474x
BBU
Figure 57. Block Diagram for Hot Swap and ORing in BBU Applications
Figure 58 shows the schematic for this implementation. It is important to connect VDD to the mid-point to ensure
that the IC has power even if VIN goes away. In addition the ENHS pin should be based on the mid-point voltage
to ensure that the Hot Swap stays ON even if the VIN power goes away.
VBBU
BS FET
HS FET
RSENS
CRV
RBG
CP
CP
A BGATE
C
RVSNP
RRV
RFSTP
C1
0.1 μF
RSET
VIN
RVSNM VDD SET FSTP
VOUT
COUT
CFST
RHG
SENM
470 μF
HGATE
OUTH
PGHS
ENOR
TPS2474x
FLTb
ENHS
IMONBUF
OV
IMON
RIMON
RPLIM
PLIM
GND
STAT
TINR
CINR
TFLT
CFLT
Figure 58. Application Schematic for TPS2474x in BBU Applications
Figure 59 shows a switch over from the AC/DC power (VIN) to BBU power with a 12A load. The BBU is modeled
as drawing 4A when VMIDDLE > 12V and supplying up to 20A when VMIDDLE < 12V. Note that when VIN collapses
the BBU current goes from negative to positive and the BGATE goes down to prevent the AC/DC from draining
power from the BBU.
42
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: TPS24740 TPS24741 TPS24742
TPS24740
TPS24741
TPS24742
www.ti.com
SLVSCV6A – JANUARY 2015 – REVISED FEBRUARY 2015
System Examples (continued)
Figure 59. Switch Over to Battery Power
10.3.2 TPS2474x in Priority Muxing
Priority muxing is used in the following scenario:
1. The system should be powered from Main when it’s present
2. The system should be powered from Auxiliary when Main goes away.
3. Auxiliary voltage may be above the Main voltage.
4. The system should support a short to ground on both Main and Aux.
Due to condition 3, the 2 supplies can’t be simply ORed together because the load could start drawing power
from AUX. That’s why an additional Hot Swap is required on the AUX rail to prevent the forward current flow. The
OV pin of the TPS2474x can be used to keep the Auxiliary Hot Swap OFF unless the voltage on MAIN falls
below a certain threshold.
MAIN
Hotswap
OR
TPS2474x
OFF if
VMAIN > 11 V
AUX
Hotswap
To Load
OR
TPS2474x
Figure 60. Block Diagram for Priority Muxing
Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: TPS24740 TPS24741 TPS24742
Submit Documentation Feedback
43
TPS24740
TPS24741
TPS24742
SLVSCV6A – JANUARY 2015 – REVISED FEBRUARY 2015
www.ti.com
System Examples (continued)
HS FET
BS FET
RSNS
0.1 µF
RDIV1
VDD
SET
VOUT
CFST
FSTP
SENM
HGATE
OUTH
CP
A
C RV
RBG
BGATE
RVSNM
COUT
RVSNP
C
ENOR
PGHS
ENHS
TPS24742
FLTb
OV
IMONBUF
RPLIM
RDIV4
PLIM
GND
IMON
RIMON
VMAIN
RDIV3
RDIV2
CCP
RHG
RRV
RSET
CIN
RFSTP
VAUX
CENHS
CMIDDLE
TINR
CINR
TFLT
STAT
CFLT
Figure 61. OV Pin Hook Up on the AUX Channel
The following waveforms show the performance of the priority mux using the settings from the Hot Swap then
ORing design example. The OV pin on the AUX side was set to make it turn on once Main was below 11V. Note
that for a 10A load the switch over occurs without any issues, but the system cannot handle it at 30A. This
occurs due to VAUX being higher than VMAIN and VOUT drooping after the main channel shuts down and the
AUX channel coming back up. As a result there is a voltage drop across the Hot Swap MOSFET (VAUX – VOUT)
and the TPS24742 limits the input current to PLIM/VDS. If the supplied current is lower than the load current the
output capacitor continues to discharge and the system shuts down. When the power limit was increased to
160W the switch over occurred without any issues, because sufficient current was supplied to power the load
and charge the output capacitor.
Figure 62. Switch from Main to Aux (VMAIN = 12V, VAUX = 14V, ILOAD = 10A)
44
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: TPS24740 TPS24741 TPS24742
TPS24740
TPS24741
TPS24742
www.ti.com
SLVSCV6A – JANUARY 2015 – REVISED FEBRUARY 2015
System Examples (continued)
PLIM = 160W
PLIM = 39W
Figure 63. Switch from Main to Aux with VMAIN = 12V, VAUX = 14V, ILOAD = 30A
(left: PLIM = 39W, right; PLIM = 160W)
10.3.3 TPS2474x with Multiple Loads and Multiple Supplies
Figure 64 applies to systems that have multiple supplies and multiple loads. The ORing after each supply
ensures that the loads won’t lose power if any of the supplies fail and the Hot Swap in front of each load ensures
that a failure on one load doesn’t affect the operation of the other loads. The node on the output of ORing and
input of the Hot Swaps is referred to as VMIDDLE.
AC/DC1
OR
Hotswap
To Load1
TPS2474x
AC/DC2
OR
Hotswap
To Load2
TPS2474x
Figure 64. Block Diagram for Systems with Multiple Supplies and Loads
Figure 65 shows a hot-short on load 1, which results in a shutdown of the first Hot Swap gate. Note that the
second load continues to be powered as both HGATE2 and VMIDDLE stay high.
Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: TPS24740 TPS24741 TPS24742
Submit Documentation Feedback
45
TPS24740
TPS24741
TPS24742
SLVSCV6A – JANUARY 2015 – REVISED FEBRUARY 2015
www.ti.com
System Examples (continued)
Figure 65. Hot Short on Load 1, Load 2 Not Interrupted
The main purpose of the ORing controller is to protect the loads when one of the input supplies has a failure. The
two waveforms below show this scenario. The left waveform shows a condition where both of the power supplies
are at the same voltage and both of the BGATEs are ON. When VIN1 goes to ground BGATE1 quickly turns
OFF, while BGATE2 remains ON. In the waveform on the right VIN1 is above VIN2 so the system starts by with
only BGATE1 being ON. When VIN1 goes to ground, BGATE1 quickly turns off and BGATE2 turns ON. There is
a short delay between BGATE1 turning off and BGATE2 turning ON. This pause is due to VMIDDLE discharging
from 12.5V to 12V (BGATE2 will only turn on when VIN2 > VMIDDLE)
VIN1 = VIN2 = 12V
VIN1 =12.5V, VIN2 = 12V
Figure 66. Hot Short on VIN1
(left: VIN1 = VIN2 = 12V; right VIN1 =12.5V, VIN2 = 12V, ILOAD1 = ILOAD2 = 12A )
46
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: TPS24740 TPS24741 TPS24742
TPS24740
TPS24741
TPS24742
www.ti.com
SLVSCV6A – JANUARY 2015 – REVISED FEBRUARY 2015
System Examples (continued)
Figure 67 shows a system configuration where VIN1 equals VIN2 and VIN2 is hot plugged. Note that when BGATE2
comes up almost immediately and VIN1 raises as well. This is due to the fact that VIN1 had some voltage droop
due to the IR drop of the input impedance. When a second supply was placed in parallel the load was shared
reducing the droop. The quick input spike on VIN2 is due input inductance.
Figure 67. Hot Plug VIN2 (VIN1 = 12V; VIN2 = 12V; ILOAD1 = ILOAD2 = 12A)
10.3.4 Two Supplies Powering a Load
Figure 68 can be used when ORing two power supplies together to drive a single load. The ORing provide
protection in case one of the AC/DC’s fail and the Hot Swap provides protection if there is a failure at the load
and if one of the AC/DC output voltages has an overvoltage condition.
Hotswap
AC/DC1
OR
TPS2474x
To Load
AC/DC2
Hotswap
OR
TPS2474x
Figure 68. Block Diagram for ORing Two Power Supplies
Figure 69 and Figure 70 shows a hot plug event on power supply A, when power supply B is already up. If VINA
is above VINB, the blocking gate of channel B turns off and the load is powered from channel A. If VINA is below
VINB, BGATEA doesn’t enhance and the power continues to be supplied from channel B.
Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: TPS24740 TPS24741 TPS24742
Submit Documentation Feedback
47
TPS24740
TPS24741
TPS24742
SLVSCV6A – JANUARY 2015 – REVISED FEBRUARY 2015
www.ti.com
System Examples (continued)
Figure 69. Hot Plug VINA (VINA =12.5, VINB = 12V,
RLOAD = 10Ω)
Figure 70. Hot Plug VINA (VINA =11.5V, VIN2 = 12V,
RLOAD = 10Ω)
Figure 71 shows power switching from VINA to VINB after VINA shorts to ground. Note that VOUT droops until it is at
the same level as VINB when BGATEB turns on.
Figure 71. Short on VINA Zoomed In and Zoomed Out View (ILOAD=10A, VINA = 12V, VINB = 11.5V)
Figure 72 shows the same event when VINA and VINB are equal and both channels are on before VINA shorts to
ground. Note channel B stays on and channel A shuts down.
48
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: TPS24740 TPS24741 TPS24742
TPS24740
TPS24741
TPS24742
www.ti.com
SLVSCV6A – JANUARY 2015 – REVISED FEBRUARY 2015
System Examples (continued)
Figure 72. Short on VINA (ILOAD=10A, VINA = 12V, VINB = 12V)
10.3.5 TPS2474x in Redundant DC/DC Applications
In systems that require zero down time, redundant DC/DCs may be used. The goal is to maintain the output
voltage bus even if one of the DC/DCs fail. Consider a case when there is a short on the high-side MOSFET.
This would effectively short the input bus to the output bus through an inductor resulting in a system failure.
Adding Hot Swap before the DC/DC will protect both the input bus and the output bus by disconnecting power to
the faulty DC/DC module. Next consider a case when the low side MOSFET is shorted. This would pull down the
output bus causing system failure as well. To prevent this and ORing controller should be added on the output of
the DC/DC controller.
TPS2474x is ideal for this application because it can provide both the hot swap and ORing functionality. Note
that the combination of the DC/DC and TPS2474x can be made into hot-swappable modules. That way these
can be replaced without turning OFF the system.
12 V_IN
Hotswap
DC/DC
OR
TPS2474x
Hotswap
DC/DC
OR
To Loads
TPS2474x
Figure 73. Block Diagram for Systems With Redundant DC/DC
Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: TPS24740 TPS24741 TPS24742
Submit Documentation Feedback
49
TPS24740
TPS24741
TPS24742
SLVSCV6A – JANUARY 2015 – REVISED FEBRUARY 2015
www.ti.com
System Examples (continued)
12 V
DC/DC
CONVERTER
0.9 V – 5 V
C RV
HS FET
BS FET
R SNS
R SET
R FSTP
V IN
C1
0.1 μF
VDD
SET FSTP
V OUT
C FST
CP
R HG
SENM
HGATE OUTH
R RV
R BG
CP RVSNM
A BGATE
C
ENOR
C OUT
RVSNP
PGHS
TPS2474x
ENHS
FLTb
IMONBUF
OV
STAT
IMON
R IMON
R PLIM
PLIM
GND
TINR
C INR
TFLT
C FLT
Figure 74. Application Schematic for Hot Swap, DC/DC, ORing Configuration
50
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: TPS24740 TPS24741 TPS24742
TPS24740
TPS24741
TPS24742
www.ti.com
SLVSCV6A – JANUARY 2015 – REVISED FEBRUARY 2015
11 Power Supply Recommendations
In general, operation is best when the input supply isn’t noisy and doesn’t have significant transients. For noisier
environments filtering on input, output, fast trip, and reverse trip should be adjusted to avoid nuisance trips.
12 Layout
12.1 Layout Guidelines
When doing the layout of the TPS2474x in the ORing then hot swap configuration the following are considered
best practice.
• Ensure proper Kelvin Sense of RSNS
• Keep the filtering capacitors CFSTP and CRV as close to the IC as possible.
• Keep the traces from CCP to CP and A as short as possible.
• Run a separate trace from A and RVSNM to ORing FET source. This will prevent the charge pump noise
along with a DC bias (due to supply current draw) from interfering with the reverse current threshold.
• Run a separate trace from C and from RRV to ORing FET drain.
• Place a Schottky diode and a ceramic bypass capacitor close to the source of the Hot Swap MOSFET.
• Place a TVS and a ceramic bypass capacitor between VIN and ground close to the source of the ORing
MOSFET.
• Use a separate trace to connect to VDD and SENM.
• Note that special care must be taken when placing the bypass capacitor for the VDD pin. During Hot Shorts,
there is a very large dv/dt on input voltage during the MOSFET turn off. If the bypass capacitor is placed right
next to the pin and the trace from RSNS to the pin is long, an LC filter is formed. As a result a large differential
voltage can develop between VDD and SENM if there is a large transient on Vin. This could result in a
violation of the abs max rating from VDD to SENM. To avoid this, place the bypass capacitor close to RSNS
instead of the VDD pin.
SENM
Vdd
Trace
inductance
Figure 75. Layout Don'ts
Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: TPS24740 TPS24741 TPS24742
Submit Documentation Feedback
51
TPS24740
TPS24741
TPS24742
SLVSCV6A – JANUARY 2015 – REVISED FEBRUARY 2015
www.ti.com
12.2 Layout Example
Power Flow
G
ORING FET
HS FET
R SNS
S
D
V IN
D
S
G
V OUT
RSET
RFSTP
RRV
C RV
15
14
IMONBUF
HGATE
13
12
RIMON
IMON
11
RPLIM
10
GND
OV
TFLT
TINR
9
CFLT
CINR
8
PLIM
6
7
RDIV3
SET
VDD
5
R DIV2
4
STAT
18
C
3
FSTP
17
RVSNP
SENM
TPS2474X
FLTb
PGHS
19
16
A
BGATE
RVSNM
C CP
20
Shottkey
21
C MIDDLE
22
C FSTP
2
ENHS
ENOR
23
C OUT
24
CP
1
C IN
TVS
R DIV1
OUTH
layer1
layer2
via
Power_GND
Figure 76. Layout Example for ORing then Hot Swap Configuration
52
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: TPS24740 TPS24741 TPS24742
TPS24740
TPS24741
TPS24742
www.ti.com
SLVSCV6A – JANUARY 2015 – REVISED FEBRUARY 2015
13 Device and Documentation Support
13.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 6. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS24740
Click here
Click here
Click here
Click here
Click here
TPS24741
Click here
Click here
Click here
Click here
Click here
TPS24742
Click here
Click here
Click here
Click here
Click here
13.2 Trademarks
All trademarks are the property of their respective owners.
13.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: TPS24740 TPS24741 TPS24742
Submit Documentation Feedback
53
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS24740RGER
ACTIVE
VQFN
RGE
24
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS
24740
TPS24740RGET
ACTIVE
VQFN
RGE
24
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS
24740
TPS24741RGER
ACTIVE
VQFN
RGE
24
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS
24741
TPS24741RGET
ACTIVE
VQFN
RGE
24
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS
24741
TPS24742RGER
ACTIVE
VQFN
RGE
24
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS
24742
TPS24742RGET
ACTIVE
VQFN
RGE
24
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS
24742
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
