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TPS3103, TPS3106, TPS3110
SLVS363G – AUGUST 2001 – REVISED SEPTEMBER 2016
TPS31xx
Ultralow Supply-Current Voltage Monitor With Optional Watchdog
1 Features
3 Description
•
The TPS310x and TPS311x families of supervisory
circuits provide circuit initialization and timing
supervision, primarily for DSP and processor-based
systems.
1
•
•
•
•
•
•
Precision Supply Voltage Supervision Range:
0.9 V, 1.2 V, 1.5 V, 1.6 V, 2 V, and 3.3 V
High Trip-Point Accuracy: 0.75%
Supply Current of 1.2 μA (Typical)
RESET Defined With Input Voltages as Low as
0.4 V
Power-On Reset Generator With a Delay Time of
130 ms
Push/Pull or Open-Drain RESET Outputs
Package Temperature Range: –40°C to 125°C
2 Applications
•
•
•
•
•
•
Applications Using Low-Power DSPs,
Microcontrollers, or Microprocessors
Portable and Battery-Powered Equipment
Intelligent Instruments
Wireless Communication Systems
Industrial Equipment
Notebook and Desktop Computers
All the devices of this family have a fixed-sense
threshold voltage (VIT–) set by an internal voltage
divider.
The TPS3103 and TPS3106 devices have an activelow, open-drain RESET output and either an
integrated power-fail input (PFI) or SENSE input with
corresponding outputs for monitoring other voltages.
The TPS3110 has an active-low push/pull RESET
and a watchdog timer to monitor the operation of
microprocessors. All three devices have a manual
reset pin that can be used to force the outputs low
regardless of the sensed voltages.
Typical Application Schematic
3.3 V
1.6 V
VDD
VCORE
During power-on, RESET is asserted low when the
supply voltage (VDD) becomes higher than 0.4 V.
Thereafter, the supervisory circuit monitors VDD and
keeps the RESET output low as long as VDD remains
below the threshold voltage (VIT–). To ensure proper
system reset, after VDD surpasses the threshold
voltage, an internal timer delays the transition of the
RESET signal from low to high for the specified time.
When VDD drops below VIT–, the output transitions low
again.
VIO
The product spectrum is designed for supply voltages
of 0.9 V up to 3.6 V. The circuits are available in 6-pin
SOT-23 packages. The TPS31xx family is
characterized for operation over a temperature range
of –40°C to 125°C.
R3
TPS3106K33DBV
Device Information(1)
DSP
R1
MR
RSTVDD
RESET
TPS3106xxx
RSTSENSE
R2
GND
GND
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TPS3103xxx
SENSE
GND
SOT-23 (6)
2.90 mm × 1.60 mm
TPS3110xxx
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS3103, TPS3106, TPS3110
SLVS363G – AUGUST 2001 – REVISED SEPTEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Available Options...................................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
8
1
1
1
2
4
4
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings ............................................................ 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 6
Electrical Characteristics........................................... 6
Timing Requirements ................................................ 8
Switching Characteristics .......................................... 8
Typical Characteristics ............................................ 11
Detailed Description ............................................ 13
8.1 Overview ................................................................. 13
8.2 Functional Block Diagrams ..................................... 13
8.3 Feature Description................................................. 15
8.4 Device Functional Modes........................................ 17
9
Application and Implementation ........................ 18
9.1 Application Information............................................ 18
9.2 Typical Application .................................................. 18
10 Power Supply Recommendations ..................... 20
11 Layout................................................................... 20
11.1 Layout Guidelines ................................................. 20
11.2 Layout Example .................................................... 20
12 Device and Documentation Support ................. 21
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Device Support ....................................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
21
21
21
22
22
22
22
13 Mechanical, Packaging, and Orderable
Information ........................................................... 22
4 Revision History
Changes from Revision F (November 2015) to Revision G
Page
•
Changed Package Temperature Range Features bullet to extend to 125°C ........................................................................ 1
•
Changed supply voltage and temperature range in last paragraph of Description section ................................................... 1
•
Changed maximum specifications in Supply voltage, All other pins, and Operating temperature parameters in
Absolute Maximum Ratings table ........................................................................................................................................... 5
•
Changed maximum specifications in VDD, PFI, and TJ parameters of Recommended Operating Conditions table .............. 5
•
Added TA = –40°C to 125°C rows to VIT– parameter of Electrical Characteristics table ........................................................ 6
•
Added second row to VIT–(S) parameter of Electrical Characteristics table............................................................................. 6
•
Changed IDD parameter of Electrical Characteristics table..................................................................................................... 7
•
Changed Typical Characteristics curves TPS3110E09 Supply Current vs Supply Voltage, TPS3110E09 Low-Level
Output Voltage vs Low-Level Output Current, TPS3110E09 Low-Level Output Voltage vs Low-Level Output Current,
TPS3110E09 High-Level Output Voltage vs High-Level Output Current, and TPS3110K33 High-Level Output
Voltage vs High-Level Output Current ................................................................................................................................. 11
•
Changed Normalized Threshold Voltage vs Free-Air Temperature curve ........................................................................... 12
•
Changed supply voltage range in first sentence of Overview section ................................................................................. 13
•
Changed supply voltage range in description of Application Information section ............................................................... 18
•
Changed Normalized Threshold Voltage vs Free-Air Temperature figure ........................................................................... 19
•
Changed supply voltage range in first sentence of Power Supply Recommendations section ........................................... 20
Changes from Revision E (September 2007) to Revision F
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
•
Changed title of document ..................................................................................................................................................... 1
•
Deleted Features bullet for SOT23-6 package ...................................................................................................................... 1
•
Changed front-page figure...................................................................................................................................................... 1
•
Changed second paragraph of Description section .............................................................................................................. 1
2
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Copyright © 2001–2016, Texas Instruments Incorporated
Product Folder Links: TPS3103 TPS3106 TPS3110
TPS3103, TPS3106, TPS3110
www.ti.com
SLVS363G – AUGUST 2001 – REVISED SEPTEMBER 2016
•
Changed fourth paragraph of Description section.................................................................................................................. 1
•
Changed Pin Configuration and Functions section; updated table format ............................................................................ 4
•
Changed "free-air temperature" to "junction temperature" in Absolute Maximum Ratings condition statement .................... 5
•
Deleted clamp current from Absolute Maximum Ratings table; changed to current .............................................................. 5
•
Deleted soldering temperature specification from Absolute Maximum Ratings table ............................................................ 5
•
Changed "free-air temperature" to "junction temperature" in Recommended Operating Conditions condition
statement ............................................................................................................................................................................... 5
•
Added Thermal Information table; deleted Dissipation Ratings table..................................................................................... 6
•
Changed "free-air temperature" to "junction temperature" in Electrical Characteristics condition statement ....................... 6
•
Changed "free-air temperature" to "junction temperature" in Electrical Characteristics condition statement ....................... 7
•
Changed Switching Characteristics table ............................................................................................................................... 8
•
Changed Figure 1 title and timing drawing ............................................................................................................................ 8
•
Changed Figure 2 title ............................................................................................................................................................ 9
•
Changed Figure 3................................................................................................................................................................... 9
•
Changed Figure 4................................................................................................................................................................. 10
Copyright © 2001–2016, Texas Instruments Incorporated
Product Folder Links: TPS3103 TPS3106 TPS3110
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TPS3103, TPS3106, TPS3110
SLVS363G – AUGUST 2001 – REVISED SEPTEMBER 2016
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5 Available Options
DEVICE
RESET OUTPUT
TPS3103
Open-drain
RSTSENSE, RSTVDD OUTPUT
SENSE INPUT
Open-drain
✓
PFO OUTPUT
Open-drain
TPS3106
TPS3110
WDI INPUT
✓
Push-pull
✓
6 Pin Configuration and Functions
TPS3103 DBV Package
6-Pin SOT-23
Top View
TPS3106 DBV Package
6-Pin SOT-23
Top View
RESET
1
6
VDD
RSTVDD
1
6
VDD
GND
2
5
PFO
GND
2
5
RSTSENSE
MR
3
4
PFI
MR
3
4
SENSE
TPS3110 DBV Package
6-Pin SOT-23
Top View
RESET
1
6
VDD
GND
2
5
WDI
MR
3
4
SENSE
Pin Functions
PIN
NAME
I/O
DESCRIPTION
TPS3103
TPS3106
TPS3110
GND
2
2
2
—
MR
3
3
3
I
Manual-reset input. Pull low to force a reset. RESET remains low as long as
MR is low and for the time-out period after MR goes high. Leave
unconnected or connect to VDD when unused.
PFI
4
—
—
I
Power-fail input compares to 0.551 V with no additional delay. Connect to
VDD if not used.
PFO
5
—
—
O
Power-fail output. Goes high when voltage at PFI rises above 0.551 V.
RESET
1
—
1
O
Active-low reset output. Either push-pull or open-drain output stage.
RSTSENSE
—
5
—
O
Active-low reset output. Logic level at RSTSENSE only depends on the
voltage at SENSE and the status of MR.
RSTVDD
—
1
—
O
Active-low reset output. Logic level at RSTVDD only depends on the voltage
at VDD and the status of MR.
SENSE
—
4
4
I
A reset is asserted if the voltage at SENSE is lower than 0.551 V. Connect
to VDD if unused.
VDD
6
6
6
I
Supply voltage. Powers the device and monitors its own voltage.
WDI
—
—
5
I
Watchdog timer input. If WDI remains high or low longer than the time-out
period, then reset is triggered. The timer clears when reset is asserted or
when WDI sees a rising edge or a falling edge.
4
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GND
Copyright © 2001–2016, Texas Instruments Incorporated
Product Folder Links: TPS3103 TPS3106 TPS3110
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SLVS363G – AUGUST 2001 – REVISED SEPTEMBER 2016
7 Specifications
7.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
Supply voltage (2)
VDD
–0.3
4
V
MR Pin, RESET (push-pull)
VMR, VRESET (push-pull)
–0.3
VDD + 0.3
V
–0.3
4
V
–5
5
mA
All other pins (2)
Maximum low output current
IOL
Maximum high output current
IOH
–5
5
mA
Input current
IIK (VSENSE < 0 V or VSENSE > VDD)
–10
10
mA
Output current
IOK (VO < 0 V or VO > VDD) (3)
–10
10
mA
Continuous total power dissipation
Temperature
(1)
(2)
(3)
See Thermal Information
Operating, TJ
–40
125
°C
Storage, Tstg
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to GND. For reliable operation, the device must not be operated at 3.6 V for more than t = 1000h
continuously.
Output is clamped for push-pull outputs by the back gate diodes internal to the IC. No clamp exists for the open-drain outputs.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating junction temperature range, unless otherwise noted.
MIN
VDD (1)
Supply voltage
VSENSE
SENSE voltage
WDI
High-level input voltage VIH at MR
WDI
Low-level input voltage VIL at MR
WDI
Input transition rise and fall rate at Δt/ΔV at MR
MR
MR voltage
PFI
PFI voltage
TJ
Operating temperature
(1)
NOM
MAX
UNIT
0.9
3.6
V
0
VDD
V
0.7 × VDD
V
0.3 × VDD
0
V
100
ns/V
VDD
V
0
3.6
V
–40
125
°C
For proper operation of SENSE, PFI, and WDI functions: VDD ≥ 0.8 V.
Copyright © 2001–2016, Texas Instruments Incorporated
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SLVS363G – AUGUST 2001 – REVISED SEPTEMBER 2016
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7.4 Thermal Information
TPS31xx
THERMAL METRIC (1)
DBV (SOT-23)
UNIT
6 PINS
RθJA
Junction-to-ambient thermal resistance
183.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
123.3
°C/W
RθJB
Junction-to-board thermal resistance
29.4
°C/W
ψJT
Junction-to-top characterization parameter
20.5
°C/W
ψJB
Junction-to-board characterization parameter
29
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.5 Electrical Characteristics
over operating junction temperature range (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDD = 3.3 V, IOH = –3 mA
VDD = 1.8 V, IOH = –2 mA
VOH
High-level output voltage
VDD = 1.5 V, IOH = –1 mA
0.8 × VDD
V
VDD = 0.9 V, IOH = –0.4 mA
VDD = 0.5 V, IOH = –5 μA
0.7 × VDD
VDD = 3.3 V, IOL = 3 mA
VOL
VDD = 1.5 V, IOL = 2 mA
Low-level output voltage
VDD = 1.2 V, IOL = 1 mA
0.3
V
0.1
V
VDD = 0.9 V, IOL = 500 μA
VOL
Low-level output voltage
RESET only
0.854
0.86
0.866
TPS31xxE12
1.133
1.142
1.151
1.423
1.434
1.445
1.512
1.523
1.534
TPS31xxH20
1.829
1.843
1.857
TPS31xxK33
2.919
2.941
2.963
TPS31xxE09
0.817
0.903
TPS31xxE12
1.084
1.199
1.362
1.505
TPS31xxE15
TPS31xxE16
Negative-going input
threshold voltage (1)
VIT–
VDD = 0.4 V, IOL = 5 μA
TPS31xxE09
TPS31xxE15
TA = 25°C
TA = –40°C to 125°C
TPS31xxK33
VIT–(S)
Negative-going input
threshold voltage (1)
VHYS
Hysteresis at VDD input
2.823
VDD ≥ 0.8 V, TA = 25°C
SENSE, PFI
VDD ≥ 0.8 V, TA = –40°C to
125°C
0.5
20
30
2.5 V ≤ VIT– < 3.3 V
50
–0.012
TA = –40°C to 85°C
VHYS(S)
Hysteresis at SENSE, PFI input
VDD ≥ 0.8 V
IIH
High-level input current
0.559
0.58
1.6 V ≤ VIT– < 2.4 V
Temperature coefficient of VIT−, PFI,
SENSE
6
3.058
0.551
0.8 V ≤ VIT– < 1.5 V
T(K)
(1)
0.542
V
V
mV
–0.019
15
%/K
mV
MR
MR = VDD, VDD = 3.3 V
–25
25
SENSE, PFI,
WDI
SENSE, PFI, WDI = VDD,
VDD = 3.3 V
–25
25
nA
To ensure the best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 μF) should be placed close to the supply
terminals.
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SLVS363G – AUGUST 2001 – REVISED SEPTEMBER 2016
Electrical Characteristics (continued)
over operating junction temperature range (unless otherwise noted).
PARAMETER
IIL
Low-level input current
IOH
High-level output current
at RESET (2)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
–33
–25
μA
25
nA
200
nA
MR
MR = 0 V, VDD = 3.3 V
–47
SENSE, PFI,
WDI
SENSE, PFI, WDI = 0 V,
VDD = 3.3 V
–25
Open-drain
VDD = VIT– + 0.2 V, VOH = 3.3 V
TA = –40°C to 85°C, VDD > VIT–
(average current), VDD < 1.8 V
1.2
TA = –40°C to 125°C, VDD > VIT–
(average current), VDD < 1.8 V
3
TA = –40°C to 85°C, VDD > VIT–
(average current), VDD > 1.8 V
IDD
Supply current
(2)
2
4.5
TA = –40°C to 125°C, VDD > VIT–
(average current), VDD > 1.8 V
5.5
TA = –40°C to 85°C, VDD < VIT–,
VDD < 1.8 V
22
TA = –40°C to 125°C, VDD <
VIT–, VDD < 1.8 V
27
TA = –40°C to 85°C, VDD < VIT–,
VDD > 1.8 V
27
TA = –40°C to 125°C, VDD <
VIT–, VDD > 1.8 V
32
Internal pullup resistor at MR
CIN
3
μA
70
Input capacitance at MR, SENSE, PFI, WDI VIN = 0 V to VDD
100
130
1
kΩ
pF
Also refers to RSTVDD and RSTSENSE.
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7.6 Timing Requirements
At RL = 1 MΩ, CL = 50 pF, and TA = –40°C to 85°C, unless otherwise noted.
tT(OUT)
Time-out period
tW
Pulse duration
MIN
TYP
MAX
UNIT
0.55
1.1
1.65
s
at WDI
VDD ≥ 0.85 V
at VDD
VIH = 1.1 × VIT–, VIL = 0.9 × VIT–, VIT– = 0.86 V
20
at MR
VDD ≥ VIT– + 0.2 V, VIL = 0.3 × VDD, VIH = 0.7 × VDD
0.1
at SENSE
VDD ≥ VIT–, VIH = 1.1 × VIT − (S), VIL = 0.9 × VIT − (S)
20
at PFI
VDD ≥ 0.85 V, VIH = 1.1 × VIT − (S),VIL = 0.9 × VIT − (S)
20
at WDI
VDD ≥ VIT–, VIL = 0.3 × VDD, VIH = 0.7 × VDD
0.3
μs
7.7 Switching Characteristics
At RL = 1 MΩ, CL = 50 pF, and TA = –40°C to 85°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
VDD ≥ 1.1 × VIT–, MR = 0.7 × VDD.
See Timing Requirements.
MIN
TYP
MAX
UNIT
65
130
195
ms
tD
Delay time
tPHL(VDD)
Propagation delay time,
high-to-low level output
VDD to RESET or
RSTVDD delay
VIH = 1.1 × VIT–, VIL = 0.9 × VIT–
40
μs
tPHL(SENSE)
Propagation delay time,
high-to-low level output
SENSE to RESET or
RSTSENSE delay
VDD ≥ 0.8 V, VIH = 1.1 × VIT–, VIL = 0.9 × VIT–
40
μs
tPHL(PFO)
Propagation delay time,
high-to-low level output
PFI to PFO delay
VDD ≥ 0.8 V, VIH = 1.1 × VIT–, VIL = 0.9 × VIT–
40
μs
tPLH(PFO)
Propagation delay time,
low-to-high level output
PFI to PFO delay
VDD ≥ 0.8 V, VIH = 1.1 × VIT–, VIL = 0.9 × VIT–
300
μs
tPHL(MR)
Propagation delay time,
high-to-low level output
MR to RESET.
RSTVDD,
RSTSENSE delay
VDD ≥ 1.1 × VIT–, VIL = 0.3 × VDD, VIH = 0.7 × VDD
5
μs
1
VDD
VIT0.4 V
t
tD
tD
tD
tD
RESET
Output Condition
Undefined
Output Condition
Undefined
t
MR
t
Figure 1. RESET Timing Diagram for TPS3103
8
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SLVS363G – AUGUST 2001 – REVISED SEPTEMBER 2016
PFI
VIT - (S) = 0.551 V
t
PFO
Output Condition
Undefined
Output Condition
Undefined
t
Figure 2. PFO Timing Diagram for TPS3103
VDD
VIT0.4 V
tD
t
tD
RSTVDD
Output Condition
Undefined
Output Condition
Undefined
t
SENSE
VIT-(S) = 0.551 V
t
tD
RSTSENSE
Output Condition
Undefined
Output Condition
Undefined
tD
t
MR
t
Figure 3. Timing Diagram for TPS3106
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VDD
VIT0.4 V
t
SENSE
VIT-(S) = 0.551 V
tD
tD
tD
t
tD
RESET
tD
Output Condition
Undefined
Output Condition
Undefined
t
t(TOUT)
WDI
x = Don’t Care
t
MR
t
Figure 4. Timing Diagram for TPS3110
10
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SLVS363G – AUGUST 2001 – REVISED SEPTEMBER 2016
7.8 Typical Characteristics
22
0.55
TA = -40°C
TA = 0°C
TA = 25°C
TA = 85°C
TA = 105°C
TA = 125°C
20
16
14
0.45
0.4
0.35
VOL (V)
Supply Current (PA)
18
12
10
0.3
0.25
8
0.2
6
0.15
4
0.1
2
0.05
0
0
0
0.4
0.8
1.2
1.6
2
2.4
Supply Voltage (V)
2.8
3.2
3.6
0
SENSE = VDD, MR = open, RESET = open, WDI: triggered
0.2
0.6
0.8
1
1.2
IOL (mA)
1.4
1.6
1.8
2
Figure 6. TPS3110E09 Low-Level Output Voltage vs
Low-Level Output Current
1
0.9
TA = -40°C
TA = 0°C
TA = 25°C
TA = 85°C
TA = 105°C
TA = 125°C
0.9
0.8
0.7
VOH (V)
0.6
0.85
0.5
0.4
0.8
0.75
TA = -40°C
TA = 0°C
TA = 25°C
TA = 85°C
TA = 105°C
TA = 125°C
0.3
0.2
0.7
0.1
0
0.65
0
2
4
6
8
10
12
IOL (mA)
14
16
18
20
0
0.1
0.2
0.3
0.4
0.5
IOH (mA)
VDD = 3.3 V, SENSE = GND, MR = GND, WDI: GND
VDD = 0.9 V, SENSE = VDD, MR = VDD, WDI: triggered
Figure 7. TPS3110E09 Low-Level Output Voltage vs
Low-Level Output Current
Figure 8. TPS3110E09 High-Level Output Voltage vs
High-Level Output Current
50
tW - Minimum Pulse Duration at VDD - ms
3.3
3.2
3.1
VOH (V)
0.4
VDD = 0.9 V, SENSE = GND, MR = GND, WDI: GND
Figure 5. TPS3110E09 Supply Current vs Supply Voltage
VOL (V)
TA = -40°C
TA = 0°C
TA = 25°C
TA = 85°C
TA = 105°C
TA = 125°C
0.5
3
2.9
TA = -40°C
TA = 0°C
TA = 25°C
TA = 85°C
TA = 105°C
TA = 125°C
2.8
2.7
2
40
35
30
VDD = 3.3 V
25
20
15
10
VDD = 0.9 V
5
0
2.6
0
MR : Open
SENSE = VDD
45
4
6
8
10
IOH (mA)
0
0.1
0.2
0.3
0.4
0.5
VDD - Threshold Overdrive Voltage - V
VDD = 3.3 V, SENSE = VDD, MR = VDD, WDI: triggered
Figure 9. TPS3110K33 High-Level Output Voltage vs
High-Level Output Current
Figure 10. Minimum Pulse Duration at VDD vs
Threshold Overdrive Voltage
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Typical Characteristics (continued)
1.008
Normalized VIT (V)
1.005
1.002
0.999
0.996
0.993
0.99
-40
-25
-10
5
20
35 50
TA (qC)
65
80
95
110 125
Figure 11. Normalized Threshold Voltage vs Free-Air Temperature
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8 Detailed Description
8.1 Overview
The TPS310x and TPS311x families of supervisory circuits operate from supply voltages from 0.9 V to 3.6 V and
provide circuit initialization and timing supervision for DSP- and processor-based systems. During power-on,
RESET is asserted when the supply voltage (VDD) exceeds 0.4 V. The devices monitor VDD and keep the RESET
output low as long as VDD remains below the threshold voltage (VIT–). To ensure proper system reset, after VDD
surpasses the threshold voltage plus the hysteresis (VIT– + VHYS) an internal timer delays the transition of the
RESET signal from low to high for the specified time. The delay time starts after VDD has risen above (VIT– +
VHYS). When VDD drops below VIT–, the output becomes active again.
All the devices of this family have a fixed-VDD threshold voltage (VIT–) set by an internal voltage divider. The
TPS3103 and TPS3106 devices both have an active-low, open-drain RESET output. The TPS3103 device has
an integrated power-fail input (PFI) and corresponding power-fail output (PFO) that can be used for low-battery
detection or for monitoring a power supply other than the input supply. The TPS3106 device has a SENSE input
with a corresponding output (RSTSENSE) for monitoring voltages other than the input supply. The TPS3110
device has an active-low push/pull RESET and a watchdog timer that is used for monitoring the operation of
microprocessors. All three devices have manual reset pin (MR) that can be used to force the outputs low
regardless of the sensed voltages.
8.2 Functional Block Diagrams
TPS3103
VDD
+
_
MR
Reset Logic
and Timer
+
_
PFI
RESET
PFO
0.551 V
GND
Figure 12. TPS3103 Functional Block Diagram
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Functional Block Diagrams (continued)
TPS3106
VDD
+
_
MR
RSTSENSE
Reset Logic
and Timer
+
_
SENSE
RSTVDD
Reset Logic
and Timer
0.551 V
GND
Figure 13. TPS3106 Functional Block Diagram
TPS3110
VDD
+
_
MR
+
_
SENSE
Reset Logic
and Timer
RESET
0.551 V
Watchdog
Logic and
Control
WDI
GND
Figure 14. TPS3110 Functional Block Diagram
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8.3 Feature Description
8.3.1 Watchdog
The TPS3110 device integrates a watchdog timer that must be periodically triggered by a positive or negative
transition of WDI. When the supervising system fails to retrigger the watchdog circuit within the time-out interval,
RESET becomes active for the time period (tD). This event also reinitializes the watchdog timer.
8.3.2 Manual Reset (MR)
Many μC-based products require manual-reset capability, allowing an operator or logic circuitry to initiate a reset.
Logic low at MR asserts reset. Reset remains asserted while MR is low and for a time period (tD) after MR
returns high. The input has an internal 100-kΩ pullup resistor, so it can be left open if it is unused.
Connect a normally open momentary switch from MR to GND to create a manual reset function. External
debounce is not required. If MR is driven from long cables or if the device is used in noisy environments,
connecting a 0.1-μF capacitor from MR to GND provides additional noise immunity.
If there is a possibility of transient or DC conditions causing MR to rise above VDD, a diode should be used to
limit MR to a diode drop above VDD.
8.3.3 PFI, PFO
The TPS3103 has an integrated power-fail (PFI) comparator with a separate open-drain (PFO) output. The PFI
and PFO can be used for low-battery detection, power-fail warning, or for monitoring a power supply other than
the main supply, and has no effect on RESET.
An additional comparator is provided to monitor voltages other than the nominal supply voltage. The power-fail
input (PFI) will be compared with an internal voltage reference of 0.551 V. If the input voltage falls below the
power-fail threshold (VIT – (S)), the power-fail output (PFO) goes low. If it goes above 0.551 V plus approximately
15-mV hysteresis, the output returns to high. By connecting two external resistors, it is possible to supervise any
voltage above 0.551 V. The sum of both resistors should be approximately 1 MΩ, to minimize power
consumption and to assure that the current into the PFI pin can be neglected, compared with the current through
the resistor network. The tolerance of the external resistors should be not more than 1% to ensure minimal
variation of sensed voltage. If the power-fail comparator is unused, connect PFI to GND and leave PFO
unconnected. For proper operation of the PFI-comparator, the supply voltage (VDD) must be higher than 0.8 V.
8.3.4 SENSE
The voltage at the SENSE input is compared with a reference voltage of 0.551 V. If the voltage at SENSE falls
below the sense-threshold (VIT − (S)), reset is asserted. On the TPS3106 device, a dedicated RSTSENSE output
is available. On the TPS3110 device, the logic signal from SENSE is OR-wired with the logic signal from VDD or
MR. An internal timer delays the return of the output to the inactive state, once the voltage at SENSE goes
above 0.551 V plus about 15 mV of hysteresis. For proper operation of the SENSE-comparator, the supply
voltage must be higher than 0.8 V.
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Feature Description (continued)
2V
VDD
(1)
(1)
TPS3103H20
R1
MR
RESET
PFI
R2
VDD
MSP430
Low-Power μC
Px.x
RESET
Analog
Circuit
Py.x
PFO
GND
GND
–2 V
V(NEG_TH) = 0.551 V – R2 (VDD – 0.551 V)
R1
(1)
Resistor may be integrated in microcontroller.
Figure 15. TPS3103 Monitoring a Negative Voltage
3.3 V
1.5 V
VCORE
VDD
V(CORE_TH) = 0.551 V x R1 + R2
R2
R1
TPS3110K33
MR
RESET
SENSE
DSP
RESET
Px.y
WDI
R2
VIO
GND
GND
GND
Figure 16. TPS3110 in a DSP-System Monitoring Both Supply Voltages
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8.4 Device Functional Modes
Table 1. TPS3103 Function Table
(1)
MR
V(PFI) > 0.551 V
VDD > VIT–
RESET
PFO
L
0
X (1)
L
L
L
1
X
L
H
H
0
0
L
L
H
0
1
H
L
H
1
0
L
H
H
1
1
H
H
X = Don’t care.
Table 2. TPS3106 Function Table
MR
VDD > VIT–
RSTVDD
RSTSENSE
(1)
X
L
L
H
0
0
L
L
H
0
1
H
L
H
1
0
L
H
H
1
1
H
H
L
(1)
V(SENSE) > 0.551 V
X
X = Don’t care.
Table 3. TPS3110 Function Table (1)
MR
V(SENSE) > 0.551 V
VDD > VIT–
RESET
(2)
X
L
H
0
0
L
H
0
1
L
H
1
0
L
H
1
1
H
L
(1)
(2)
X
Function of watchdog timer not shown.
X = Don’t care.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS310x and TPS311x families are supervisory circuits made to monitor the input supply and other external
voltages greater than 0.551 V. These devices are made to operate from and monitor input supplies ranging from
0.9 V to 3.6 V, and all versions have a manual reset pin. The TPS3103 and TPS3106 both have an active-low,
open-drain RESET output. The TPS3103 device has an integrated power-fail input (PFI) and corresponding
power-fail output (PFO) that can be used for low-battery detection or for monitoring a power supply other than
the input supply and has a short delay time for more immediate triggering of the output. The TPS3106 device has
a SENSE input with a corresponding output (RSTSENSE) for monitoring voltages other than the input supply and
a longer delay time than the TPS3103 device to minimize accidental triggering of the output. The TPS3110
device has an active-low push/pull RESET and a watchdog timer that is used for monitoring the operation of
microprocessors.
9.2 Typical Application
VDD
R1
TPS3106E09DBV
R3
MR
2 Cell
NiMH
RSTVDD
SENSE
RSTSENSE
R2
Reset Output
GND
Figure 17. Battery Monitoring With 3-μA Supply Current for Device and Resistor Divider
9.2.1 Design Requirements
In some applications it is necessary to minimize the quiescent current even during the reset period. This is
especially true when the voltage of a battery is supervised and the RESET is used to shut down the system or
for an early warning. In this case the reset condition will last for a longer period of time. The current drawn from
the battery should almost be zero, especially when the battery is discharged.
For this kind of application, either the TPS3103 or TPS3106 device is a good fit. To minimize current
consumption, select a version where the threshold voltage is lower than the voltage monitored at VDD. The
TPS3106 device has two reset outputs. One output (RSTVDD) is triggered from the voltage monitored at VDD.
The other output (RSTSENSE) is triggered from the voltage monitored at SENSE. In the application shown in
Figure 17, the TPS3106E09 device is used to monitor the input voltage of two NiCd or NiMH cells. The threshold
voltage [V(TH) = 0.86 V] was chosen as low as possible to ensure that the supply voltage is always higher than
the threshold voltage at VDD. The voltage of the battery is monitored using the SENSE input.
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Typical Application (continued)
9.2.2 Detailed Design Procedure
The voltage divider was calculated to assert a reset using the RSTSENSE output at 2 × 0.8 V = 1.6 V, using
Equation 1.
R 1 = R2 ´
VTRIP
-1
VIT-(S)
where
•
•
•
•
•
•
VTRIP is the voltage of the battery at which a reset is asserted
VIT–(S) is the threshold voltage at SENSE = 0.551 V
R1 was chosen for a resistor current in the 1-μA range
With VTRIP = 1.6 V
R1 ≡ 1.9 × R2
R1 = 820 kΩ, R2 = 430 kΩ
(1)
9.2.3 Application Curve
1.008
Normalized VIT (V)
1.005
1.002
0.999
0.996
0.993
0.99
-40
-25
-10
5
20
35 50
TA (qC)
65
80
95
110 125
Figure 18. Normalized Threshold Voltage vs Free-Air Temperature
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10 Power Supply Recommendations
These devices are designed to operate from an input supply with a voltage range between 0.9 V and 3.6 V.
Though not required, it is good analog design practice to place a 0.1-μF ceramic capacitor close to the VCC pin if
the input supply is noisy.
11 Layout
11.1 Layout Guidelines
Follow these guidelines to lay out the printed-circuit-board (PCB) that is used for the TPS310x and TPS3110x
family of devices.
• Place the VDD decoupling capacitor close to the device.
• Avoid using long traces for the VCC supply node. The VCC capacitor (CVDD), along with parasitic inductance
from the supply to the capacitor, can form an LC tank and create ringing with peak voltages above the
maximum VDD voltage.
11.2 Layout Example
Pullup
Voltage
RP1
CVDD
RSTVDD
Flag
MR
Signal
Pullup
Voltage
TPS3106
1
6
2
5
3
4
RP2
RSTSENSE
Flag
R1
Monitored
Voltage
R2
Figure 19. Example Layout (DBV Package)
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
12.1.1.1 Spice Models
Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of
analog circuits and systems. SPICE models for the TPS310x and TPS311x are available through the respective
product folders under Tools & Software.
12.1.2 Device Nomenclature
Table 4. Ordering Information (1)
(1)
(2)
PRODUCT
NOMINAL SUPPLY VOLTAGE
THRESHOLD VOLTAGE, VIT– (2)
TPS3103E12DBVR
1.2 V
1.142 V
1.434 V
TPS3103E15DBVR
1.5 V
TPS3103H20DBVR
2.0 V
1.84 V
TPS3103K33DBVR
3.3 V
2.941 V
TPS3106E09DBVR
0.9 V
0.86 V
TPS3106E16DBVR
1.6 V
1.521 V
TPS3106K33DBVR
3.3 V
2.941 V
TPS3110E09DBVR
0.9 V
0.86 V
TPS3110E12DBVR
1.2 V
1.142 V
TPS3110E15DBVR
1.5 V
1.434 V
TPS3110K33DBVR
3.3 V
2.941 V
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
Custom threshold voltages are available. Minimum order quantities apply. Contact factory for details and availability.
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 5. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS3103
Click here
Click here
Click here
Click here
Click here
TPS3106
Click here
Click here
Click here
Click here
Click here
TPS3110
Click here
Click here
Click here
Click here
Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
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12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPS3103E12DBVR
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PFWI
Samples
TPS3103E12DBVRG4
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PFWI
Samples
TPS3103E12DBVT
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PFWI
Samples
TPS3103E15DBVR
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PFXI
Samples
TPS3103E15DBVT
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PFXI
Samples
TPS3103E15DBVTG4
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PFXI
Samples
TPS3103H20DBVR
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PFYI
Samples
TPS3103H20DBVT
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PFYI
Samples
TPS3103K33DBVR
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PGRI
Samples
TPS3103K33DBVRG4
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PGRI
Samples
TPS3103K33DBVT
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PGRI
Samples
TPS3103K33DBVTG4
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PGRI
Samples
TPS3106E09DBVR
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PFZI
Samples
TPS3106E09DBVRG4
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PFZI
Samples
TPS3106E09DBVT
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PFZI
Samples
TPS3106E09DBVTG4
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PFZI
Samples
TPS3106E16DBVR
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PGSI
Samples
TPS3106E16DBVRG4
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PGSI
Samples
TPS3106E16DBVT
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PGSI
Samples
TPS3106E16DBVTG4
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PGSI
Samples
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
14-Oct-2022
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPS3106K33DBVR
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PGBI
Samples
TPS3106K33DBVRG4
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PGBI
Samples
TPS3106K33DBVT
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PGBI
Samples
TPS3106K33DBVTG4
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PGBI
Samples
TPS3110E09DBVR
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PGII
Samples
TPS3110E12DBVR
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PGJI
Samples
TPS3110E12DBVT
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PGJI
Samples
TPS3110E15DBVR
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PGKI
Samples
TPS3110E15DBVT
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PGKI
Samples
TPS3110K33DBVR
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PGLI
Samples
TPS3110K33DBVT
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PGLI
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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