TPS7B4255DBVR

TPS7B4255 SBVS441 – DECEMBER 2022 TPS7B4255 70-mA, 40-V, Voltage-Tracking LDO With Voltage-Buffering Capability 1 Features 3 Description • The TPS7B4255 is a low-dropout (LDO) voltagetracking regulator, with high tracking accuracy and excellent load and line transient response. The device is available in a 5-pin, SOT-23 (DBV) package. The TPS7B4255 is designed to supply off-board sensors in industrial applications such as condition monitoring sensor systems. The device provides integrated protection features such as reverse polarity, output short to supply and ground, current limit, and thermal shutdown to protect against the high risk of cable failures in an off-board power system. The device is designed to survive a 45-V (absolute maximum) input voltage during extreme transient events. • • • • • • • • • • • • • Wide input operating voltage range (3 V to 40 V): – Absolute maximum input range: –40 V to +45 V Wide output voltage range: 2 V to 30 V Very-tight, output-tracking tolerance: 5 mV (max) Low dropout voltage: 500 mV (max) at 70 mA Reverse polarity protection Reverse current protection Combined reference and enable input Low quiescent current at light loads (100-μA load): – 50 μA (max) Wide ESR range: – Stable with 1-µF to 200-µF ceramic output capacitor, 1-mΩ to 3-Ω ESR Overtemperature protection Output short-circuit protection to ground and supply Junction temperature: –40°C to +150°C, TJ Available in 5-pin SOT-23 DBV package Buffers signals up to 1 kHz (see the SignalBuffering LDO section) A reference voltage applied at the ADJ/EN pin is effectively tracked with high accuracy for loads up to 70 mA. The high tracking accuracy provides accurate power supply to off-board modules and enables better accuracy when making measurements using ratiometric sensors. By setting the ADJ/EN input pin low, the TPS7B4255 switches to standby mode and reduces the quiescent current to the minimum value. 2 Applications • • • • • Condition monitoring sensors Motion detectors (PIR, uWave, and so forth) Wired controls Telemetry and RTUs Robot sensing modules Package Information(1) PART NUMBER TPS7B4255 (1) PACKAGE DBV (SOT-23, 5) BODY SIZE (NOM) 2.90 mm × 1.60 mm For all available packages, see the orderable addendum at the end of the data sheet. DC Supply IN IN DC/DC converter or LDO OUT TPS7B4255 ADJ/EN OUT 5V Sensor 1 MCU ADC Control Unit Board Typical Application An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS7B4255 www.ti.com SBVS441 – DECEMBER 2022 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................3 6 Specifications.................................................................. 3 6.1 Absolute Maximum Ratings........................................ 3 6.2 ESD Ratings............................................................... 3 6.3 Recommended Operating Conditions.........................4 6.4 Thermal Information....................................................4 6.5 Electrical Characteristics.............................................5 Timing Characteristics.......................................................5 6.6 Typical Characteristics................................................ 6 7 Detailed Description........................................................8 7.1 Overview..................................................................... 8 7.2 Functional Block Diagram........................................... 8 7.3 Feature Description.....................................................8 7.4 Device Functional Modes..........................................11 8 Application and Implementation.................................. 12 8.1 Application Information............................................. 12 8.2 Typical Application.................................................... 13 8.3 Power Supply Recommendations.............................15 8.4 Layout....................................................................... 15 9 Device and Documentation Support............................18 9.1 Device Support......................................................... 18 9.2 Receiving Notification of Documentation Updates....18 9.3 Support Resources................................................... 18 9.4 Trademarks............................................................... 18 9.5 Electrostatic Discharge Caution................................18 9.6 Glossary....................................................................18 10 Mechanical, Packaging, and Orderable Information.................................................................... 18 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. 2 DATE REVISION NOTES December 2022 * Initial Release Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS7B4255 TPS7B4255 www.ti.com SBVS441 – DECEMBER 2022 5 Pin Configuration and Functions ADJ/EN 1 GND 2 IN 3 5 NC 4 OUT Not to scale Figure 5-1. DBV Package, 5-Pin SOT-23 (Top View) Table 5-1. Pin Functions PIN NAME NO. TYPE DESCRIPTION ADJ/EN pin. Connect the reference voltage to this pin. This pin connects to the error amplifier internally. A low signal below VIL disables the device and a high signal above VIH enables the device. Connect the voltage reference directly or with a voltage divider for lower output voltages. To compensate for line influences, place a capacitor close to this pin. ADJ/EN 1 I GND 2 — Ground pin. NC 5 — This pin is not internally connected. Connect this pin to GND for improved thermal performance. IN 3 I Input power-supply voltage pin. This pin is the device supply. For best transient response and to minimize input impedance, use the recommended value or larger ceramic capacitor from IN to GND as listed in the Recommended Operating Conditions table. Place the input capacitor as close to the input of the device as possible to compensate for line influences. O Regulated output voltage pin. A capacitor is required from OUT to GND for stability. For best transient response, use the nominal recommended value or larger ceramic capacitor from OUT to GND; see the Recommended Operating Conditions table. Place the output capacitor as close to output of the device as possible. OUT 4 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VIN Unregulated input voltage -40 45 V VOUT Regulated output voltage –5 45 V VADJ/EN Adjustable input and enable input voltage -0.3 45 V VIN - VOUT Input output voltage difference -40 40 V TJ Operating junction temperature –40 150 °C Tstg Storage temperature –65 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect the device reliability, functionality, performance, and shorten the device lifetime. 6.2 ESD Ratings VALUE Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) V(ESD) (1) (2) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22-C101(2) UNIT ±1000 All pins ±500 Corner pins ±750 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS7B4255 3 TPS7B4255 www.ti.com SBVS441 – DECEMBER 2022 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN TYP MAX UNIT VIN Unregulated input voltage 3 40 VOUT Regulated output voltage 2 30 V IOUT Output current 0 70 mA CIN Input capacitor(1) 0 capacitor(2) COUT Output ESR Output capacitor ESR requirements TJ Operating junction temperature (1) (2) 1 V µF 1 200 0.001 3 µF Ω –40 150 °C For robust EMI performance the minimum input capacitance is 500 nF. Effective output capacitance of 500 nF minimum required for stability. 6.4 Thermal Information TPS7B4255 THERMAL METRIC(1) DBV (SOT-23)(2) UNIT 5 PINS RθJA Junction-to-ambient thermal resistance 176.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 75.6 °C/W RθJB Junction-to-board thermal resistance 44.4 °C/W ΨJT Junction-to-top characterization parameter 17.9 °C/W ΨJB Junction-to-board characterization parameter 44.1 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W (1) (2) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Evaluated using JEDEC standard (2s2p). Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS7B4255 TPS7B4255 www.ti.com SBVS441 – DECEMBER 2022 6.5 Electrical Characteristics specified at TJ = –40°C to +150°C, VIN = 13.5 V, IOUT = 100 µA, COUT = 1 µF, 1 mΩ < COUT ESR < 2 Ω, CIN = 1 µF, and VADJ = 5 V (unless otherwise noted), typical values are at TJ = 25°C PARAMETER TEST CONDITIONS MIN TYP –5 MAX UNIT ΔVOUT Output voltage tracking accuracy VIN = VOUT + 600 mV to 40 V, IOUT = 100 µA to 70 mA 5 mV ΔVOUT(ΔVIN) Line regulation VIN = VOUT + 600 mV to 40 V 0.5 mV ΔVOUT(ΔIOUT) Load regulation VIN = VOUT + 600 mV, IOUT = 100 µA to 70 mA (1) 0.5 mV VIN = 5.6 V to 40 V, IOUT = 100 µA, TJ = 25ºC IQ Quiescent current IGND Ground current 34 40 VIN = 5.6 V to 40 V, IOUT = 100 µA, -40ºC < TJ < 85ºC 45 VIN = 5.6 V to 40 V, IOUT = 100 µA 50 VIN = 5.6 V to 40 V, IOUT = 70 mA, TJ = 25ºC 470 VIN = 5.6 V to 40 V, IOUT = 70 mA 550 IOUT = 70 mA, VADJ ≥ 3.3 V, VIN = VADJ 470 IOUT = 50 mA, VADJ ≥ 4 V, VIN = VADJ 330 µA VDO Dropout voltage ISHUTDOWN Shutdown supply current (IGND) IADJ/EN ADJ/EN pin current VUVLO(RISING) Rising input supply UVLO VIN rising 2.6 2.7 2.81 VUVLO(FALLING) Falling input supply UVLO VIN falling 2.3 2.4 2.5 VUVLO(HYST) VUVLO(IN) hysteresis VIL Adjustable and enable logic input low level VIH Adjustable and enable logic input high level ICL Output current limit VIN = VOUT + 1 V, VOUT short to 90% x VADJ PSRR Power-supply ripple rejection VIN - VOUT = 1 V, Frequency = 100 Hz, IOUT = 70 mA Vn Output noise voltage VOUT = 3.3 V, IOUT = 1 mA, a 5 µVRMS reference is used for this measurement IR Reverse current at VIN VIN = 0 V, VOUT = 20 V, VADJ = 5 V -0.25 0.25 IRN1 Reverse current at negative VIN VIN = -20 V, VOUT = 20 V, VADJ = 5 V -0.5 0.5 IRN2 Reverse current at negative VIN VIN = -20 V, VOUT = 0 V, VADJ = 5 V -0.5 0.5 TJ Junction temperature TSD(SHUTDOWN) Junction shutdown temperature 175 °C TSD(HYST) Hysteresis of thermal shutdown 15 °C (1) VADJ/EN = 0 V 3 0.25 300 mV µA V mV 1 V 1.65 75 100 130 mA 80 dB 150 µVRMS –40 150 µA °C Power dissipation is limited to 2 W for device production testing purposes. The power dissipation can be higher during normal operation. Please see the thermal dissipation section for more information on how much power the device can dissipate while maintaining a junction temperature below 150℃. Timing Characteristics specified at VIN = 13.5 V, IOUT = 100 µA, COUT = 1 µF, CIN = 1 µF, and VADJ = 5 V (unless otherwise noted), typical values are at TJ = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Timing Characteristics tstartup Startup time Time from EN high to VOUT = 95% × VADJ 255 µs Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS7B4255 5 TPS7B4255 www.ti.com SBVS441 – DECEMBER 2022 6.6 Typical Characteristics VIN = VADJ/EN = 5 V VIN = VADJ/EN = 5 V, IOUT = 5 mA, 20 mA, 50 mA, 70 mA Figure 6-2. Dropout Voltage vs Output Current Figure 6-1. Dropout Voltage vs Temperature 600 100µA 20mA 500 50mA 70mA IGND (A) 400 300 200 100 0 -55 -30 VIN = 13.5 V, VADJ/EN = 5 V -5 20 45 70 Temperature (C) 95 120 145 VIN = 13.5 V, VADJ/EN = 5 V Figure 6-3. Ground Current vs Output Current Figure 6-4. Ground Current vs Temperature 120 115 Current Limit (mA) 110 105 100 95 90 85 80 -55 -30 -5 20 45 70 Temperature (C) 95 120 145 VIN = 13.5 V, VADJ/EN = 5 V VIN = 13.5 V, VADJ/EN = 5 V Figure 6-5. Current Limit vs Temperature 6 Figure 6-6. Tracking Error vs Temperature Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS7B4255 TPS7B4255 www.ti.com SBVS441 – DECEMBER 2022 6.6 Typical Characteristics (continued) 8 -55°C -40°C 7 0°C 25°C 85°C 125°C 150°C 6 VOUT (V) 5 4 3 2 1 0 -1 5 10 15 20 VIN (V) 25 30 35 40 VADJ/EN = 5 V, IOUT = 10 mA VIN = 13.5 V, IOUT = 10 mA Figure 6-7. Output Voltage vs Input Voltage Figure 6-8. Output Voltage vs Adjustable Voltage IOUT (mA) 80 70 30 IOUT VOUT 20 60 10 50 0 40 -10 30 -20 20 -30 10 -40 0 0 VADJ/EN = 5 V, COUT = 10 μF, VIN = 9 V to 16 V 100 200 300 400 500 600 Time (s) 700 800 -50 900 1000 AC Coupled Output Voltage - VOUT (mV) 0 VIN = 13.5 V, VADJ/EN = 5 V, COUT = 10 μF, IOUT = 1 mA to 30 mA Figure 6-9. Line Transient Figure 6-10. Load Transient VIN = 13.5 V, COUT = 10 µF, IOUT = 1 mA, 10 mA, 50 mA, 70 mA, VADJ/EN = 5 V Figure 6-12. Load Capacitance vs ESR Stability Figure 6-11. Power-Supply Rejection Ratio vs Frequency Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS7B4255 7 TPS7B4255 www.ti.com SBVS441 – DECEMBER 2022 7 Detailed Description 7.1 Overview The TPS7B4255 is an integrated, low-dropout (LDO) voltage tracker with ultra-low tracking tolerance. Because of the high risk of cable shorts when powering sensors off-board, multiple protection features are built into the LDO including short to battery, short to GND, and reverse current protection. This device features thermal shutdown protection, brick-wall current limiting, undervoltage lockout (UVLO), and reverse current protection. 7.2 Functional Block Diagram IN OUT VIN Load Reverse Current Protection Internal Supply Brick-wall Current Limit UVLO + Logic Control – Thermal Shutdown ADJ/EN VREF GND Figure 7-1. Functional Block Diagram 7.3 Feature Description 7.3.1 Regulated Output (VOUT) This device is a tracking LDO; thus, the output voltage is determined by the voltage provided to the ADJ/EN pin, provided that VIN is greater than VIH. When the voltage at the ADJ/EN pin exceeds the required voltage to enable the LDO (VIH), the output begins to rise to the voltage on the ADJ/EN pin. The output rises linearly as determined by the load, the output capacitor, and the current limit. When the voltage reaches the level on the ADJ/EN pin, the output voltage remains within 5 mV from the voltage set on the ADJ/EN pin over all specified operating conditions. 7.3.2 Undervoltage Lockout The device has an internally fixed undervoltage lockout threshold. Undervoltage lockout activates when the input voltage on VIN drops below the undervoltage lockout (UVLO) level (see the VUVLO(FALLING) parameter in the Electrical Characteristics table). This activation makes sure the regulator is not latched into an unknown state during a low input supply voltage. If the input voltage has a negative transient that drops below the UVLO threshold and recovers, the regulator shuts down and powers up in the standard power-up sequence when the input voltage recovers to the required level (see the VUVLO(RISING) parameter in the Electrical Characteristics table). 8 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS7B4255 TPS7B4255 www.ti.com SBVS441 – DECEMBER 2022 7.3.3 Thermal Protection Thermal protection disables the output when the junction temperature rises to approximately 175°C, which allows the device to cool. When the junction temperature cools to approximately 160°C, the output circuitry enables. Based on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit can cycle off and on until the excessive power dissipation condition is removed. This cycling limits the dissipation of the regulator, thus protecting the regulator from damage as a result of overheating. The internal protection circuitry of the TPS7B4255 is designed to protect against overload conditions. The circuitry is not intended to replace proper heat sinking. Continuously running the TPS7B4255 into thermal shutdown degrades device reliability. 7.3.4 Current Limit The device has an internal current limit circuit to protect the device during overcurrent or shorting conditions. The current limit circuit, as shown in Figure 7-2, is a brick-wall scheme. When the device is in current limit, the device sources ICL and the output voltage is not regulated. In this scenario, the output voltage depends on the load impedance. During a current limit event, the potential for high power dissipation exists because of the elevated current level and the increased input-to-output differential voltage (VIN – VOUT). If the device heats enough, the device can enter thermal shutdown. If the current-limit condition is not removed when the device turns back on after cooling, the device can enter thermal shutdown again and continue this cycle until the current limit condition is removed. The device survives this fault, but repeatedly operating in this mode degrades long-term reliability. VOUT Brickwall VOUT(NOM) IOUT 0V IRATED 0 mA ICL Figure 7-2. Current Limit: Brick-Wall Scheme Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS7B4255 9 TPS7B4255 www.ti.com SBVS441 – DECEMBER 2022 7.3.5 VOUT Short to Battery When the output is shorted to the supply (as shown in Figure 7-3), the TPS7B4255 survives and no damage occurs to the device. As shown in Figure 7-4, a short to the supply can also occur when the device is powered by an isolated supply at a lower voltage. In this example, the TPS7B4255 supply input voltage is set at 7 V when a short to the main supply (14 V typical) occurs on VOUT, which typically runs at 5 V. The device survives without damage, and continuous reverse current that flows out through VIN is less than 5 μA. Main System Supply 14 V (typical) Switch Switch VSYS Main System Supply 14 V (typical) IN TPS7B4255 OUT Isolated Supply Vreg VSYS 1 µF IN TPS7B4255 OUT 1 µF ADJ/EN Vreg 7-V VIN 2.2 µF 2.2 µF GND 5-V Vref ADJ/EN GND 5-V Vref Figure 7-3. Output Voltage Short to Supply Figure 7-4. Output Voltage Higher Than the Input 7.3.6 Tracking Regulator With an Enable Circuit Pulling the reference voltage below 0.7 V disables the device, and the device enters a sleep state where the device draws 3 μA (max) from the power supply. In a typical application, the reference voltage is generally sourced from another LDO voltage rail. A scenario where the device must be disabled without a shutdown of the reference voltage can occur; the device can be configured as shown in Figure 7-5 in this case. The TPS7B84-Q1 is a 150-mA LDO with ultra-low quiescent current that is used as a reference voltage to the TPS7B4255 and also as a power supply to the ADC. The operational status of the device is controlled by a microcontroller (MCU) input or output. IN OUT Sensor OUT IN Vsys ADC 10 µF 2.2 µF TPS7B4255 22 µF TPS7B84-Q1 10 µF 47k GND GND ADJ/EN EN 100k MCU I/O 47k Figure 7-5. Tracking an LDO With an Enable Circuit 10 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS7B4255 TPS7B4255 www.ti.com SBVS441 – DECEMBER 2022 7.4 Device Functional Modes The device operates with input voltages above 3 V to ensure proper operation. The device turns on when VIN is greater than VUVLO(RISING) and VADJ/EN is greater than VIH, and operates correctly as long as the input voltage stays above 3 V. 7.4.1 Operation With VIN < 3 V For voltages below 3 V and above VUVLO(FALLING), the LDO continues to operate but certain circuits can possibly not have the proper headroom to operate within specification. When the input voltage drops below VUVLO(FALLING) the device shuts off again. 7.4.2 Operation With ADJ/EN Control The ADJ/EN pin operates as both the reference and the enable pin to the LDO. When the input voltage is greater than VUVLO(RISING) and VADJ/EN is greater than VIH, the LDO is enabled and functional. When in this mode, the LDO tracks the voltage at the ADJ/EN pin because this pin functions as the reference to the control loop in the error amplifier. When VIN is greater than VUVLO(RISING) and VADJ/EN is lower than VIL, the LDO is disabled and is in a lower power mode. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS7B4255 11 TPS7B4255 www.ti.com SBVS441 – DECEMBER 2022 8 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 8.1 Application Information Depending on the end-application, different values of external components can be used. An application can require a larger output capacitor during fast load steps to prevent a reset from occurring. Use a low ESR ceramic capacitor with a dielectric of type X5R or X7R for better load transient response. 8.1.1 Dropout Voltage Dropout voltage (VDO) is defined as the input voltage minus the output voltage (VIN – VOUT) when the pass transistor is fully on. This condition arises when the input voltage falls to the point where the error amplifier must drive the pass device all the way to the rail and has no remaining headroom for the control loop to operate. The pass transistor is in the ohmic or triode region of operation, and acts as a switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than the nominal output regulation, then the output voltage follows, minus the dropout voltage (VDO). In dropout mode, the output is no longer regulated, and transient performance is severely degraded. The device loses PSRR, and load transients can cause large output voltage deviation. For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (RDS(ON)) of the pass transistor. Therefore, if the linear regulator operates at less than the rated output current (IRATED, see the Recommended Operating Conditions table), the dropout voltage for that current scales accordingly. The following equation calculates the RDS(ON) of the device. V RDS(ON)= I DO (1) RATED 8.1.2 Reverse Current The TPS7B4255 incorporates reverse current protection that prevents damage from a reverse polarity (that is, when VOUT is higher than VIN). During a reverse polarity event, where the VIN and VOUT absolute maximum ratings are not violated and VOUT – VIN is less than 40 V, no damage occurs and less than 5 μA flows out of VIN. The reverse current comparator typically responds to a reverse voltage condition and limits the reverse current in 1 μs. 8.1.3 Signal-Buffering LDO The TPS7B4255 can be used as a signal buffer up to frequencies of 1 kHz. The output tracks the signal in the ADJ/EN pin if VADJ/EN(min) is greater than VIH. A phase change begins at approximately 2 kHz, causing distortion in the output signal. At frequencies higher than 2 kHz, the signal gets attenuated and distorted further. Low-dropout regulators (LDOs) cannot sink current into the output, so for the signal-buffering circuit to operate correctly, the device must be loaded. The buffering LDO is limited by the current capability of the device, so use the minimum output capacitor (1 μF) to avoid high AC current. Figure 8-1 and Figure 8-2 depict the gain and phase, respectively, for the buffering LDO with resistive loads of 62 Ω, 100 Ω, and 330 Ω, and COUT = 1 μF. 12 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS7B4255 TPS7B4255 10 9 8 7 6 5 4 3 2 1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 10 SBVS441 – DECEMBER 2022 10 0 -10 -20 -30 -40 Phase () Gain (dB) www.ti.com -50 -60 -70 -80 -90 RLoad 62 100 330 -100 -110 100 1000 10000 100000 RLoad 62 100 330 -120 10 100 1000 Frequency (Hz) 10000 100000 Frequency (Hz) Figure 8-1. VADJ/EN Gain vs Frequency Figure 8-2. VADJ/EN Phase vs Frequency 8.2 Typical Application Figure 8-3 shows a typical application circuit for the TPS7B4255. IN Vsupply TPS7B4255 OUT Vreg 2.2 µF 1 µF Vref Optional ADJ/EN Vref GND 0.1 µF Figure 8-3. Typical Application Schematic 8.2.1 Design Requirements Use the parameters listed in Table 8-1 for this design example. Table 8-1. Design Parameters DESIGN PARAMETER EXAMPLE VALUES Input voltage 3 V to 40 V ADJ/EN reference voltage 2 V to 30 V Output voltage 2 V to 30 V Output current rating 70 mA Output capacitor range 1 µF to 200 µF Output capacitor ESR range 1 mΩ to 3 Ω Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS7B4255 13 TPS7B4255 www.ti.com SBVS441 – DECEMBER 2022 8.2.2 Detailed Design Procedure 8.2.2.1 Input and Output Capacitor Selection The TPS7B4255 requires an output capacitor of at least 1 µF (500 nF or larger capacitance) for stability and an equivalent series resistance (ESR) between 0.001 Ω and 3 Ω. Without the output capacitor, the regulator oscillates. For best transient performance, use X5R- and X7R-type ceramic capacitors because these capacitors have minimal variation in value and ESR over temperature. When choosing a capacitor for a specific application, be mindful of the DC bias characteristics for the capacitor. Higher output voltages cause a significant derating of the capacitor. For best performance, the maximum recommended output capacitor is 200 µF. Although an input capacitor is not required for stability, good analog design practice is to connect a capacitor from IN to GND, connected close to the device pins. Some input supplies have a high impedance; thus, placing the input capacitor on the input supply helps reduce the input impedance. This capacitor counteracts reactive input sources and improves transient response, input ripple, and PSRR. If the input supply has a high impedance over a large range of frequencies, several input capacitors can be used in parallel to lower the impedance over frequency. Use a higher-value capacitor if large, fast rise-time load transients are anticipated, or if the device is located several inches from the input power source. 8.2.3 Application Curves 14 14 12 12 10 → 6 4 VOUT 2 160 0 VIN 8 6 VOUT 4 VADJ/EN Right Scale → 160 2 0 IIN IIN -2  Left Scale 0 Current (mA) VADJ/EN Right scale 80 10 IIN VADJ/EN VOUT VIN 8 Voltage (V) VIN Voltage (V) Current (mA) IIN VADJ/EN VOUT VIN 80 0 -80 -2  Left Scale -80 50 100 150 200 250 300 350 400 450 500 0 200 400 600 800 Time (s) VIN = 12 V, VADJ/EN = 5 V, VADJ/EN slew rate = 1 V/μs, CIN = COUT = 1 μF, RLOAD = 470 Ω 1200 1400 1600 1800 2000 VIN = 12 V, VADJ/EN = 5 V, VADJ/EN slew rate = 1 V/μs, CIN = COUT = 1 μF, RLOAD = 470 Ω Figure 8-4. Power-Up Figure 8-5. Power-Down 100 5.4 90 Right Scale VIN VOUT 80 VIN (V) 1000 Time (s) → 5.2 5 70 4.8 60 4.6 50 4.4 40 4.2 30 4 20 3.8 10 3.6 0 0 50 100 150 200 250 300 Time (s) 350 400 450 VOUT (V) 0 3.4 500 COUT = 1 μF, VADJ/EN = 5 V, IOUT = 70 mA, VIN slew rate = 1 V/μs Figure 8-6. Dropout Exit Recovery 14 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS7B4255 TPS7B4255 www.ti.com SBVS441 – DECEMBER 2022 8.3 Power Supply Recommendations The device is designed to operate from an input voltage supply range from 3 V to 40 V. If the input supply is located more than a few inches from the TPS7B4255, add an electrolytic capacitor with a value of 10 µF and a ceramic bypass capacitor at the input. 8.4 Layout 8.4.1 Layout Guidelines For best overall performance, place all circuit components on the same side of the circuit board and as near as practical to the respective LDO pin connections. Place ground return connections to the input and output capacitor, and to the LDO ground pin as close as possible to each other, connected by a wide, component-side, copper surface. The use of vias and long traces to the input and output capacitors is strongly discouraged and negatively affects system performance. TI also recommends a ground reference plane either embedded in the PCB or located on the bottom side of the PCB opposite the components. This reference plane serves to assure accuracy of the output voltage, shield noise, and behaves similarly to a thermal plane to spread (or sink) heat from the LDO device when connected to the thermal pad. In most applications, this ground plane is necessary to meet thermal requirements. 8.4.1.1 Package Mounting Solder-pad footprint recommendations for the TPS7B4255 are available at the end of this document and at www.ti.com. 8.4.1.2 Board Layout Recommendations to Improve PSRR and Noise Performance To improve AC performance (such as PSRR, output noise, and transient response), design the board with separate ground planes for VIN and VOUT, with each ground plane connected only at the GND pin of the device. In addition, the ground connection for the output capacitor must connect directly to the GND pin of the device. Equivalent series inductance (ESL) and ESR must be minimized in order to maximize performance and ensure stability. Every capacitor must be placed as close as possible to the device and on the same side of the printed circuit board (PCB) as the regulator. Do not place any of the capacitors on the opposite side of the PCB from where the regulator is installed. Using vias and long traces is strongly discouraged because of the negative impact on system performance. Vias and long traces can also cause instability. If possible, and to make sure that the maximum performance is as denoted in this product data sheet, use the same layout pattern used for the TPS7B4255 evaluation board, available at www.ti.com. 8.4.1.3 Power Dissipation and Thermal Considerations Equation 2 calculates the device power dissipation. PD = IOUT × (VIN – VOUT) + IQ × VIN (2) where: • • • • • PD = Continuous power dissipation IOUT = Output current VIN = Input voltage VOUT = Output voltage IQ = Quiescent current Because IQ is much less than IOUT, the term IQ × VIN in Equation 2 can be ignored. Calculate the junction temperature (TJ) with Equation 3 for a device under operation at a given ambient air temperature (TA). TJ = TA + (RθJA × PD) (3) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS7B4255 15 TPS7B4255 www.ti.com SBVS441 – DECEMBER 2022 where: • RθJA = Junction-to-junction-ambient air thermal impedance Equation 4 calculates a rise in junction temperature because of power dissipation. ΔT = TJ – TA = (RθJA × PD) (4) The maximum ambient air temperature (TAMAX) at which the device can operate can be calculated with Equation 5 for a given maximum junction temperature (TJMAX). TAMAX = TJMAX – (RθJA × PD) (5) 8.4.1.4 Thermal Performance Versus Copper Area The most used thermal resistance parameter RθJA is highly dependent on the heat-spreading capability built into the particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the planes. The RθJA recorded in the Thermal Information table is determined by the JEDEC standard (Figure 8-7), PCB, and copper-spreading area, and is only used as a relative measure of package thermal performance. For a well-designed thermal layout, RθJA is actually the sum of the package junction-to-case (bottom) thermal resistance (RθJCbot) plus the thermal resistance contribution by the PCB copper. Wire Die Mold Compound Die Attach 2oz Signal Trace Internal Signal or power plane 1oz copper Lead Frame Internal GND plane 1oz copper Thermal Vias Bottom Relief 2oz copper Thermal Pad or Tab of the LDO Figure 8-7. JEDEC Standard 2s2p PCB Figure 8-8 and Figure 8-9 illustrate the functions of RθJA and ψJB versus copper area and thickness. These plots are generated with a 101.6-mm × 101.6-mm × 1.6-mm PCB of two and four layers. For the 4-layer board, inner planes use 1-oz copper thickness. Outer layers are simulated with both 1-oz and 2-oz copper thickness. A 4 x 5 (DBV package) array of thermal vias with a 300-µm drill diameter and 25-µm copper plating is located as close as practical to the GND pin of the device. The thermal vias connect the top layer, the bottom layer and, in the case of the 4-layer board, the first inner GND plane. Each of the layers has a copper plane of equal area. As illustrated in Figure 8-9, ψJB increases with increasing connecting copper area. The reason for this increase is that the board temperature is measured at the copper near the GND pin, and because the GND pin is fused to the die pad, more heat escapes through the GND pin when more copper is connected to the pad, and thus 16 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS7B4255 TPS7B4255 www.ti.com SBVS441 – DECEMBER 2022 the temperature at this point is higher. Consequently the ψJB increases. This increase does not imply that heat sinking for the device is reduced when more connecting copper is added. Increasing connecting copper area always increases board-level heat sinking for the device. Furthermore, the boards used for Figure 8-9 have vias connecting to internal copper planes. Therefore, ψJB is much higher than what is specified in the Thermal Information table, which uses the high-K board layout specified in JESD51-7 that has no thermal vias. 90 4 4 2 2 Thermal Resistance - JB (C/W) 89 88 Layer Layer Layer Layer PCB, PCB, PCB, PCB, 1 2 1 2 oz oz oz oz copper copper copper copper 87 86 85 84 83 82 81 80 0 Figure 8-8. RθJA vs Copper Area (DBV Package) 10 20 30 40 50 60 Cu Area Per Layer (cm2) 70 80 90 100 Figure 8-9. ψJB vs Copper Area (DBV Package) 8.4.2 Layout Example ADJ/EN 1 NC 5 GND 2 3 4 IN OUT Circles denote PCB via connections Figure 8-10. DBV Package Layout Example Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS7B4255 17 TPS7B4255 www.ti.com SBVS441 – DECEMBER 2022 9 Device and Documentation Support 9.1 Device Support 9.1.1 Device Nomenclature Table 9-1. Device Nomenclature(1) PRODUCT TPS7B4255yyyR (1) VOUT yyy is the package designator. R is the packaging quantity. For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the device product folder on www.ti.com. 9.1.2 Development Support 9.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 9.3 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 9.4 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 9.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 9.6 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 10 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 18 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS7B4255 PACKAGE OPTION ADDENDUM www.ti.com 25-Oct-2023 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) TPS7B4255DBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 2W4F (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of