TPS3307-18MDREPG4

  
 
       SGLS140A − NOVEMBER 2002 − REVISED AUGUST 2005 D Controlled Baseline D D D D D D Triple Supervisory Circuits for DSP and − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of −55°C to 125°C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product Change Notification Qualification Pedigree† ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) D D D D D D Processor-Based Systems Power-On Reset Generator With Fixed Delay Time of 200 ms, No External Capacitor Needed Temperature-Compensated Voltage Reference Maximum Supply Current of 40 µA Supply Voltage Range . . . 2 V to 6 V Defined RESET Output from VDD ≥ 1.1 V SO-8 and MSOP-8 Packages D or DGN PACKAGE (TOP VIEW) † Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. SENSE1 SENSE2 SENSE3 GND 1 8 2 7 3 6 4 5 VDD MR RESET RESET typical applications Figure 1 lists some of the typical applications for the TPS3307 family, and a schematic diagram for a processor-based system application. This application uses Texas Instruments part numbers TPS3307-18 and SMJ320C6201B. 2.5 V 3.3 V 1.8 V VDD 100 nF SENSE 1 SENSE 2 470 kΩ SMJ320C6201B RESET RESET TPS3307-18 GND SENSE 3 620 kΩ VDD • w w w Military applications using DSPs, Microcontrollers or Microprocessors Industrial Equipment Programmable Controls Military Systems GND Figure 1. Applications Using the TPS3307-18 description The TPS3307-xx family is a series of micropower supply voltage supervisors designed for circuit initialization primarily in DSP and processor-based systems which require more than one supply voltage. The TPS3307-18 and TPS3307-33 are designed for monitoring three independent supply voltages: 3.3 V/1.8 V/adj and 5V/3.3V/adj, respectively. The adjustable SENSE input allows the monitoring of any supply voltage >1.25 V. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2005, Texas Instruments Incorporated 
 
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       SGLS140A − NOVEMBER 2002 − REVISED AUGUST 2005 description (continued) The various supply voltage supervisors are designed to monitor the nominal supply voltage as shown in the following supply voltage monitoring table. SUPPLY VOLTAGE MONITORING NOMINAL SUPERVISED VOLTAGE DEVICE THRESHOLD VOLTAGE (TYP) SENSE1 SENSE2 SENSE3 SENSE1 SENSE2 3.3 V 1.8 V User defined 2.93 V 1.68 V TPS3307-18 SENSE3 1.25 V† TPS3307-33 5V 3.3 V User defined 4.55 V 2.93 V 1.25 V† † The actual sense voltage has to be adjusted by an external resistor divider according to the application requirements. During power-on, RESET is asserted when the supply voltage VDD becomes higher than 1.1 V. Thereafter, the supply voltage supervisor monitors the SENSEn inputs and keeps RESET active as long as SENSEn remain below the threshold voltage VIT+. An internal timer delays the return of the RESET output to the inactive state (high) to ensure proper system reset. The delay time, tdtyp = 200 ms, starts after all SENSEn inputs have risen above the threshold voltage VIT+. When the voltage at any SENSE input drops below the threshold voltage VIT–, the RESET output becomes active (low) again. The TPS3307-xx family of devices incorporates a manual reset input, MR. A low level at MR causes RESET to become active. In addition to the active-low RESET output, the TPS3307-xx family includes an active-high RESET output. The devices are available in either 8-pin MSOP or a standard 8-pin SO packages and are characterized for operation over a temperature range of −55°C to 125°C. ORDERING INFORMATION PACKAGE‡ TA −55°C to 125°C ORDERABLE PART NUMBER TOP-SIDE MARKING Small Outline (D) Tape and Reel TPS3307-18MDREP 30718E PowerPad µ-Small Outline (DGN) Tape and Reel TPS3307-33MDGNREP BNP ‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION/TRUTH TABLES MR SENSE1 > VIT1 SENSE2 > VIT2 SENSE3 > VIT3 RESET RESET L X X X L H H 0 0 0 L H H 0 0 1 L H H 0 1 0 L H H 0 1 1 L H H 1 0 0 L H H 1 0 1 L H H 1 1 0 L H H 1 1 1 H L X = Don’t care 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
  
 
       SGLS140A − NOVEMBER 2002 − REVISED AUGUST 2005 functional block diagram VDD TPS3307 14 kΩ MR R1 + _ SENSE 1 R2 R3 SENSE 2 R4 + _ RESET RESET Logic + Timer RESET GND Reference Voltage of 1.25 V _ Oscillator + SENSE 3 timing diagram SENSEn V(nom) VIT− t MR 1 0 t RESET 1 t 0 td td td RESET Because of SENSE Below VIT RESET Because of MR RESET Because of SENSE Below VIT− RESET Because of SENSE Below VIT− POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 
  
 
       SGLS140A − NOVEMBER 2002 − REVISED AUGUST 2005 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V All other pins (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V Maximum low output current, IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA Maximum high output current, IOH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −5 mA Input clamp current, IIK (VI < 0 or VI > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Maximum junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Package thermal impedance, θJA (see Note 2) D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126°C/W DGN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58.4°C/W Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C Storage temperature range, Tstg (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C Soldering temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260_C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to GND. For reliable operation the device must not be operated at 7 V for more than t = 1000 h continuously. NOTE 2: The thermal impedance, θJA, for the D package is determined for JEDEC high-K PCB (JESD51-7). The thermal impedance value for the DGN package is determined for Texas Instruments recommended assembly for PowerPAD packages. See Texas Instruments technical briefs SLMA002 and SLMA004 for more information about utilizing the PowerPAD thermally enhanced package. Thermal impedance, θJA, values for the D and DGN packages using JEDEC low-K PCB (JESD51-3) are 215°C/W and 296°C/W, respectively. NOTE 3: Long-term, high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of overall device life. See http://www.ti.com/sc/ep for more information. recommended operating conditions at specified temperature range MIN MAX UNIT Supply voltage, VDD 2 6 V Input voltage at MR and SENSE3, VI 0 V Input voltage at SENSE1 and SENSE2, VI 0 VDD+0.3 (VDD+0.3)VIT/1.25 V High-level input voltage at MR, VIH 0.7xVDD Low-level input voltage at MR, VIL Input transition rise and fall rate at MR, ∆t/∆V Operating free-air temperature range, TA 4 −55 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 V V 0.3×VDD 50 V ns/V 125 °C 
  
 
       SGLS140A − NOVEMBER 2002 − REVISED AUGUST 2005 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL TEST CONDITIONS High-level output voltage Low-level output voltage Power-up reset voltage (see Note 4) Vhys Negative-going input threshold voltage (see Note 5) SENSE1, SENSE2 Hysteresis at VSENSEn input MR IH High-level input current IL Low-level input current IDD Ci Supply current TYP IOH = −20 µA IOH = −2 mA VDD– 0.2 V VDD– 0.4 V VDD = 6 V, VDD = 2 V to 6 V, IOH = −3 mA IOL = 20 µA VDD– 0.4 V VDD = 3.3 V, VDD = 6 V, IOL = 2 mA IOL = 3 mA VDD ≥ 1.1 V, IOL = 20 µA SENSE3 VIT− MIN VDD = 2 V to 6 V, VDD = 3.3 V, VDD = 2 V to 6 V MAX V 0.2 0.4 0.4 1.25 1.29 VSENSE = 1.8 V 1.6 1.68 1.73 VSENSE = 3.3 V 2.8 2.93 3.02 VSENSE = 5 V 4.4 4.55 4.67 VIT− = 1.25 V VIT− = 1.68 V 2 10 30 2 15 40 VIT− = 2.93 V VIT− = 4.55 V 3 30 60 3 40 80 −130 −180 5 8 6 9 −430 −600 MR = 0.7 × VDD, VDD = 6 V VSENSE1 = VDD = 6 V SENSE2 VSENSE2 = VDD = 6 V SENSE3 VSENSE3 = VDD MR MR = 0 V, SENSEn VSENSE1,2,3 = 0 V V 0.4 1.2 SENSE1 UNIT −1 VDD = 6 V −1 V V mV µA A 1 1 40 µA A µΑ Input capacitance VI = 0 V to VDD 10 pF NOTES: 4. The lowest supply voltage at which RESET becomes active. tr, VDD ≥ 15 µs/V 5. To ensure best stability of the threshold voltage, a bypass capacitor (ceramic 0.1 µF) should be placed close to the supply terminals. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 
  
 
       SGLS140A − NOVEMBER 2002 − REVISED AUGUST 2005 timing requirements at VDD = 2 V to 6 V, RL = 1 MΩ, CL = 50 pF, TA = 25°C PARAMETER tw Pulse width SENSEn MR TEST CONDITIONS VSENSEnL = VIT− −0.2 V, VIH = 0.7 × VDD, VSENSEnH = VIT+ + 0.2 V VIL = 0.3 × VDD MIN TYP MAX UNIT 6 µs 100 ns switching characteristics at VDD = 2 V to 6 V, RL = 1 MΩ, CL = 50 pF, TA = 25°C PARAMETER td Delay time tPHL Propagation (delay) time, high-to-low level output MR to RESET tPLH Propagation (delay) time, low-to-high level output MR to RESET tPHL Propagation (delay) time, high-to-low level output SENSEn to RESET tPLH Propagation (delay) time, low-to-high level output SENSEn to RESET 6 TEST CONDITIONS MIN TYP MAX UNIT VI(SENSEn) ≥ VIT+ + 0.2 V, MR ≥ 0.7 × VDD, See timing diagram 140 200 280 ms 200 600 ns 1 5 µss VI(SENSEn) ≥ VIT+ + 0.2 V, VIH = 0.7 × VDD, VIL = 0.3 × VDD VIH ≥ VIT+ + 0.2 V, VIL ≤ VIT− − 0.2 V, MR ≥ 0.7 × VDD POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
  
 
       SGLS140A − NOVEMBER 2002 − REVISED AUGUST 2005 SUPPLY CURRENT vs SUPPLY VOLTAGE NORMALIZED SENSE THRESHOLD VOLTAGE vs FREE-AIR TEMPERATURE AT VDD 18 1.005 VDD = 2 V MR = Open 1.004 16 14 1.003 12 I DD − Supply Current − µ A Normalized Input Threshold Voltage − VIT(TA), VIT(25°C ) TYPICAL CHARACTERISTICS 1.002 1.001 1 0.999 0.998 0.997 TPS3307−33 10 8 6 4 2 0 −2 −4 SENSEn = VDD MR = Open TA = 25°C −6 0.996 0.995 −40 −15 10 60 35 −8 −10 −0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 85 TA − Free-Air Temperature − °C VDD − Supply Voltage − V Figure 3 Figure 2 INPUT CURRENT vs INPUT VOLTAGE AT MR MINIMUM PULSE DURATION AT SENSE vs THRESHOLD OVERDRIVE 100 tw − Minimum Pulse Duration at Vsense − µ s 0 10 VDD = 6 V TA = 25°C I I − Input Current − µ A −100 −200 −300 −400 −500 −600 −700 −800 −900 −1 −0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 VDD = 6 V MR = Open 9 8 7 6 5 4 3 2 1 0 0 100 200 300 400 500 600 700 800 900 1000 VI − Input Voltage at MR − V SENSE − Threshold Overdrive − mV Figure 4 Figure 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 
  
 
       SGLS140A − NOVEMBER 2002 − REVISED AUGUST 2005 TYPICAL CHARACTERISTICS HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 2.5 6.5 VDD = 6 V MR = Open 6 VOH − High-Level Output Voltage − V VOH − High-Level Output Voltage − V VDD = 2 V MR = Open 2 1.5 −40°C 1 85°C 0.5 5.5 5 4.5 4 −40°C 3.5 3 85°C 2.5 2 1.5 1 0.5 0 0 0 −0.5 −1 −1.5 −2 −2.5 −3 −3.5 −4 −4.5 −5 −5.5 −6 0 −5 −10 −15 −20 −25 −30 −35 −40 −45 −50 IOH − High-Level Output Current − mA IOH − High-Level Output Current − mA Figure 6 Figure 7 LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 6.5 VDD = 2 V MR = Open 2 1.5 1 VDD = 6 V MR = Open 6 VOL − Low-Level Output Voltage − V VOL − Low-Level Output Voltage − V 2.5 85°C 0.5 −40°C 5.5 5 4.5 4 3.5 3 85°C 2.5 2 1.5 −40°C 1 0.5 0 0 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 IOL − Low-Level Output Current − mA 1 6 0 0 5 Figure 8 8 10 15 20 25 30 35 40 45 50 55 60 IOL − Low-Level Output Current − mA Figure 9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPS3307-18MDREP ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 30718E TPS3307-18MDREPG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 30718E TPS3307-33MDGNREP ACTIVE HVSSOP DGN 8 2500 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -55 to 125 BNP V62/03629-01XE ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 30718E V62/03629-02YE ACTIVE HVSSOP DGN 8 2500 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -55 to 125 BNP (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of