TPS5420-EP
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SLVS717 – DECEMBER 2006
2-A WIDE-INPUT-RANGE STEP-DOWN SWIFT™ CONVERTER
FEATURES
•
•
•
•
•
•
•
•
•
(1)
Controlled Baseline
– One Assembly/Test Site, One Fabrication
Site
Enhanced Diminishing Manufacturing Sources
(DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree (1)
Wide Input Voltage Range: 5.5 V to 35 V
Up to 2-A Continuous (3-A Peak) Output
Current
High Efficiency up to 95% Enabled by 110-mΩ
Integrated MOSFET Switch
Wide Output Voltage Range: Adjustable Down
to 1.22 V with 1.5% Initial Accuracy
Internal Compensation Minimizes External
Parts Count
Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
•
•
•
•
•
•
Fixed 500-kHz Switching Frequency for Small
Filter Size
Improved Line Regulation and Transient
Response by Input Voltage Feed Forward
System Protected by Overcurrent Limiting and
Thermal Shutdown
-55°C to 125°C Operating Junction
Temperature Range
Available in Small 8-Pin SOIC Package
For SWIFT™ Documentation, Application
Reports, and Design Software, See the TI
Website at www.ti.com/swift
APPLICATIONS
•
•
•
•
Consumer: Set-Top Boxes, DVDs, LCD
Displays
Industrial and Car Audio Power Supplies
Battery Chargers, High-Power LED Supplies
12-V/24-V Distributed Power Systems
DESCRIPTION/ORDERING INFORMATION
As a member of the SWIFT™ family of dc/dc regulators, the TPS5420 is a high-output-current PWM converter
that integrates a low-resistance high-side N-channel MOSFET. Included on the substrate with the listed features
is a high-performance voltage error amplifier that provides tight voltage regulation accuracy under transient
conditions, an undervoltage-lockout circuit to prevent start-up until the input voltage reaches 5.5 V, an internally
set slow-start circuit to limit inrush currents, and a voltage feed-forward circuit to improve the transient response.
Using the ENA pin, shutdown supply current is reduced to 18 µA, typically. Other features include an active high
enable, overcurrent protection, and thermal shutdown. To reduce design complexity and external component
count, the TPS5420 feedback loop is internally compensated.
The TPS5420 device is available in an easy to use 8-pin SOIC package. TI provides evaluation modules and the
SWIFT Designer Software tool to aid in quickly achieving high-performance power-supply designs to meet
aggressive equipment development cycles.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SWIFT is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated
TPS5420-EP
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SLVS717 – DECEMBER 2006
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
TJ
INPUT VOLTAGE
–55°C to 125°C
(1)
(2)
PACKAGE (1)
OUTPUT VOLTAGE
5.5 V to 35 V
Adjustable to 1.22 V
SOIC
PART NUMBER
(D) (2)
TPS5420MDREP
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
The D package is available taped and reeled. Add an R suffix to the device type (i.e., TPS5420DR).
SIMPLIFIED SCHEMATIC
Efficiency vs Output Current
VIN
100
VOUT
PH
VIN
95
TPS5420
90
BOOT
85
Efficiency − %
NC
NC
ENA VSENSE
VI = 12 V
80
75
70
65
GND
60
55
50
0
0.5
1
1.5
2
I − Output Current− A
O
2.5
3
Absolute Maximum Ratings (1) (2)
over operating free-air temperature range (unless otherwise noted)
VALUE
BOOT
–0.3 to 50
PH (steady-state)
VI
Input voltage range
–0.6 to 38 (3)
EN
–0.3 to 7
VSENSE
–0.3 to 3
BOOT-PH
10
PH (transient < 10 ns)
V
–1.2
IO
Source current
PH
Internally limited
Ilkg
Leakage current
PH
10
µA
TJ
Operating virtual junction temperature range
–55 to 150
°C
Tstg
Storage temperature range
–65 to 150
°C
(1)
(2)
(3)
2
UNIT
–0.3 to 38 (3)
VIN
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
Approaching the absolute maximum rating for the VIN pin may cause the voltage on the PH pin to exceed the absolute maximum rating.
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Dissipation Ratings
(1) (2)
THERMAL IMPEDANCE
JUNCTION-TO-AMBIENT
PACKAGE
8-pin D
(1)
(2)
(3)
(3)
75°C/W
Maximum power dissipation may be limited by overcurrent protection.
Power rating at a specific ambient temperature TA should be determined with a junction temperature of 125°C. This is the point where
distortion starts to substantially increase. Thermal management of the final PCB should strive to keep the junction temperature at or
below 125°C for best performance and long-term reliability. See Thermal Calculations in applications section of this data sheet for more
information.
Test board conditions:
a. 3 in × 3 in, two layers, thickness: 0.062 in
b. 2-oz copper traces located on the top and bottom of the PCB
Recommended Operating Conditions
MIN
MAX
VI
Input voltage range, VIN
5.5
35
UNIT
V
TJ
Operating junction temperature
–55
125
°C
Electrical Characteristics
TJ = –55°C to 125°C, VIN = 5.5 V to 35 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Supply Voltage (VIN Pin)
IQ
3
4.4
mA
18
50
µA
Start threshold voltage, UVLO
5.3
5.5
Hysteresis voltage, UVLO
330
Quiescent current
VSENSE = 2 V, Not switching, PH pin open
Shutdown, ENA = 0 V
Undervoltage Lockout (UVLO)
V
mV
Voltage Reference
Voltage reference accuracy
TJ = 25°C
1.202
1.221
1.239
IO = 0 A – 2 A
1.196
1.221
1.245
TJ = 25°C
400
500
600
kHz
TJ = -55°C to 125°C
375
600
kHz
200
ns
1.3
V
V
Oscillator
Internally set free-running frequency
Minimum controllable on time
150
Maximum duty cycle
87%
89%
Enable (ENA Pin)
Start threshold voltage, ENA
Stop threshold voltage, ENA
0.5
Hysteresis voltage, ENA
V
450
Internal slow-start time (0 ~ 100%)
6.6
mV
8
10.6
ms
Current Limit
Current limit
Current limit hiccup time
3
4
5.2
A
13
16
22
ms
135
162
°C
14
°C
Thermal Shutdown
Thermal shutdown trip point
Thermal shutdown hysteresis
Output MOSFET
rDS(on)
High-side power MOSFET switch
VIN = 5.5 V
150
VIN = 10 V – 35 V
110
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mΩ
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PIN ASSIGNMENTS
D PACKAGE
(TOP VIEW)
BOOT
1
8
PH
NC
2
7
VIN
NC
3
6
GND
VSENSE
4
5
ENA
TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
BOOT
1
NC
4
2, 3
DESCRIPTION
Boost capacitor for the high-side FET gate driver. Connect 0.01-µF low-ESR capacitor from BOOT pin to PH pin.
Not connected internally
VSENSE
4
Feedback voltage for the regulator. Connect to output voltage divider.
ENA
5
On/off control. Below 0.5 V, the device stops switching. Float the pin to enable.
GND
6
Ground
VIN
7
Input supply voltage. Bypass VIN pin to GND pin close to device package with a high-quality, low-ESR ceramic
capacitor.
PH
8
Source of the high-side power MOSFET. Connected to external inductor and diode.
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TYPICAL CHARACTERISTICS
OSCILLATOR FREQUENCY
vs
JUNCTION TEMPERATURE
3.5
f − Oscillator Frequency − kHz
520
510
500
490
480
470
460
-50
180
VI = 12 V
170
Minimum Controllable On Time − ns
IQ − Operating Quiescent Current − mA
530
3.25
3
2.75
2.5
-25
0
50
25
75
100
-50
125
-25
0
50
25
75
100
160
150
140
130
120
-50
125
-25
o
TJ − Junction Temperature − oC
TJ − Junction Temperature − C
0
25
50
75
100
Figure 2.
Figure 3.
VOLTAGE REFERENCE
vs
JUNCTION TEMPERATURE
ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
INTERNAL SLOW START TIME
vs
JUNCTION TEMPERATURE
180
9
VI = 12 V
1.22
1.215
tSS − Internal Slow Start Time − ms
rDS(on) − On-State Resistance − mW
170
1.225
125
o
TJ − Junction Temperature − C
Figure 1.
1.23
160
150
140
130
120
110
100
8.5
8
7.5
90
1.21
80
-25
0
50
25
75
100
125
-50
-25
0
50
25
100
7
125
-25
TJ − Junction Temperature − oC
Figure 4.
0
25
50
75
100
125
o
TJ − Junction Temperature − C
Figure 5.
Figure 6.
MINIMUM CONTROLLABLE
DUTY RATIO
vs
JUNCTION TEMPERATURE
SHUTDOWN QUIESCENT CURRENT
vs
INPUT VOLTAGE
25
75
-50
o
TJ − Junction Temperature − C
8
ENA = 0 V
o
TJ = 125 C
20
Minimum Duty Ratio − %
-50
ISD − Shutdown Current − mA
Vref − Voltage Reference − V
MINIMUM CONTROLLABLE
ON TIME
vs
JUNCTION TEMPERATURE
OPERATING QUIESCENT CURRENT
vs
JUNCTION TEMPERATURE
TJ = 27oC
15
10
7.5
7.5
7.25
TJ = -40oC
5
7
0
5
10
15
20
25
VI − Input Voltage − V
30
35
40
-50
-25
0
25
50
75
100
125
TJ − Junction Temperature − oC
Figure 7.
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APPLICATION INFORMATION
FUNCTIONAL BLOCK DIAGRAM
VIN
VIN
1.221 V Bandgap
Reference
UVLO
VREF
SHDN
Slow Start
Boot
Regulator
BOOT
HICCUP
5 µA
ENA
ENABLE
SHDN
SHDN
VSENSE
Z1
Thermal
Protection
NC
SHDN
VIN
Ramp
Generator
NC
GND
Z2
Feed Forward
Gain = 25
SHDN
SHDN
Error
Amplifier
SHDN
PWM
Comparator
HICCUP
Overcurrent
Protection
Oscillator
SHDN
Gate Drive
Control
Gate
Driver
SHDN
BOOT
PH
VOUT
DETAILED DESCRIPTION
Oscillator Frequency
The internal free-running oscillator sets the PWM switching frequency at 500 kHz. The 500-kHz switching
frequency allows less output inductance for the same output ripple requirement, resulting in a smaller output
inductor.
Voltage Reference
The voltage reference system produces a precision reference signal by scaling the output of a
temperature-stable bandgap circuit. The bandgap and scaling circuits are trimmed during production testing to
an output of 1.221 V at room temperature.
Enable (ENA) and Internal Slow Start
The ENA pin provides electrical on/off control of the regulator. Once the ENA pin voltage exceeds the threshold
voltage, the regulator starts operation and the internal slow start begins to ramp. If the ENA pin voltage is pulled
below the threshold voltage the regulator stops switching and the internal slow start resets. Connecting the pin
to ground or to any voltage less than 0.5 V disables the regulator and activates the shutdown mode. The
quiescent current of the TPS5420 in shutdown mode is typically 18 µA.
The ENA pin has an internal pullup current source, allowing the user to float the ENA pin. If an application
requires controlling the ENA pin, use open-drain or open-collector output logic to interface with the pin. To limit
the start-up inrush current, an internal slow start circuit is used to ramp up the reference voltage from 0 V to its
final value, linearly. The internal slow start time is 8 ms, typically.
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APPLICATION INFORMATION (continued)
Undervoltage Lockout (UVLO)
The TPS5420 incorporates an undervoltage lockout circuit to keep the device disabled when VIN (the input
voltage) is below the UVLO start voltage threshold. During power up, internal circuits are held inactive until VIN
exceeds the UVLO start threshold voltage. Once the UVLO start threshold voltage is reached, device start-up
begins. The device operates until VIN falls below the UVLO stop threshold voltage. The typical hysteresis in the
UVLO comparator is 330 mV.
Boost Capacitor (BOOT)
Connect a 0.01-µF low-ESR ceramic capacitor between the BOOT pin and PH pin. This capacitor provides the
gate drive voltage for the high-side MOSFET. X7R or X5R grade dielectrics are recommended due to their
stable values over temperature.
Output Feedback (VSENSE)
The output voltage of the regulator is set by feeding back the center point voltage of an external resistor divider
network to the VSENSE pin. In steady-state operation, the VSENSE pin voltage should be equal to the voltage
reference 1.221 V.
Internal Compensation
The TPS5420 implements internal compensation to simplify the regulator design. Since the TPS5420 uses
voltage mode control, a type 3 compensation network has been designed on chip to provide a high crossover
frequency and a high phase margin for good stability. See the Internal Compensation Network in the
applications section for more details.
Voltage Feed Forward
The internal voltage feed forward provides a constant dc power stage gain, despite any variations with the input
voltage. This greatly simplifies the stability analysis and improves the transient response. Voltage feed forward
varies the peak ramp voltage inversely with the input voltage so that the modulator and power stage gain are
constant at the feed forward gain:
VIN
Feed Forward Gain =
Ramppk-pk
(1)
The typical feed-forward gain of TPS5420 is 25.
Pulse-Width-Modulation (PWM) Control
The regulator employs a fixed-frequency pulse-width-modulator (PWM) control method. First, the feedback
voltage (VSENSE pin voltage) is compared to the constant voltage reference by the high-gain error amplifier and
compensation network to produce a error voltage. Then, the error voltage is compared to the ramp voltage by
the PWM comparator. In this way, the error voltage magnitude is converted to a pulse width that is the duty
cycle. Finally, the PWM output is fed into the gate drive circuit to control the on time of the high-side MOSFET.
Overcurrent Protection
Overcurrent protection is implemented by sensing the drain-to-source voltage across the high-side MOSFET.
The drain to source voltage is then compared to a voltage level representing the overcurrent threshold limit. If
the drain-to-source voltage exceeds the overcurrent threshold limit, the overcurrent indicator is set true. The
system ignores the overcurrent indicator for the leading-edge blanking time at the beginning of each cycle to
avoid any turn-on noise glitches.
Once overcurrent indicator is set true, overcurrent protection is triggered. The high-side MOSFET is turned off
for the rest of the cycle after a propagation delay. The overcurrent protection scheme is called cycle-by-cycle
current limiting.
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APPLICATION INFORMATION (continued)
If the sensed current continues increasing, even with the cycle-by-cycle current limiting that may happen during
short circuit or under other circumstances, the hiccup-mode overcurrent protection is triggered instead of the
cycle-by-cycle current limiting. During the hiccup-mode overcurrent protection, the voltage reference is grounded
and the high-side MOSFET is turned off for the hiccup time. Once the hiccup time is complete, the regulator
restarts.
Thermal Shutdown
The TPS5420 protects itself from overheating with an internal thermal shutdown circuit. If the junction
temperature exceeds the thermal shutdown trip point, the voltage reference is grounded and the high-side
MOSFET is turned off. The part is restarted under control of the slow start circuit automatically when the junction
temperature drops 14°C below the thermal shutdown trip point.
PCB Layout
Connect a low ESR ceramic bypass capacitor to the VIN pin. Care should be taken to minimize the loop area
formed by the bypass capacitor connections, the VIN pin, and the TPS5420 ground pin. The best way to do this
is to extend the top-side ground area from under the device adjacent to the VIN trace, and place the bypass
capacitor as close as possible to the VIN pin. The minimum recommended bypass capacitance is 10-µF ceramic
with a X5R or X7R dielectric.
There should be a ground area on the top layer directly underneath the IC to connect the GND pin of the device
and the anode of the catch diode. The GND pin should be tied to the PCB ground by connecting it to the ground
area under the device as shown in Figure 9.
The PH pin should be routed to the output inductor, catch diode, and boot capacitor. Since the PH connection is
the switching node, the inductor should be located close to the PH pin, and the area of the PCB conductor
minimized to prevent excessive capacitive coupling. The catch diode should also be placed close to the device
to minimize the output current loop area. Connect the boot capacitor between the phase node and the BOOT pin
as shown. Keep the boot capacitor close to the IC and minimize the conductor trace lengths. The component
placements and connections shown work well, but other connection routings may also be effective.
Connect the output filter capacitor(s) as shown between the VOUT trace and GND. It is important to keep the
loop formed by the PH pin, Lout, Cout, and GND as small as is practical.
Connect the VOUT trace to the VSENSE pin using the resistor divider network to set the output voltage. Do not
route this trace too close to the PH trace. Due to the size of the IC package and the device pinout, the trace may
need to be routed under the output capacitor. The routing may be done on an alternate layer if a trace under the
output capacitor is not desired.
The grounding scheme shown is used via a connection to a different layer to route to the ENA pin.
8
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APPLICATION INFORMATION (continued)
PH
BOOT
CAPACITOR
OUTPUT
INDUCTOR
RESISTOR
DIVIDER
VOUT
BOOT
PH
NC
VIN
NC
GND
VSENSE
ENA
OUTPUT
FILTER
CAPACITOR
Route feedback
trace under the output
filter capacitor or on
the other layer.
CATCH
DIODE
INPUT
INPUT
BULK
BYPASS
CAPACITOR FILTER
Vin
TOPSIDE GROUND AREA
VIA to Ground Plane
Signal VIA
Figure 9. Design Layout
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0.050
APPLICATION INFORMATION (continued)
0.026
0.220
0.080
All dimensions in inches
Figure 10. TPS5420 Land Pattern
Application Circuits
Figure 11 shows the schematic for a typical TPS5420 application. The TPS5420 can provide up to 2-A output
current at a nominal output voltage of 5 V.
U1
TPS5420D
10 V - 35 V
7
VIN
ENA
C1
4.7 mF
C4
4.7 mF
VIN
BOOT
5 ENA
2 NC
1
C2
0.01 mF
TP5
PH 8
3 NC
6 GND
VSNS 4
L1
33 mH
5V
VOUT
D1
B340A
+
C3
100 mF
(See Note A)
R1
10 kW
R2
3.24 kW
A.
C3 = Tantalum AVX TPSD107M010R0080
Figure 11. Application Circuit, 10-V – 35-V Input to 5-V Output
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APPLICATION INFORMATION (continued)
Design Procedure
The following design procedure can be used to select component values for the TPS5420. Alternately, the
SWIFT Designer Software may be used to generate a complete design. The SWIFT Designer Software uses an
iterative design procedure and accesses a comprehensive database of components when generating a design.
This section presents a simplified discussion of the design process.
To
•
•
•
•
•
•
begin the design process, a few parameters must be determined. The designer must know the following:
Input voltage range
Output voltage
Input ripple voltage
Output ripple voltage
Output current rating
Operating frequency
Design Parameters
For this design example, use the following as the input parameters:
(1)
DESIGN PARAMETER (1)
EXAMPLE VALUE
Input voltage range
10 V to 35 V
Output voltage
5V
Input ripple voltage
300 mV
Output ripple voltage
30 mV
Output current rating
2A
Operating frequency
500 kHz
As an additional constraint, the design is set up to be small size and low component height.
Switching Frequency
The switching frequency for the TPS5420 is internally set to 500 kHz. It is not possible to adjust the switching
frequency.
Input Capacitors
The TPS5420 requires an input decoupling capacitor and, depending on the application, a bulk input capacitor.
The recommended value for the decoupling capacitor is 10 µF. A high-quality ceramic type X5R or X7R is
required. For some applications, a smaller value decoupling capacitor may be used, if the input voltage and
current ripple ratings are not exceeded. The voltage rating must be greater than the maximum input voltage,
including ripple. For this design, two 4.7-µF capacitors, C1 and C4, are used to allow for smaller 1812 case size
to be used while maintaining a 50-V rating.
This input ripple voltage can be approximated by Equation 2 :
IOUT(MAX) x 0.25
+ IOUT(MAX) x ESRMAX
DVIN =
CBULK x ƒSW
(
)
(2)
Where:
IOUT(MAX) = Maximum load current
fSW = Switching frequency
CI = Input capacitor value
ESRMAX = Maximum series resistance of the input capacitor
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The maximum RMS ripple current also needs to be checked. For worst-case conditions, this is approximated by
Equation 3:
I
OUT(MAX)
I
+
CIN
2
(3)
In this example, the calculated input ripple voltage is 118 mV and the RMS ripple current is 1.0 A. The maximum
voltage across the input capacitors would be VIN max plus delta VIN/2. The chosen input decoupling capacitors
are rated for 50 V, and the ripple current capacity for each is 3 A at 500 kHz, providing ample margin. The actual
measured input ripple voltage may be larger than the calculated value, due to the output impedance of the input
voltage source and parasitics associated with the layout.
CAUTION:
The maximum ratings for voltage and current are not to be exceeded under any
circumstance.
Additionally, some bulk capacitance may be needed, especially if the TPS5420 circuit is not located within
approximately 2 in from the input voltage source. The value for this capacitor is not critical, but it should be rated
to handle the maximum input voltage, including ripple voltage, and should filter the output so that input ripple
voltage is acceptable.
Output Filter Components
Two components need to be selected for the output filter, L1 and C2. Since the TPS5420 is an internally
compensated device, a limited range of filter component types and values can be supported.
Inductor Selection
To calculate the minimum value of the output inductor, use Equation 4:
LMIN =
VOUT ´
(VIN(MAX)
)
- VOUT
VIN(max) ´ KIND ´ IOUT ´ FSW ´ 0.8
(4)
KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current.
Three things need to be considered when determining the amount of ripple current in the inductor: the
peak-to-peak ripple current affects the output ripple voltage amplitude, the ripple current affects the peak switch
current, and the amount of ripple current determines at what point the circuit becomes discontinuous. For
designs using the TPS5420, KIND of 0.2 to 0.3 yields good results. Low output ripple voltages are obtained when
paired with the proper output capacitor, the peak switch current is below the current limit set point, and low load
currents can be sourced before discontinuous operation.
For this design example, use KIND = 0.2, and the minimum inductor value is 31 µH. The next highest standard
value used in this design is 33 µH.
For the output filter inductor, it is important that the RMS current and saturation current ratings not be exceeded.
The RMS inductor current can be found from Equation 5:
I
L(RMS)
+
Ǹ
1
I2
)
OUT(MAX) 12
ǒ
V
V
OUT
ǒVIN(MAX) * VOUTǓ
L
IN(MAX)
OUT
F
SW
0.8
Ǔ
2
(5)
and the peak inductor current can be determined using Equation 6:
(
)
VOUT ´ VIN(MAX) - VOUT
IL(PK) = IOUT(MAX) +
1.6 ´ VIN(MAX) ´ LOUT ´ FSW
(6)
For this design, the RMS inductor current is 2.002 A, and the peak inductor current is 2.16 A. The chosen
inductor is a Coilcraft MSS1260-333 type. The nominal inductance is 33 µH. It has a saturation current rating of
2.2 A and an RMS current rating of 2.7 A, which meets the requirements. Inductor values for use with the
TPS5420 are in the range of 10 µH to 100 µH.
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Capacitor Selection
The important design factors for the output capacitor are dc voltage rating, ripple current rating, and equivalent
series resistance (ESR). The dc voltage and ripple current ratings cannot be exceeded. The ESR is important
because, along with the inductor ripple current, it determines the amount of output ripple voltage. The actual
value of the output capacitor is not critical, but some practical limits do exist. Consider the relationship between
the desired closed-loop crossover frequency of the design and LC corner frequency of the output filter. Due to
the design of the internal compensation, it is recommended to keep the closed-loop crossover frequency in the
range 3 kHz to 30 kHz, as this frequency range has adequate phase boost to allow for stable operation. For this
design example, the intended closed-loop crossover frequency is between 2590 Hz and 24 kHz, and below the
ESR zero of the output capacitor. Under these conditions, the closed-loop crossover frequency is related to the
LC corner frequency as:
f CO +
f LC
2
85 VOUT
(7)
and the desired output capacitor value for the output filter to:
1
C OUT +
3357 L OUT f CO V OUT
(8)
For a desired crossover of 18 kHz and a 33-µH inductor, the calculated value for the output capacitor is 100 µF.
The capacitor type should be chosen so that the ESR zero is above the loop crossover. The maximum ESR is:
1
ESR MAX +
2p C OUT f CO
(9)
The maximum ESR of the output capacitor also determines the amount of output ripple, as specified in the initial
design parameters. The output ripple voltage is the inductor ripple current times the ESR of the output filter.
Check that the maximum specified ESR as listed in the capacitor data-sheet results in an acceptable output
ripple voltage:
VPP(MAX) =
(
)
ESRMAX ´ VOUT ´ VIN(MAX) - VOUT
NC ´ VIN(MAX) ´ LOUT ´ FSW ´ 0.8
(10)
Where:
∆ VPP = Desired peak-to-peak output ripple
NC = Number of parallel output capacitors
FSW = Switching frequency
The minimum ESR of the output capacitor should also be considered. For a good phase margin, if the ESR is
zero when the ESR is at its minimum, it should not be above the internal compensation poles at 24 kHz and
54 kHz.
The selected output capacitor must also be rated for a voltage greater than the desired output voltage, plus
one-half the ripple voltage. Any derating amount must also be included. The maximum RMS ripple current in the
output capacitor is given by Equation 11:
ICOUT(RMS) =
1
Ö12
´
[
(
-
VOUT ´ VIN(MAX) - VOUT
)
VIN(MAX) ´ LOUT - FSW ´ 0.8 ´ NC
]
(11)
Where:
NC = Number of output capacitors in parallel
FSW = Switching frequency
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TPS5420-EP
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SLVS717 – DECEMBER 2006
For this design example, a single 100-µF output capacitor is chosen for C3. The calculated RMS ripple current is
143 mA, and the maximum ESR required is 88 mΩ. A capacitor that meets these requirements is an AVX
TPSD107M010R0080, rated at 10 V, with a maximum ESR of 80 mΩ and a ripple current rating of 1.369 A. This
capacitor results in a peak-to-peak output ripple of 26 mV using Equation 10. An additional small 0.1-µF ceramic
bypass capacitor may also used, but is not included in this design.
Other capacitor types can be used with the TPS5420, depending on the needs of the application.
Output Voltage Setpoint
The output voltage of the TPS5420 is set by a resistor divider (R1 and R2) from the output to the VSENSE pin.
Calculate the R2 resistor value for the output voltage of 5 V using Equation 12:
R1 1.221
R2 +
V
* 1.221
OUT
(12)
For any TPS5420 design, start with an R1 value of 10 kΩ. R2 is then 3.24 kΩ.
Boot Capacitor
The boot capacitor should be 0.01 µF.
Catch Diode
The TPS5420 is designed to operate using an external catch diode between PH and GND. The selected diode
must meet the absolute maximum ratings for the application—reverse voltage must be higher than the maximum
voltage at the PH pin, which is VINMAX + 0.5 V. Peak current must be greater than IOUTMAX plus one-half the
peak-to-peak inductor current. Forward voltage drop should be small for higher efficiencies. It is important to
note that the catch diode conduction time is typically longer than the high-side FET on time; therefore, the diode
parameters improve the overall efficiency. Additionally, check that the device chosen is capable of dissipating
the power losses. For this design, a Diodes, Inc. B340A is chosen, with a reverse voltage of 40 V, forward
current of 3 A, and a forward voltage drop of 0.5 V.
Additional Circuits
Figure 12 shows an application circuit using a wide input voltage range. The design parameters are similar to
those given for the design example, with a larger-value output inductor and a lower closed-loop crossover
frequency.
10 V - 21 V
VIN
ENA
C1
10 mF
U1
TPS5420D
7
5
2
3
6
VIN
BOOT
C2
0.01 mF
TP5
L1
27 mH
5V
1
VOUT
ENA
PH
NC
NC
VSNS
8
4
D1
B340A
+
C3
100 mF
(See Note A)
R1
10 kW
GND
R2
3.24 kW
A.
C3 = Tantalum AVX TPSD107M010R0080
Figure 12. 10-V — 21-V Input to 5-V Output Application Circuit
14
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ADVANCED INFORMATION
Output Voltage Limitations
Due to the internal design of the TPS5420, there are both upper and lower output voltage limits for any given
input voltage. The upper limit of the output voltage set point is constrained by the maximum duty cycle of 87%
and is given by:
V OUTMAX + 0.87
ƪǒVINMIN * I OMAX
Ǔ
ƫ ǒ
0.230 ) VD * I OMAX
Ǔ
RL * VD
(13)
Where:
VINMIN = Minimum input voltage
IOMAX = Maximum load current
VD = Catch diode forward voltage
RL = Output inductor series resistance
This equation assumes maximum on-resistance for the internal high-side FET.
The lower limit is constrained by the minimum controllable on time, which may be as high as 200 ns. The
approximate minimum output voltage for a given input voltage and minimum load current is given by:
V OUTMIN + 0.12
ƪǒVINMAX * I OMIN
Ǔ
ƫ ǒ
0.110 ) VD * I OMIN
Ǔ
RL * VD
(14)
Where:
VINMAX = Maximum input voltage
IOMIN = Minimum load current
VD = Catch diode forward voltage
RL = Output inductor series resistance
This equation assumes nominal on resistance for the high-side FET and accounts for worst-case variation of
operating frequency set point. Any design operating near the operational limits of the device should be checked
to ensure proper functionality.
Internal Compensation Network
The design equations given in the example circuit can be used to generate circuits using the TPS5420. These
designs are based on certain assumptions, and always select output capacitors within a limited range of ESR
values. If a different capacitor type is desired, it may be possible to fit one to the internal compensation of the
TPS5420. Equation 15 gives the nominal frequency response of the internal voltage-mode type III compensation
network:
s
s
1)
1)
2p Fz1
2p Fz2
H(s) +
s
s
s
s
1)
1)
1)
2p Fp0
2p Fp1
2p Fp2
2p Fp3
(15)
ǒ
ǒ
Ǔ ǒ
Ǔ ǒ
Ǔ ǒ
Ǔ
Ǔ ǒ
Ǔ
Where:
Fp0 = 2165 Hz, Fz1 = 2170 Hz, Fz2 = 2590 Hz
Fp1 = 24 kHz, Fp2 = 54 kHz, Fp3 = 440 kHz
Fp3 represents the non-ideal parasitics effect.
Using this information, along with the desired output voltage, feed-forward gain, and output filter characteristics,
the closed-loop transfer function can be derived.
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TPS5420-EP
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ADVANCED INFORMATION (continued)
Thermal Calculations
The following formulas show how to estimate the device power dissipation under continuous conduction mode
operations. They should not be used if the device is working at light loads in the discontinuous conduction mode.
Conduction loss: Pcon = IOUT2× rDS(on)× VOUT/VIN
Switching loss: Psw = VIN× IOUT× 0.01
Quiescent current loss: Pq = VIN× 0.01
Total loss: Ptot = Pcon + Psw + Pq
Given TA => Estimated junction temperature: TJ = TA + Rth × Ptot
Given TJMAX = 125°C => Estimated maximum ambient temperature: TAMAX = TJMAX Rth × Ptot
16
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PERFORMANCE GRAPHS
The performance graphs in Figure 13 through Figure 19 are applicable to the circuit in Figure 11. TA = 25°C
(unless otherwise specified).
100
VI = 10.8 V
0.3
0.2
0.2
VI = 12 V
IO = 2 A
Output Regulation - %
VI = 15 V
90
85
VI = 18 V
VI = 19.8 V
80
Output Regulation - %
95
Efficiency - %
0.3
0.1
0
-0.1
-0.2
0
0.5
1
1.5
2
IO - Output Current - A
2.5
3
IO = 0 A
0
-0.1
IO = 1 A
-0.2
-0.3
75
0.1
-0.3
0
0.5
1
1.5
2
2.5
3
0
0.5
IO - Output Current - A
Figure 13. Efficiency
vs Output Current
Figure 14. Output Regulation %
vs Output Current
VIN = 100 mV/Div (AC Coupled)
1
3
IOUT = 500 mA/Div
t - Time = 200 μs/Div
t - Time - 1 ms / Div
Figure 16. Input Voltage Ripple
and PH Node, IO = 3 A
2.5
VOUT = 50 mV/Div (AC Coupled)
PH = 5 V/Div
t - Time - 1 ms / Div
2
Figure 15. Input Regulation %
vs Input Voltage
VOUT = 20 mV/Div (AC Coupled)
PH = 5 V/Div
1.5
VI - Input Voltage - V
Figure 17. Output Voltage Ripple
and PH Node, IO = 3 A
Figure 18. Transient Response, IO
Step 0.5 to 1.5 A
VIN = 10 V/Div
ENA = 2 V/Div
VOUT = 2 V/Div
VOUT = 2 V/Div
t - Time = 5 ms/Div
Figure 19. Startup Waveform,
VIN and VOUT
t - Time = 5 ms/Div
Figure 20. Startup Waveform,
ENA and VOUT
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS5420MDREP
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
5420MEP
TPS5420MDREPG4
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
5420MEP
V62/07613-01XE
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
5420MEP
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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