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TPS3847
SBVS231A – AUGUST 2014 – REVISED MARCH 2015
TPS3847 18-V, 380-nA Voltage Monitor
1 Features
3 Description
•
•
•
•
•
•
•
•
The TPS3847 family consists of wide operating
voltage, ultralow-current devices that monitor the
voltage at the supply pin. The device asserts an
active-low reset signal whenever the VCC supply
voltage drops below the factory-trimmed reset
threshold voltage. The reset output remains asserted
for 20 ms (max) after the VCC voltage rises above
the threshold voltage.
1
•
•
Ultralow Supply Current: 380 nA
Wide Supply Voltage Range: 4.5 V to 18 V
High Threshold Accuracy: ±2.5%
Internal Hysteresis
Push-Pull Output
20-ms (max) Delay Timing
Factory-Trimmed, Fixed-Voltage Thresholds
Specified Operating Temperature Range:
–40°C to +85°C
Operational from –40°C to +105°C
Package: 5-Pin SOT
2 Applications
•
•
•
•
•
Portable and Battery-Powered Equipment
Desktops, Notebooks, and Ultrabooks
Industrial Systems
Servers
Security Systems
The ultralow current consumption of 380 nA
combined with 18-V capability makes the TPS3847
ideal for use in low-power and portable applications.
The TPS3847 features precision, factory-trimmed
threshold voltages and extremely low-power
operation. The TPS3847 is available in an industrystandard, 5-pin, SOT package.
Device Information(1)
PART NUMBER
TPS3847
900
-40C
85C
CIN
0.1 mF
VCC
VCC
TPS3847
Regulator
GND
OUT
Supply Current (nA)
800
EN
2.90 mm × 1.60 mm
Supply Current vs Supply Voltage
12 V
RESET
BODY SIZE (NOM)
SOT (5)
(1) For all available packages, see the package option addendum
at the end of the datasheet.
Typical Application
MR
PACKAGE
0C
105C
25C
700
600
500
400
300
200
4
6
8
10
12
Supply Voltage (V)
14
16
18
C007
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS3847
SBVS231A – AUGUST 2014 – REVISED MARCH 2015
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
6
7
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Detailed Description .............................................. 9
7.1 Overview ................................................................... 9
7.2 Functional Block Diagram ......................................... 9
7.3 Feature Description................................................... 9
7.4 Device Functional Modes........................................ 11
8
Application and Implementation ........................ 12
8.1 Application Information............................................ 12
8.2 Typical Application .................................................. 12
8.3 Do's and Don'ts ....................................................... 15
9 Power Supply Recommendations...................... 15
10 Layout................................................................... 15
10.1 Layout Guidelines ................................................. 15
10.2 Layout Example .................................................... 15
11 Device and Documentation Support ................. 16
11.1
11.2
11.3
11.4
11.5
Device Support ....................................................
Documentation Support ........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
16
16
16
16
16
12 Mechanical, Packaging, and Orderable
Information ........................................................... 16
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (August 2014) to Revision A
Page
•
Changed device name to reflect entire family of devices ...................................................................................................... 1
•
Changed all SOT-23 to SOT ................................................................................................................................................. 1
•
Changed MR maximum specification in Absolute Maximum Ratings table ........................................................................... 4
•
Changed V(MR) maximum specification in Recommended Operating Conditions table ......................................................... 4
•
Deleted maximum value for CIN in Recommended Operating Conditions ............................................................................. 4
•
Changed conditions of Electrical Characteristics table: added condition for typical values .................................................. 5
•
Added new row to VIT– for TPS3847108 in Electrical Characteristics .................................................................................... 5
•
Added new row to VHYS for TPS3847108 in Electrical Characteristics................................................................................... 5
•
Added maximum specification to second row of VOL parameter in Electrical Characteristics table ...................................... 5
•
Changed VOH test conditions to IOH = 2 mA in Electrical Characteristics table ..................................................................... 5
•
Added conditions to Timing Requirements table ................................................................................................................... 6
•
Changed td(START) maximum specification in Timing Requirements table............................................................................... 6
•
Added condition to Figure 2 .................................................................................................................................................. 7
•
Changed Y-axis in Figure 12 ................................................................................................................................................ 10
•
Changed title of Typical Application section ........................................................................................................................ 12
2
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5 Pin Configuration and Functions
DBV Package
5-Pin SOT
(Top View)
RESET
1
GND
2
NC
3
5
VCC
4
MR
Pin Functions
PIN
NAME
NO.
I/O
GND
2
—
DESCRIPTION
MR
4
I
NC
3
—
No internal connection.
RESET
1
O
Active low reset output. RESET stays low as long as the voltage on VCC is below the factory trimmed
threshold voltage. RESET transitions from low to high once the VCC voltage is above the positive-going
threshold voltage for a specified time (td). RESET is a push-pull output.
VCC
5
I
Power supply and monitored voltage. TI recommends adding a small 0.1-μF bypass capacitor near the VCC
pin.
Ground
Manual reset. Pull this pin to a logic low to force the RESET output low regardless of the voltage on VCC.
After the MR pin is pulled to a logic high, the RESET output goes high after the RESET delay time (td) if the
voltage on VCC is higher than the positive-going threshold voltage.
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6 Specifications
6.1 Absolute Maximum Ratings (1)
over operating junction temperature range (unless otherwise noted)
Voltage
Current
(2)
MAX
UNIT
–0.3
+20
V
MR
–0.3
VCC + 0.3
V
RESET
–0.3
+5.5
V
10
mA
RESET
Temperature (2)
(1)
MIN
VCC
Operating junction, TJ
–40
+105
°C
Storage, Tstg
–65
+150
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.
As a result of the low dissipated power in this device, it is assumed that the junction temperature is equal to the ambient temperature.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
MIN
NOM
V(VCC)
Power supply voltage
4.5
V(MR)
MR pin voltage
0
V(RESET)
RESET pin voltage
0
I(RESET)
RESET pin current
0
CIN
Input capacitor
0
0.1
TJ
Junction temperature
–40
+25
1.2
MAX
UNIT
18
V
VCC
V
5
V
2
mA
µF
+85
°C
6.4 Thermal Information
TPS3847
THERMAL METRIC
(1)
DBV (SOT)
UNIT
5 PINS
RθJA
Junction-to-ambient thermal resistance
208.5
RθJC(top)
Junction-to-case (top) thermal resistance
123.3
RθJB
Junction-to-board thermal resistance
37.2
ψJT
Junction-to-top characterization parameter
14.6
ψJB
Junction-to-board characterization parameter
36.3
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
(1)
4
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics
At TJ = –40°C to +85°C, 4.5 V < VCC < 18 V, and CIN = 0.1 µF (unless otherwise noted). Typical values are at TJ = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
V(VCC)
Input supply voltage range
VVO
Minimum V(VCC) voltage for valid
output (1)
4.5
IOL = 1 µA, VOL = 400 mV
I(VCC)
Supply current (into VCC pin)
Output not
connected
TJ = 25°C, V(VCC) = 18 V
18
V
0.8
V
380
nA
TJ = 25°C
750
nA
–40°C ≤ TJ ≤ +85°C
900
nA
MONITORED THRESHOLD
Negative going input threshold
accuracy
VIT–
Negative-going threshold voltage
VHYS
Hysteresis voltage
TJ = 25°C
±0.5%
–2.5%
TPS3847085
8.2875
TPS3847108
10.53
+2.5%
8.5
8.7125
V
10.8
11.07
V
TPS3847085
0.11 × VIT–
V
TPS3847108
0.035 × VIT–
V
OUTPUT
Push-pull low-level output voltage
(RESET)
VOL
0.9 V < V(VCC) < 2.4 V, IOL= 10 μA
0.009
0.4
V
2.4 V ≤ V(VCC) < 4.5 V, IOL= 250 μA
0.015
0.4
V
0.09
0.4
V
3.1
V
4.5 V ≤ V(VCC) ≤ 18 V, IOL= 2 mA
IOH = –2 mA
Push-pull high-level output voltage
(RESET)
VOH
IOH = –10 µA
1.6
V(VCC) = 18 V
2.45
3
V(VCC) = 18 V
V
4
3.55
V
V
MR PIN
VIL
Low-level input voltage
VIH
High-level input voltage
Ilkg(MR)
MR leakage current
(1)
0.4
1.2
MR High, V(VCC) = 18 V
V
V
–23
nA
The lowest supply voltage (V(VCC)) at which RESET is valid. tRISE(VCC) ≥ 15 µs/V, where tRISE is the rise time.
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6.6 Timing Requirements
At TJ = –40°C to +85°C, 4.5 V < VCC < 18 V, and CIN = 0.1 μF (unless otherwise noted). Typical values are at TJ = 25°C.
TYP
MAX
td
RESET delay time
(1)
PARAMETER
4.5
20
ms
td(START)
Startup delay time (2)
6.5
40
ms
tpd(VCC)
Propagation delay for VCC falling (3)
55
µs
tpd(MR)
Propagation delay MR falling (4)
50
µs
tP(MR)
MR minimum high to low pulse duration for RESET low
50
µs
(1)
(2)
(3)
(4)
MIN
UNIT
Delay from when V(VCC) ≥ VIT– or VMR ≥ VIH until RESET goes high when V(VCC) starts from above the specified minimum V(VCC).
Measured with 5% overdrive.
When V(VCC) starts from less than the specified minimum V(VCC) and then exceeds Vth, RESET goes high after the startup delay
(td(START)) instead of the RESET delay time (td). Measured with 5% overdrive.
Delay from V(VCC) < Vth until RESET goes low. Measured with 8% overdrive.
Delay from VMR < VIL until RESET goes low. Measured with 8% overdrive.
VIT± + Vhys
VIT±
VCC
VVO
RESET
td(START)
tpd(VCC)
td
tpd(MR)
td
VIH
MR
VIL
Timing Diagram
6
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6.7 Typical Characteristics
At V(VCC) = 18 V, MR = 1.2 V, RESET = open, and CIN = 0.1 µF (unless otherwise noted).
12
VHYS as a Percent of VIT- (%)
1
VIT- Accuracy (%)
0.5
0
-0.5
11.5
11
10.5
10
9.5
-1
9
±40
±15
10
35
60
85
±40
110
Temperature (C)
±15
10
35
60
85
110
Temperature (C)
C008
C011
TPS3847085
Figure 1. Negative-Going Threshold Accuracy
vs Temperature
900
-40C
85C
0C
105C
Figure 2. Hysteresis vs Temperature
14
25C
RESET Delay Time (mS)
750
Supply Current (nA)
Unit 1
Unit 4
12
600
450
300
150
Unit 2
Unit 5
Unit 3
Average
10
8
6
4
2
0
0
0
2
4
6
8
10
12
14
16
Supply Voltage (V)
±40
18
±15
10
35
60
85
110
Temperature (C)
C007
C002
V(VCC) transitions from 7 V to 10 V
Figure 3. Supply Current vs V(VCC) and Temperature
Unit 1
Unit 4
Unit 2
Unit 5
Figure 4. RESET Delay Time vs Temperature Distribution
14
Unit 3
Average
Unit 1
Unit 4
12
Unit 2
Unit 5
Unit 3
Average
20
MR Delay Time (mS)
Startup Delay Time (mS)
25
15
10
10
8
6
4
5
2
0
0
±40
±15
10
35
60
Temperature (C)
85
110
±40
V(VCC) transitions from 0 V to 10 V
±15
10
35
60
85
Temperature (C)
C001
110
C003
MR transitions from 0.4 V to 1.2 V, V(VCC) = 10 V
Figure 5. Startup Delay Time vs Temperature Distribution
Figure 6. MR Delay Time vs Temperature Distribution
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Typical Characteristics (continued)
1.2
MR Threshold (V)
1
0.8
0.6
0.4
0.2
VIH
VIL
0
±40
±15
10
35
60
85
Temperature (C)
110
Minimum VCC Voltage for Valid Output (V)
At V(VCC) = 18 V, MR = 1.2 V, RESET = open, and CIN = 0.1 µF (unless otherwise noted).
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
±40
±15
10
V(VCC) = 10 V
0C
105C
0.2
25C
4
3
2
1
110
C010
-40C
85C
0C
105C
25C
0.16
0.12
0.08
0.04
0
0
0.25
0.5
0.75
1
1.25
Load Current (mA)
1.5
1.75
2
0
0.25
0.5
0.75
1
1.25
Load Current (mA)
C004
Figure 9. High-Level Output Voltage vs Load Current
8
85
Figure 8. Minimum V(VCC) for Valid Output vs Temperature
Low Level Output Voltage (V)
High Level Output Voltage (V)
-40C
85C
60
MR open
Figure 7. MR Threshold vs Temperature
5
35
Temperature (C)
C009
1.5
1.75
2
C005
Figure 10. Low-Level Output Voltage vs Load Current
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7 Detailed Description
7.1 Overview
The TPS3847 is a family of ultralow-current supervisors for high-voltage applications that are specified from
–40°C to +85°C and operational up to 105°C (see the Typical Characteristics section for typical –40°C to +105°C
performance).
The RESET output goes low after the power-supply voltage (V(VCC)) drops below the negative-going input
threshold voltage (VIT–), and after the VCC falling propagation delay (tpd(VCC)) elapses. When V(VCC) rises above
the positive-going reset threshold (VIT+), which is the negative-going threshold voltage plus the hysteresis (VIT– +
Vhys), RESET outputs a high signal after the reset delay time (td) elapses.
The TPS3847 also features a manual reset pin (MR) that allows a processor, or other logic devices, to initiate a
reset, even when V(VCC) exceeds VIT–. A logic low on MR causes RESET to transition to logic low after the MR
propagation delay (tpd(MR)) elapses. When MR returns to a logic high and V(VCC) exceeds VIT+, RESET transitions
to logic high after td elapses.
7.2 Functional Block Diagram
VCC
Delay
RESET
VREF
GND
VCC
MR
7.3 Feature Description
7.3.1 Ultralow Supply Current
The TPS3847 uses a unique sampling scheme to maintain an extremely-low average quiescent current of
380 nA. This low quiescent current is ideal for applications that require extremely-low power consumption.
7.3.2 Wide Supply Range
This device has an operational input supply range of 4.5 V to 18 V, allowing for a wide range of applications. This
wide supply range is ideal for applications that have either large transients or high dc voltage supplies.
7.3.3 High-Accuracy Negative Threshold
The TPS3847 has a negative threshold accuracy of ±2.5% and uses well-controlled and matched internal
resistors to set the threshold voltage in order to eliminate the inaccuracies because of the external resistors.
Unlike The TPS3847, voltage supervisors that require external resistors to set the threshold voltage always add
inaccuracy to the specified performance.
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Feature Description (continued)
7.3.4 Push-Pull Output
The TPS3847 has a push-pull output stage that covers many of the common digital logic levels. Push-pull
outputs simplify many designs compared to open-drain output devices because push-pull outputs do not require
a pull-up resistor or an additional low-voltage rail. Compared to open-drain output devices, push-pull devices
reduce power consumption when the output is low because open-drain devices sink current through the pull-up
resistor to ground in order to create the logic-low signal.
7.3.5 Manual Reset (MR) Input
The manual reset (MR) input allows a processor, or other logic devices, to initiate a reset even when the voltage
on VCC is greater than VIT–. A logic low on MR causes RESET to output a logic low. After MR returns to a logic
high and the power-supply voltage is greater than VIT+, RESET transitions to logic high after the reset delay time
(td) elapses.
7.3.6 VCC Transient Rejection
The TPS3847 has built-in rejection of fast transients on the VCC pin. Transient rejection depends on both the
duration and overdrive, or amplitude, of the transient. Overdrive of the transient is measured from the bottom of
the transient to the negative threshold voltage (VIT–) of the device, as shown in Figure 11.
V(VCC)
VITTransient
Amplitude
Transient
Duration
(tW)
Figure 11. Voltage Transient Measurement
Figure 12 shows the relationship between the overdrive and the duration required to trigger a reset. Any
combination of duration and amplitude greater than that shown in Figure 12 generates a reset signal.
V(VCC) Minimum Detectable Pulse ( s)
35
-40C
85C
30
0C
105C
25C
Reset Occurs Above the Lines
25
20
15
10
5
0
0
2
4
6
8
10
12
Overdrive (%)
14
16
18
C006
Figure 12. Minimum Detectable Pulse on VCC vs Overdrive
10
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Feature Description (continued)
7.3.7 Controlled Startup Current
The input supply current of the TPS3847 is very well controlled, including during startup. Some low-current
devices exhibit spikes in the supply current before reaching the minimum supply voltage; this type of startup
behavior can cause problems in some applications. Figure 13 shows that there are no spikes in supply current,
and the device is well controlled all the way from 0 V to minimum V(VCC).
900
-40C
85C
0C
105C
25C
Supply Current (nA)
750
600
450
300
150
0
0
1.5
3
4.5
Supply Voltage (V)
C007
Figure 13. Supply Current During Startup
7.3.8 Low Minimum Supply Voltage for Valid Output
Minimum VCC Voltage for Valid Output (V)
The TPS3847 is designed to have a valid RESET signal, even with a low input supply voltage. Figure 14 shows
that even at –40°C, the TPS3847 typically has a valid output with only 0.65 V on the input supply; at 105°C, that
input supply voltage goes down to less than 0.45 V.
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
±40
±15
10
35
60
Temperature (C)
85
110
C010
Figure 14. Minimum Supply Voltage for Valid Output vs Temperature
7.4 Device Functional Modes
The TPS3847 has two functional modes:
1. MR high: in this mode, RESET is high or low depending on the value of V(VCC) relative to VIT–.
2. MR low: in this mode, RESET is held low regardless of the value of V(VCC).
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS3847 family consists of wide-operating voltage, ultralow-current devices that monitor the power-supply
voltage. The device asserts an active-low reset signal whenever the supply voltage drops below the factorytrimmed reset. The ultralow current consumption of 380 nA combined with 18-V capability makes the TPS3847
ideal for use in low-power and portable applications.
8.2 Typical Application
Wide operating voltage and threshold options make the TPS3847 well suited for monitoring dual- and triple-cell,
lithium-ion battery applications. Figure 15 shows the TPS3847 used to disable a buck converter when the cell
voltage discharges below the threshold voltage. When the cell voltage reaches VIT–, the enable pin of the
TPS62120 is driven low, placing the buck converter in a low-current, shutdown state.
VIN
SW
GND
FB
VCC
TPS62120
TPS3847
Multicell
Li-Ion
RESET
MR
EN
VOUT
SGND
GND
PG
Figure 15. Disabled Buck Converter
8.2.1 Design Requirements
8.2.1.1 Input Capacitor
The TPS3847 uses a unique sampling scheme to maintain an extremely low average quiescent current of
380 nA. However, this current rises to approximately 12 µA for approximately 500 µs while the TPS3847
refreshes the reference voltage. This refresh pulse typically occurs every 200 ms. If the source impedance to the
supply voltage is high, then the additional current during sampling may trigger a false reset as a result of the
voltage drop from the supply to the VCC pin. For sources with a high impedance, or applications with long or thin
VCC traces, add a 0.1-µF or larger bypass capacitor near the VCC pin. Adding this bypass capacitor effectively
keeps the average current supplied from the input source close to 380 nA, reducing the voltage droop caused by
the refresh pulse, and is good analog design practice.
12
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Typical Application (continued)
8.2.1.2 Driving Bidirectional Reset Pins
Some microcontrollers have bidirectional reset pins that act as both an input and an output. When using
bidirectional reset pins, place a series resistor between the TPS3847 RESET pin and the microcontroller in order
to protect against excessive current flow in case both the TPS3847 and the microcontroller attempt to drive the
reset line simultaneously. Figure 16 illustrates the connection of the TPS3847 to a microcontroller using a series
resistor to drive a bidirectional reset line. Assuming the maximum voltage that the microprocessor outputs is the
same as the TPS3847 (4 V), use a resistor value greater than 20 kΩ in order to limit the output current to 2 mA
or less when one pin is driven high and the other is driven low. In order to cover the majority of applications, use
a resistor value of 47 kΩ.
V(VCC)
V(VCC)
Microprocessor
TPS3847
47 k:
RESET
RST
GND
Figure 16. Connection to Bidirectional Reset Pin
8.2.1.3 Manual Reset (MR) Input
The manual reset (MR) input allows a processor, or other logic devices, to initiate a reset. A logic low on MR
causes RESET to transition to logic low. After MR returns to a logic high and V(VCC) is greater than VIT+, RESET
transitions to a logic high after the reset delay time, td, elapses.
Note that internal to the device MR is connected to a very small current source that goes from the internal subregulated voltage to the MR node. If the logic signal driving MR does not exceed 3 V, there is 25 nA of additional
current drawn from the input supply because of this current source. Do not leave this pin floating; either drive this
pin above or below the MR high and low input levels. Tie MR directly to VCC if not used.
8.2.1.4 Threshold Overdrive
Threshold overdrive is how much V(VCC) exceeds the specified threshold, and is important to know because the
smaller the overdrive, the slower the RESET response. Threshold overdrive is calculated as a percent of the
threshold in question, as shown in Equation 1:
Overdrive = |(V(VCC) / VIT – 1) × 100%|
where:
•
VIT is either VIT– or VIT+, depending on whether calculating the overdrive for the negative-going threshold or the
positive-going threshold, respectively.
(1)
Figure 12 illustrates the VCC minimum detectable pulse versus overdrive, and is used to visualize the
relationship overdrive has on tpd(VCC) for negative-going events.
For positive-going events, after the overdrive is greater than 5%, the changes to td are negligible because of the
significantly longer delay time. When overdrive is less than 5%, td can increase to 200 ms while the device waits
for the next voltage reference refresh pulse.
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Typical Application (continued)
8.2.2 Detailed Design Procedure
● Select desired device based on the threshold voltage.
● Ensure that the trace from the input supply to the VCC pin is low impedance in order to avoid false reset
signals during the refresh cycle. If the impedance is too high, add an input capacitor of 0.1-µF or larger close to
the VCC pin (see the Input Capacitor section).
● If the RESET of the TPS3847 is driving a bidirectional pin, place a resistor between the output of the TPS3847
and the bidirectional pin (see the Driving Bidirectional Reset Pins section).
8.2.3 Application Curves
VCC
2 V/div
RESET
200 mV/div
VIT+ + 5%
td
VCC
5 V/div
VVO
RESET
1 V/div
Time (2 ms/div)
Time (2 ms/div)
Figure 18. Startup Delay Time
Figure 17. Startup Showing Minimum V(VCC) for
Valid Output
VCC
2 V/div
VIT+ + 5%
RESET
1 V/div
tpd(VCC)
Time (2 ms/div)
Figure 19. Propagation Delay Time
14
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8.3 Do's and Don'ts
Connect a 0.1-µF to 1.0-µF low equivalent series resistance (ESR) capacitor between the VCC pin and the GND
pin.
Connect the MR pin to a voltage higher than 1.2 V in order for RESET to go high or low, depending on the value
of V(VCC) relative to VIT–.
Connect the MR pin to a voltage lower than 0.4 V in order to hold RESET low, regardless of the value of V(VCC).
Connect the MR pin to the VCC pin if MR functionality is not used.
Do not connect the VCC pin to a high-impedance supply without a 0.1-µF to 1.0-µF low equivalent series
resistance (ESR) bypass capacitor.
Do not use a thin, long trace to connect the VCC pin to the input supply without a 0.1-µF to 1.0-µF low ESR
bypass capacitor.
Do not leave the MR pin floating.
9 Power Supply Recommendations
These devices are designed to operate from an input supply with a voltage range between 4.5 V and 18 V. Use a
low-impedance power supply to eliminate inaccuracies caused by the current during the voltage-reference
refresh.
10 Layout
10.1 Layout Guidelines
Make sure the connection to the VCC pin is low impedance and able to carry 12 µA without a significant voltage
drop. Place a 0.1-µF bypass capacitor near the VCC pin if the 12-µA current causes too much voltage droop.
10.2 Layout Example
The layout example in Figure 20 shows how the TPS3847 is laid out on a printed circuit board (PCB). Although
not required, use CIN for best device performance.
VCC
RESET
VCC
CIN
GND
MR
GND
Represents vias used for
application specific connections
Figure 20. Layout Example
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Device Nomenclature
TPS3847xxxyyy is the generic naming convention for this device. TPS3847 represents the family of these
devices, xxx is used to display the negative going threshold voltage and a decimal should be placed after the
second number while yyy is reserved for the package designator.
Example: TPS3847085DBV
Family: TPS3847
Negative-Going Threshold Voltage: 8.5 V
DBV Package: 5-pin SOT
11.2 Documentation Support
11.2.1 Related Documentation
TPS3847085EVM-577 Evaluation Module User's Guide, SBVU023
TPS62120 Data Sheet, SLVSAD5
11.3 Trademarks
All trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
16
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS3847085DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 105
PC7I
TPS3847085DBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 105
PC7I
TPS3847108DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 105
ZBYD
TPS3847108DBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 105
ZBYD
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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