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TPS4H160-Q1
SLVSCV8D – DECEMBER 2015 – REVISED DECEMBER 2019
TPS4H160-Q1 40-V, 160-mΩ Quad-Channel Smart High-Side Switch
1 Features
•
•
1
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to asd
125°C Ambient Operating Temperature Range
– Device HBM ESD Classification Level H3A
– Device CDM ESD Classification Level C4B
Functional safety capable
– Documentation available to aid functional
safety system design
Quad-Channel 160-mΩ Smart High-Side Switch
With Full Diagnostics
– Version A: Open-Drain Digital Output
– Version B: Current-Sense Analog Output
Wide Operating Voltage 3.4 V to 40 V
Ultralow Standby Current, < 500 nA
High-Accuracy Current Sense: ±15% Under >25mA Load
Adjustable Current Limit With External Resistor,
±15% Under >500 mA Load
Protection
– Short-to-GND Protection by Current Limit
(Internal or External)
– Thermal Shutdown With Latch Off Option and
Thermal Swing
– Inductive Load Negative Voltage Clamp With
Optimized Slew Rate
Typical Application Schematic
3.4 V to 40 V
SupplyVoltage
•
•
– Loss-of-GND and Loss-of-Battery Protection
Diagnostics
– Overcurrent and Short-to-Ground Detection
– Open-Load and Short-to-Battery Detection
– Global Fault Report for Fast Interrupt
28-Pin Thermally-Enhanced PWP Package
2 Applications
•
•
•
•
Multichannel LED Drivers, Bulb Drivers
Multichannel High-Side Switches for Sub-Modules
Multichannel High-Side Relay, Solenoid Drivers
PLC Digital Output Drivers
3 Description
The TPS4H160-Q1 device is fully protected quadchannel smart high-side switch with four integrated
160-mΩ NMOS power FETs.
Full diagnostics and high-accuracy current sense
enable intelligent control of the load.
An external adjustable current limit improves the
reliability of whole system by limiting the inrush or
overload current.
Device Information(1)
PART NUMBER
TPS4H160-Q1 Version A
TPS4H160-Q1 Version B
PACKAGE
HTSSOP (28)
CHANNELS
4
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Driving a Capacitive Load With Adjustable
Current Limit
VS
IN1, 2, 3, 4
OUT1
DIAG_EN
LED Strings,
Small Power Bulbs
THER
SEH
ST1
SEL
ST2
FAULT
ST3
CS
ST4
OUT2
Solenoids, Valves, Relays
OUT3
Sub-Module:
Cameras, Sensors, Displays
OUT4
General Resistive, Capacitive,
Inductive Loads
Overcurrent Is Clamped
at the Set Value of 1 A.
CL
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS4H160-Q1
SLVSCV8D – DECEMBER 2015 – REVISED DECEMBER 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
8
1
1
1
2
3
3
6
Absolute Maximum Ratings ...................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 7
Thermal Information ................................................. 7
Electrical Characteristics........................................... 7
Switching Characteristics .......................................... 9
Typical Characteristics ............................................ 11
Detailed Description ............................................ 14
8.1 Overview ................................................................. 14
8.2 Functional Block Diagram ....................................... 15
8.3 Feature Description................................................. 15
8.4 Device Functional Modes........................................ 27
9
Application and Implementation ........................ 28
9.1 Application Information............................................ 28
9.2 Typical Application ................................................. 28
10 Power Supply Recommendations ..................... 30
11 Layout................................................................... 31
11.1 Layout Guidelines ................................................. 31
11.2 Layout Examples................................................... 31
12 Device and Documentation Support ................. 33
12.1
12.2
12.3
12.4
12.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
33
33
33
33
33
13 Mechanical, Packaging, and Orderable
Information ........................................................... 33
4 Revision History
Changes from Revision C (March 2018) to Revision D
•
Page
Added Functional safety capable link to the Features section ............................................................................................... 1
Changes from Revision B (January 2017) to Revision C
Page
•
Added footnote 2 to the Electrical Characteristics table ........................................................................................................ 8
•
Added reverse current protection information to the Reverse-Current Protection section .................................................. 26
Changes from Revision A (April 2016) to Revision B
Page
•
Added an illustration to the first page ..................................................................................................................................... 1
•
Changed the functional block diagram ................................................................................................................................. 15
•
Changed Figure 38............................................................................................................................................................... 29
•
Added Receiving Notification of Documentation Updates section ....................................................................................... 33
Changes from Original (December 2015) to Revision A
•
2
Page
Changed data sheet from PRODUCT PREVIEW to PRODUCTION DATA .......................................................................... 1
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SLVSCV8D – DECEMBER 2015 – REVISED DECEMBER 2019
5 Device Comparison Table
PART NO.
FAULT REPORTING MODE
TPS4H160-Q1 Version A
Open-drain digital output
TPS4H160-Q1 Version B
Current-sense analog output
6 Pin Configuration and Functions
PWP Package
28-Pin HTSSOP With Exposed Thermal Pad
TPS4H160-Q1 Version A Top View
GND
1
28
OUT1
NC
2
27
OUT1
IN1
3
26
OUT2
IN2
4
25
OUT2
IN3
5
24
NC
IN4
6
23
VS
ST1
7
22
VS
21
VS
Thermal
Pad
ST2
8
ST3
9
20
VS
ST4
10
19
NC
CL
11
18
OUT3
GND
12
17
OUT3
THER
13
16
OUT4
DIAG_EN
14
15
OUT4
NC – No internal connection
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PWP Package
28-Pin HTSSOP With Exposed Thermal Pad
TPS4H160-Q1 Version B Top View
GND
1
28
OUT1
NC
2
27
OUT1
IN1
3
26
OUT2
IN2
4
25
OUT2
IN3
5
24
NC
IN4
6
23
VS
SEH
7
22
VS
21
VS
Thermal
Pad
SEL
8
FAULT
9
20
VS
CS
10
19
NC
CL
11
18
OUT3
GND
12
17
OUT3
THER
13
16
OUT4
DIAG_EN
14
15
OUT4
NC – No internal connection
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
VERSION A
VERSION B
11
11
O
Adjustable current limit. Connect to device GND if external current limit is not
used.
CS
—
10
O
Current-sense output
DIAG_EN
14
14
I
Enable-disable pin for diagnostics; internal pulldown
FAULT
—
9
O
Global fault report with open-drain structure, ORed logic for quad-channel fault
conditions
Ground pin
CL
GND
1, 12
1, 12
—
IN1
3
3
I
Input control for channel 1 activation; internal pulldown
IN2
4
4
I
Input control for channel 2 activation; internal pulldown
IN3
5
5
I
Input control for channel 3 activation; internal pulldown
IN4
6
6
I
Input control for channel 4 activation; internal pulldown
NC
2, 19, 24
2, 19, 24
—
No internal connection
ST1
7
—
O
Open-drain diagnostic status output for channel 1
4
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Pin Functions (continued)
PIN
NAME
NO.
I/O
DESCRIPTION
VERSION A
VERSION B
ST2
8
—
O
Open-drain diagnostic status output for channel 2
ST3
9
—
O
Open-drain diagnostic status output for channel 3
ST4
10
—
O
Open-drain diagnostic status output for channel 4
SEH
—
7
I
CS channel-selection high bit; internal pulldown
SEL
—
8
I
CS channel-selection low bit; internal pulldown
THER
13
13
I
Thermal shutdown behavior control, latch off or auto-retry; internal pulldown
OUT1
27, 28
27, 28
O
Output of the channel 1 high side-switch, connected to the load
OUT2
25, 26
25, 26
O
Output of the channel 2 high side-switch, connected to the load
OUT3
17, 18
17, 18
O
Output of the channel 3 high side-switch, connected to the load
OUT4
VS
Thermal
pad
15, 16
15, 16
O
Output of the channel 4 high side-switch, connected to the load
20, 21, 22,
23
20, 21, 22,
23
I
Power supply
—
—
—
Connect to device GND or leave floating
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7 Specifications
7.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted)
(1) (2)
MIN
MAX
UNIT
48
V
–100
250
mA
–0.3
7
V
Current on INx, DIAG_EN, SEL, SEH, and THER pins
–10
—
mA
Voltage on STx or FAULT pins
–0.3
7
V
Current on STx or FAULT pins
–30
10
mA
Voltage on CS pin
–2.7
7
V
Current on CS pin
—
30
mA
Voltage on CL pin
–0.3
7
V
Current on CL pin
—
6
mA
Supply voltage
Reverse polarity voltage
t < 400 ms
(3)
Current on GND pin
–36
t < 2 minutes
Voltage on INx, DIAG_EN, SEL, SEH, and THER pins
Inductive load switch-off energy dissipation, single pulse, single channel (4)
V
—
40
mJ
Operating junction temperature
–40
150
°C
Storage temperature, Tstg
–65
150
°C
(1)
(2)
(3)
(4)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to the ground plane.
Reverse polarity condition: t < 60 s, reverse current < IR(2), VINx = 0 V, all channels reverse, GND pin 1-kΩ resistor in parallel with diode.
Test condition: VVS = 13.5 V, L = 8 mH, R = 0 Ω, TJ = 150°C. FR4 2s2p board, 2 × 70-μm Cu, 2 x 35-µm Cu. 600 mm2 thermal pad
copper area.
7.2 ESD Ratings
VALUE
Human-body model (HBM), per AEC
Q100-002 (1)
V(ESD)
Electrostatic discharge
Charged-device model (CDM), per AEC
Q100-011
(1)
6
All pins except VS, OUTx,
GND
±4000
Pins VS, OUTx, GND
±5000
All pins
±750
Corner pins (1, 14, 15,
and 28)
±750
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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7.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
VVS
TA
MIN
MAX
Supply operating voltage
4
40
V
Voltage on INx, DIAG EN, SEL, SEH, and THER pins
0
5
V
Voltage on STx and FAULT pins
0
5
V
Nominal dc load current
0
2.5
A
–40
125
°C
Operating ambient temperature range
UNIT
7.4 Thermal Information
TPS4H160-Q1
THERMAL METRIC (1)
PWP (HTSSOP)
UNIT
28 PINS
RθJA
Junction-to-ambient thermal resistance
32.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
17.1
°C/W
RθJB
Junction-to-board thermal resistance
14.4
°C/W
ψJT
Junction-to-top characterization parameter
0.5
°C/W
ψJB
Junction-to-board characterization parameter
14.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.1
°C/W
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.5 Electrical Characteristics
5 V < VVS < 40 V; −40°C < TJ < 150°C, unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OPERATING VOLTAGE
VVS(nom)
Nominal operating voltage
VVS(uvr)
Undervoltage turnon
VVS rises up
VVS(uvf)
Undervoltage shutdown
VVS falls down
V(uv,hys)
Undervoltage shutdown, hysteresis
40
V
3.5
4
3.7
4
V
3
3.2
3.4
V
0.5
V
OPERATING CURRENT
Nominal operating current (1)
I(op)
I(off)
Standby current
VVS = 13.5 V, VINx = 5 V, VDIAG_EN = 0 V, IOUTx = 0.5 A,
current limit = 2 A, all channels on
8
mA
VVS = 13.5 V, VINx = VDIAG_EN = VCS = VCL = VOUTx =
THER = 0 V,
TJ = 25°C
0.5
VVS = 13.5 V, VINx = VDIAG_EN = VCS = VCL = VOUTx =
THER = 0 V,
TJ = 125°C
5
5
mA
15
ms
3
µA
I(off,diag)
Standby current with diagnostic
enabled
VVS = 13.5 V, VINx = 0 V, VDIAG_EN = 5 V, VVS – VOUTx >
V(ol,off), not in open-load mode
t(off,diag)
Standby mode deglitch time (1)
IN from high to low, if deglitch time > t(off,deg), the device
enters into standby mode.
Ilkg(out)
Output leakage current in off-state
VVS = 13.5 V, VINx = VDIAG_EN = VOUTx = 0
µA
10
12.5
POWER STAGE
rDS(on)
On-state resistance (1)
ICL(int)
Internal current limit
ICL(TSD)
Current limit during thermal
shutdown (1)
VDS(clamp)
Drain-to-source internal clamp voltage
(1)
VVS ≥ 3.5 V, TJ = 25°C
165
VVS ≥ 3.5 V, TJ = 150°C
Internal current limit value, CL pin connected to GND
280
8
Internal current limit value under thermal shutdown
14
6.5
External current limit value under thermal shutdown. The
percentage of the external current limit setting value
mΩ
A
A
70%
50
70
V
Value specified by design, not subject to production test
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Electrical Characteristics (continued)
5 V < VVS < 40 V; −40°C < TJ < 150°C, unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.3
0.7
0.9
UNIT
OUTPUT DIODE CHARACTERISTICS
VF
IN = 0, IOUTx = −0.15 A.
Drain−source diode voltage
t < 60 s, VINx = 0 V, TJ = 25°C, single channel reversed,
short-to-battery condition
Continuous reverse current from
source to drain (1)
IR(1), IR(2)
V
2.5
A
t < 60 s, VINx = 0 V, GND pin 1-kΩ resistor in parallel with
diode. TJ = 25°C. Reverse-polarity condition, all channels
reversed
2
LOGIC INPUT (INx, DIAG_EN, SEL, SEH, THER)
VIH
Logic high-level voltage
VIL
Logic low-level voltage
R(logic,pd)
2
V
0.8
Logic-pin pulldown resistor
INx, SEL, SEH, THER, VINx = VSEL = VSEH = VTHER = 5 V
100
175
250
DIAG_EN. VVS = VDIAG_EN = 5 V
200
275
350
V
kΩ
DIAGNOSTICS
Ilkg(GND_loss)
Output leakage current under GND
loss condition
V(ol,off)
Open-load detection threshold
td(ol,off)
Open-load detection threshold deglitch IN = 0 V, when VVS – VOUTx < V(ol,off) , duration longer than
time (see Figure 3)
t(ol,off), then open load is detected, off state
I(ol,off)
Off-state output sink current
VINx = 0 V, VDIAG_EN = 5 V, VVS = VOUTx = 13.5 V, TJ =
125°C, open load
VOL(STx)
Status low-output voltage
ISTx = 2 mA, version A only
0.2
V
VOL(FAULT)
Fault low-output voltage
IFAULT = 2 mA, version B only
0.2
V
tCL(deg)
Deglitch time when current limit
occurs (1)
VINx = VDIAG_EN = 5 V, the deglitch time from current limit
toggling to FAULT, STx, CS report.
180
µs
IN = 0 V, when VVS – VOUTx < t(ol,off), duration longer than
t(ol,off), then open load is detected, off state
(1)
T(SD)
Thermal shutdown threshold
T(SD,rst)
Thermal shutdown status reset
threshold (1)
T(SW)
Thermal swing shutdown threshold
T(hys)
Hysteresis for resetting the thermal
shutdown or thermal swing (1)
1.6
300
550
100
µA
2.6
V
800
µs
–75
µA
80
160
(1)
175
°C
155
°C
60
°C
10
°C
CURRENT SENSE (Version B) AND CURRENT LIMIT
K(CS)
Current-sense ratio
K(CL)
Current-limit ratio
VCL(th)
Current limit internal threshold (1)
dK(CS) /
K(CS)
Current-sense accuracy, (ICS × K(CS) –
IOUTx) /IOUTx × 100
dK(CL) / K(CL)
External current limit accuracy (2)
(IOUTx – ICL × K(CL)) × 100 / (ICL × K(CL))
300
2500
0.8
–65%
65%
VVS = 13.5 V, IOUTx ≥ 25 mA
–15%
15%
VVS = 13.5 V, IOUTx ≥ 50 mA
–8%
8%
VVS = 13.5 V, IOUTx ≥ 100 mA
–4%
4%
VVS = 13.5 V, IOUTx ≥ 0.5 A
–3%
3%
VVS = 13.5 V, I(limit) ≥ 0.25 A
–20%
20%
VVS = 13.5 V, 0.5 A ≤ I(limit) ≤ 7 A
–15%
15%
VVS ≥ 6.5 V
0
4
5 V ≤ VVS < 6.5 V
0
VVS –
2.5
VVS ≥ 6.5 V, VCS(lin) ≤ 4 V
0
2.5
5 V ≤ VVS < 6.5 V, VCS(lin) ≤ VVS – 2.5 V
0
2.5
4.5
6.5
V
Min(VVS – 2,
4.5)
6.5
V
VCS(lin)
Current-sense voltage linear range (1)
IOUTx(lin)
Output-current linear range (1)
VCS(H)
Current sense pin output voltage
ICS(H)
Current-sense pin output current
VCS = 4.5 V, VVS = 13.5 V
Ilkg(CS)
Current-sense leakage current in
disabled mode
VDIAG_EN = 0 V, TJ =125ºC
VVS ≥ 7 V, fault mode
(2)
8
V
VVS = 13.5 V, IOUTx ≥ 5 mA
5 V ≤ VVS < 7 V, fault mode
15
V
A
mA
0.5
µA
External current limit accuracy is only applicable to overload conditions greater than 1.5 x the current limit setting
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7.6 Switching Characteristics
MIN
TYP
MAX
td(on)
Delay time, VOUTx 10% after VINx↑ (See
Figure 1.)
PARAMETER
VVS = 13.5 V, VDIAG_EN = 5 V, IOUTx = 0.5 A, IN rising
edge to 10% of VOUTx
TEST CONDITIONS
UNIT
20
50
90
µs
td(off)
Delay time, VOUTx 90% after VINx↓ (See
Figure 1.)
VVS = 13.5 V, VDIAG_EN = 5 V, IOUTx = 0.5 A, IN falling
edge to 90% of VOUTx
20
50
90
µs
dV/dt(on)
Turnon slew rate
VVS = 13.5 V, VDIAG_EN = 5 V, IOUTx = 0.5 A, VOUTx from
10% to 90%
0.1
0.3
0.55
V/µs
dV/dt(off)
Turnoff slew rate
VVS = 13.5 V, VDIAG_EN = 5 V, IOUTx = 0.5 A, VOUTx from
90% to 10%
0.1
0.3
0.55
V/µs
td(match)
td(rise) – td(fall) (See Figure 1.)
VVS = 13.5 V, IL = 0.5A. td, rise is the IN rising edge to
VOUTx = 90%.
td(fall) is the IN falling edge to VOUTx = 10%.
–50
50
µs
CURRENT-SENSE CHARACTERISTICS (See Figure 2.)
tCS(off1)
CS settling time from DIAG_EN disabled (1)
VVS = 13.5 V, VINx = 5 V, IOUTx = 0.5 A. current limit = 2 A.
DIAG_EN falling edge to 10% of VCS.
20
µs
tCS(on1)
CS settling time from DIAG_EN enabled (1)
VVS = 13.5 V, VINx = 5 V, IOUTx = 0.5 A. current limit is 2
A. DIAG_EN rising edge to 90% of VCS.
20
µs
tCS(off2)
CS settling time from IN falling edge
VVS = 13.5 V, VDIAG_EN = 5 V, IOUTx = 0.5 A. current limit =
2 A. IN falling edge to 10% of VCS
30
100
µs
tCS(on2)
CS settling time from IN rising edge
VVS = 13.5 V, VDIAG_EN = 5 V, IOUTx = 0.5 A. current limit =
2 A. IN rising edge to 90% of VCS
50
150
µs
tSEx
Multi-sense transition delay from channel to
channel
VDIAG_EN = 5 V, current sense output delay when multisense pins SEL and SEH transition from channel to
channel
50
µs
(1)
Value specified by design, not subject to production test
V INx
90%
90%
dV/dt(off)
dV/dt(on)
VOUTx
10%
10%
td(on)
td(off)
td(fall)
td(rise)
Figure 1. Output Delay Characteristics
VINx
IOUTx
VDIAG_EN
VCS
tCS(on2)
tCS(off1)
tCS(on1)
tCS(off2)
Figure 2. CS Delay Characteristics
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Open Load
VINx
VCS(H)
VCS
td(ol,off)
VSTx,VFAULT
td(ol,off)
Figure 3. Open-Load Blanking-Time Characteristics
SEH
SEL
tSEx
VCS
VCS(CH 2)
VCS(CH 1)
Figure 4. Multi-Sense Transition Delay
10
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1.6
1.7
1.5
1.6
IN1 High
IN1 Low
IN2 High
IN2 Low
1.4
1.3
DIAG_EN Voltage (V)
INx Voltage (V)
7.7 Typical Characteristics
IN3 High
IN3 Low
IN4 High
IN4 Low
1.2
1.1
1
-40
1.5
1.4
1.3
1.2
1.1
-20
0
20
40
60
80
100
Ambient Temperature (qC)
120
1
-40
140
Figure 5. INx Voltage Threshold
120
140
D002
OUT`1
OUT2
OUT3
OUT4
0.75
Diode Voltage (V)
SEx Voltage (V)
20
40
60
80
100
Ambient Temperature (qC)
Figure 6. DIAG_EN Voltage Threshold
1.3
SEx High
SEx Low
1.2
1.1
0.7
0.65
0.6
0.55
-20
0
20
40
60
80
100
Ambient Temperature (qC)
120
0.5
-40
140
-20
0
D003
Figure 7. SEx Voltage Threshold
20
40
60
80
100
Ambient Temperature (qC)
120
140
D004
Figure 8. Body-Diode Forward Voltage
0.3
0.25
On-Resistance (:)
Clamp Voltagge (V)
0
0.8
1.4
64
63.5
63
62.5
62
61.5
61
60.5
60
59.5
59
58.5
58
57.5
-40
-20
D001
1.5
1
-40
DIAG_EN High
DIAG_EN Low
Ch 1
Ch 2
Ch 3
Ch 4
-20
0
20
40
60
80
100
Ambient Temperature (qC)
120
Figure 9. Drain-to-Source Clamp Voltage
0.2
0.15
0.1
3.5 V
13.5 V
40 V
0.05
140
0
-40
-20
D005
0
20
40
60
80
100
Ambient Temperature (qC)
120
140
D006
Figure 10. Channel-1 FET On-Resistance
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0.3
0.3
0.25
0.25
On-Resistance (:)
On-Resistance (:)
Typical Characteristics (continued)
0.2
0.15
0.1
3.5 V
13.5 V
40 V
0.05
0
-40
-20
0
20
40
60
80
100
Ambient Temperature (qC)
120
0.2
0.15
0.1
0
-40
140
Figure 11. Channel-2 FET On-Resistanc
16
Current Sense Ratio (%)
0.26
On-Resistance (:)
0.24
0.22
0.2
0.18
0.16
3.5 V
13.5 V
40 V
-20
0
20
40
60
80
100
Ambient Temperature (qC)
140
D008
120
Ch 1
Ch 2
Ch 3
Ch 4
10
8
6
4
2
140
-20
0
D009
20
40
60
80
100
Ambient Temperature (ºC)
120
140
D010
Figure 14. Current-Sense Ratio at 5 mA
1
Ch 1
Ch 2
Ch 3
Ch 4
2
Ch 1
Ch 2
0.8
Current Sense Ratio (%)
2.25
Current Sense Ratio (%)
120
12
Figure 13. Channel-4 FET On-Resistanc
1.75
1.5
1.25
1
0.75
0.5
Ch 3
Ch 4
0.6
0.4
0.2
0
-0.2
-0.4
0.25
-20
0
20
40
60
80
100
Ambient Temperature (qC)
120
Figure 15. Current-Sense Ratio at 25 mA
12
20
40
60
80
100
Ambient Temperature (qC)
14
0
-40
2.5
0
-40
0
Figure 12. Channel-3 FET On-Resistanc
18
0.12
-40
-20
D007
0.28
0.14
3.5 V
13.5 V
40 V
0.05
140
-0.6
-40
-20
D011
0
20
40
60
80
100
Ambient Temperature (qC)
120
140
D012
Figure 16. Current-Sense Ratio at 50 mA
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Typical Characteristics (continued)
1
0.6
0.5
Current Sense Ratio (%)
Current Sense Ratio (%)
0.8
1
Ch 1
Ch 2
Ch 3
Ch 4
0.4
0.2
0
-0.2
-0.4
-0.6
Ch 1
Ch 2
Ch 3
Ch 4
0
-0.5
-1
-1.5
-0.8
-1
-40
-20
0
20
40
60
80
100
Ambient Temperature (qC)
120
140
-2
-40
-20
0
D013
Figure 17. Current-Sense Ratio at 100 mA
20
40
60
80
100
Ambient Temperature (qC)
120
140
D014
Figure 18. Current-Sense Ratio at 500 mA
1.5
Current Sense Ratio (%)
1
0.5
Ch 1
Ch 2
Ch 3
Ch 4
0
-0.5
-1
-1.5
-2
-40
-20
0
20
40
60
80
100
Ambient Temperature (qC)
120
140
D015
Figure 19. Current-Sense Ratio at 1 A
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8 Detailed Description
8.1 Overview
The TPS4H160-Q1 device is a smart high-side switch, with internal charge pump and quad-channel integrated
NMOS power FETs. Full diagnostics and high-accuracy current-sense features enable intelligent control of the
load. The adjustable current-limit function greatly improves the reliability of whole system. The device has two
versions with different diagnostic reporting, the open-drain digital output (version A) and the current-sense analog
output (version B).
For version A, the device implements the digital fault report with an open-drain structure. When a fault occurs,
the device pulls STx down to GND. A 3.3- or 5-V external pullup is required to match the microcontroller supply
level. The digital status of each channel can report individually, or globally by connecting the STx pins together.
For version B, high-accuracy current sense makes the diagnostics more accurate without further calibration. One
integrated current mirror can source 1 / K(CS) of the load current. The mirrored current flows into the CS-pin
resistor to become a voltage signal. K(CS) is a constant value across temperature and supply voltage. A wide
linear region from 0 V to 4 V allows a better real-time load-current monitoring. The CS pin can also report a fault
with pullup voltage of VCS(H).
The external high-accuracy current limit allows setting the current-limit value by applications. When overcurrent
occurs, the device improves system reliability by clamping the inrush current effectively. The device can also
save system cost by reducing the size of PCB traces and connectors, and the capacity of the preceding power
stage. Besides, the device also implements an internal current limit with a fixed value.
For inductive loads (relays, solenoids, valves), the device implements an active clamp between drain and source
to protect itself. During the inductive switching-off cycle, both the energy of the power supply and the load are
dissipated on the high-side switch. The device also optimizes the switching-off slew rate when the clamp is
active, which helps the system design by keeping the effects of transient power and EMI to a minimum.
The TPS4H160-Q1 device is a smart high-side switch for a wide variety of resistive, inductive, and capacitive
loads, including low-wattage bulbs, LEDs, relays, solenoids, heaters, and sub-modules.
14
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8.2 Functional Block Diagram
Internal LDO
Internal Reference
Auxiliary Charge Pump
Temperature Sensor
VS
Output
Clamp
Gate Driver
and
Charge Pump
INx
OUT1
Protection
and
Diagnostics
Oscillator
OUT2
THER
OUT3
CS
Current-Sense
Mux
Current Sense
OUT4
SEH
SEL
ESD
Protection
Current Limit
CL
FAULT
Current Limit
Reference
2
DIAG_EN
GND
STx
Diagnosis
4
Temperature
Sensor
OTP
8.3 Feature Description
8.3.1 Pin Current and Voltage Conventions
For reference purposes throughout the data sheet, current directions on their respective pins are as shown by
the arrows in Figure 20. All voltages are measured relative to the ground plane.
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Feature Description (continued)
Ivs
VS
VINx
VSTx,
VFAULT
VDIAG_EN
Vvs
IINx
INx
ISTx,
IFAULT
STX,
FAULT
IDIAG_EN
IOUTx
DIAG_EN
VOUTx
OUTx
VCL
VCS
VTHER
ICL
CL
ICS
CS
ITHER
THER
ISEx
SEx
VSEx
GND
IGND
VGND
Ground Plane
Figure 20. Voltage and Current Conventions
8.3.2 Accurate Current Sense
High-accuracy current sense is implemented in the version-B device. It allows a better real-time monitoring effect
and more-accurate diagnostics without further calibration.
One integrated current mirror can source 1 / K(CS) of the load current, and the mirrored current flows into the
external current sense resistor to become a voltage signal. The current mirror is shared by the four channels.
K(CS) is the ratio of the output current and the sense current. It is a constant value across the temperature and
supply voltage. Each device is calibrated accurately during production, so post-calibration is not required. See
Figure 21 for more details.
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Feature Description (continued)
VBAT
VS
IOUT/K(CS)
IOUT
VCS(H)
FAULT
4x
OUTx
CS
R(CS)
Figure 21. Current-Sense Block Diagram
When a fault occurs, the CS pin also works as a fault report with a pullup voltage, VCS(H). See Figure 22 for more
details.
V CS
VCS(H)
VCS(lin)
Fault Report
Current Monitor
I OUTx
Normal Operating
On-State: Current Limit, The rmal Fault
Off-State: Open Load or Short to Batte r y
or Reverse Polarity
Figure 22. Current-Sense Output-Voltage Curve
Use Equation 1 to calculate R(CS).
VCS ´ K (CS)
V
R (CS) = CS =
I CS
I OUTx
(1)
Take the following points into consideration when calculating R(CS).
• Ensure VCS is within the current-sense linear region (VCS, IOUTx(lin)) across the full range of the load current.
Check R(CS) with Equation 2.
VCS(lin)
V
R (CS) = CS £
I CS
I CS
(2)
•
In fault mode, ensure ICS is within the source capacity of the CS pin (ICS(H)). Check R(CS) with Equation 3.
VCS(H,min)
V
R (CS) = CS ³
I CS
I CS(H,min)
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Feature Description (continued)
8.3.3 Adjustable Current Limit
A high-accuracy current limit allows high reliability of the design. It protects the load and the power supply from
overstressing during short-circuit-to-GND or power-up conditions. The current limit can also save system cost by
reducing the size of PCB traces and connectors, and the capacity of the preceding power stage.
When a current-limit threshold is hit, a closed loop activates immediately. The output current is clamped at the
set value, and a fault is reported out. The device heats up due to the high power dissipation on the power FET. If
thermal shutdown occurs, the current limit is set to ICL(TSD) to reduce the power dissipation on the power FET.
See Figure 23 for more details.
The device has two current-limit thresholds.
• Internal current limit – The internal current limit is fixed at ICL(int). Tie the CL pin directly to the device GND for
large-transient-current applications.
• External adjustable current limit – An external resistor is used to set the current-limit threashold. Use the
Equation 4 to calculate the R(CL). VCL(th) is the internal band-gap voltage. K(CL) is the ratio of the output current
and the current-limit set value. It is constant across the temperature and supply voltage. The external
adjustable current limit allows the flexibility to set the current limit value by applications.
I OUT
VCL(th)
I CL =
=
R(CL)
K (CL)
R(CL) =
VCL(th) ´ K (CL)
I OUT
(4)
VBAT
VS
IOUT/K(CL)
±
Internal Current Limit
+
±
VCL(th)
+
IOUT
+
4x
OUT
External Current Limit
±
VCL(th)
+
CL
Figure 23. Current-Limit Block Diargam
18
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Feature Description (continued)
Note that if using a GND network which causes a level shift between the device GND and board GND, the CL
pin must be connected with device GND.
For better protection from a hard short-to-GND condition (when the INx pins are enabled, a short to GND occurs
suddenly), the device implements a fast-trip protection to turn off the related channel before the current-limit
closed loop is set up. The fast-trip response time is less than 1 μs, typically. With this fast response, the device
can achieve better inrush current-suppression performance.
8.3.4 Inductive-Load Switching-Off Clamp
When switching an inductive load off, the inductive reactance tends to pull the output voltage negative. Excessive
negative voltage could cause the power FET to break down. To protect the power FET, an internal clamp
between drain and source is implemented, namely VDS(clamp).
VDS(clamp) = VVS - VOUT
(5)
During the period of demagnetization (tdecay), the power FET is turned on for inductance-energy dissipation. The
total energy is dissipated in the high-side switch. Total energy includes the energy of the power supply (E(VS))
and the energy of the load (E(load)). If resistance is in series with inductance, some of the load energy is
dissipated on the resistance.
E (HSS) = E (VS) + E (load) = E(VS) + E(L) - E(R)
(6)
When an inductive load switches off, E(HSS) causes high thermal stressing on the device.. The upper limit of the
power dissipation depends on the device intrinsic capacity, ambient temperature, and board dissipation condition.
VBAT
VDS(clamp)
IN
L
±
OUT
R
GND
+
Figure 24. Drain-to-Source Clamping Structure
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Feature Description (continued)
IN
VVS
VOUT
VDS(clamp)
E(HSS)
IOUT
t(decay)
Figure 25. Inductive Load Switching-Off Diagram
From the perspective of the high-side switch, E(HSS) equals the integration value during the demagnetization
period.
E(HSS) =
ò
t(decay )
VDS(clamp) ´ I OUT (t)dt
0
t(decay) =
æ R ´ I OUT(max) + VOUT
L
´ ln ç
ç
R
VOUT
è
E(HSS) = L ´
VVS + VOUT
R2
ö
÷
÷
ø
é
æ R ´ I OUT(max) + VOUT
´ êR ´ I OUT(max) - VOUT ln ç
ç
VOUT
êë
è
öù
÷ú
÷ú
øû
(7)
When R approximately equals 0, E(HSD) can be given simply as:
E (HSS) =
VVS + VOUT
1
2
´ L ´ I OUT(max
)
2
VOUT
(8)
Figure 26 is a waveform of the device driving an inductive load, and Figure 27 is waveform with an expanded
time scale. Channel 1 is the IN signal, channel 2 is the supply voltage VVS, channel 3 is the output voltage VOUT,
channel 4 is the output current IOUT, and channel M is the measured power dissipation E(HSS).
On the waveform, the duration of VOUT from VVS to (VVS – VDS(clamp)) is around 120 µs. The device also optimizes
the switching-off slew rate when the clamp is active. This optimization can help the system design by keeping the
effects of transient power and EMI to a minimum. As shown in Figure 26 and Figure 27, the controlled slew rate
is around 0.5 V/µs.
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Feature Description (continued)
Figure 26. Inductive Load Switching-Off Waveform
Figure 27. Inductive Load Switching-Off Expanded
Waveform
Note that for PWM-controlled inductive loads, it is recommended to add the external freewheeling circuitry shown
in Figure 28 to protect the device from repetitive power stressing. TVS is used to achieve the fast decay. See
Figure 28 for more details.
VS
Output
Clamp
OUTx
GND
D
L
TVS
Figure 28. Protection With External Circuitry
8.3.5 Fault Detection and Reporting
8.3.5.1 Diagnostic Enable Function
The DIAG_EN pin enables or disables the diagnostic functions. If multiple devices are used, but the ADC
resource is limited in the microcontroller, the MCU can use GPIOs to set DIAG_EN high to enable the
diagnostics of one device while disabling the diagnostics of the other devices by setting DIAG_EN low. In
addition, the device can keep the power consumption to a minimum by setting DIAG_EN and INx low.
8.3.5.2 Multiplexing of Current Sense
For version B, SEL and SEH are two pins to multiplex the shared current-sense function among the four
channels. See Table 1 for more details.
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Feature Description (continued)
Table 1. Diagnosis Configuration Table
DIAG_EN
L
H
INx
SEH
SEL
CS ACTIVATED
CHANNEL
CS, FAULT, STx
—
—
—
High impedance
0
0
Channel 1
0
1
Channel 2
1
0
Channel 3
1
1
Channel 4
H
L
—
PROTECTIONS AND DIAGNOSTICS
Diagnostics disabled, full protection
Diagnostics disabled, no protection
See Table 2
See Table 2
8.3.5.3 Fault Table
Table 2 applies when the DIAG_EN pin is enabled.
Table 2. Fault Table
CONDITIONS
STx
CS
FAULT
(VER. A) (VER. B) (VER. B)
INx
OUTx
THER
CRITERION
L
L
—
—
H
0
H
—
H
H
—
—
H
In linear
region
H
—
Overlaod, short to ground
H
L
—
Current limit
triggered
L
VCS(H)
L
Auto
Open load (1), short to battery,
reverse polarity
L
H
—
VVS – VOUTx <
V(ol,off)
L
VCS(H)
L
Auto
L
Output auto-retry. Fault
recovers when TJ < T(SD,rst) or
when INx toggles.
Normal
L
Thermal shutdown
H
—
TSD triggered
L
VCS(H)
Output latch off. Fault recovers
when INx toggles.
H
Thermal swing
(1)
H
—
—
FAULT RECOVERY
TSW triggered
L
VCS(H)
L
Auto
An external pullup is required for open-load detection.
8.3.5.4 STx and FAULT Reporting
For version A, four individual STx pins report the fault conditions, each pin for its respective channel. When a
fault condition occurs, it pulls STx down to GND. A 3.3- or 5-V external pullup is required to match the supply
level of the microcontroller. The digital status of each channel can be reported individually, or globally by
connecting all the STx pins together.
For version B, a global FAULT pin is used to monitor the global fault condition among all the channels. When a
fault condition occurs on any channel, the FAULT pin is pulled down to GND. A 3.3-V or 5-V external pullup is
required to match the supply level of the microcontroller.
After the FAULT report, the microcontroller can check and identify the channel in fault status by multiplexed
current sensing. The CS pin also works as a fault report with an internal pullup voltage, VCS(H).
8.3.6 Full Diagnostics
8.3.6.1 Short-to-GND and Overload Detection
When a channel is on, a short to GND or overload condition causes overcurrent. If the overcurrent triggers either
the internal or external current-limit threshold, the fault condition is reported out. The microcontroller can handle
the overcurrent by turning off the switch. The device heats up if no actions are taken. If a thermal shutdown
occurs, the current limit is ICL(TSD) to keep the power stressing on the power FET to a minimum. The device
automatically recovers when the fault condition is removed.
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8.3.6.2 Open-Load Detection
8.3.6.2.1 Channel On
When a channel on, benefiting from the high-accuracy current sense in a small current range, if an open-load
event occurs, it can be detected as an ultralow VCS and handled by the microcontroller. Note that the detection is
not reported on the STx or FAULT pins. The microcontroller must multiplex the SEL and SEH pins to detect the
channel-on open-load fault proactively.
8.3.6.2.2 Channel Off
When a channel is off, if a load is connected, the output is pulled down to GND. But if an open load occurs, the
output voltage is close to the supply voltage (VVS – VOUTx < V(ol,off)), and the fault is reported out.
There is always a leakage current I(ol,off) present on the output due to internal logic control path or external
humidity, corrosion, and so forth. Thus, TI recommends an external pullup resistor to offset the leakage current
when an open load is detected. The recommended pullup resistance is 20 kΩ.
VBAT
Open-Load Detection in Off State
V(ol,off)
R(PU)
VDS
Load
Figure 29. Open-Load Detection in Off-State
8.3.6.3 Short-to-Battery Detection
Short-to-battery has the same detection mechanism and behavior as open-load detection, in both the on-state
and off-state. See Table 2 for more details.
In the on-state, reverse current flows through the FET instead of the body diode, leading to less power
dissipation. Thus, the worst case occurs in the off-state.
• If VOUTx – VVS < V(F) (body diode forward voltage), no reverse current occurs.
• If VOUTx – VVS > V(F), reverse current occurs. The current must be limited to less than IR(1). Setting an INx pin
high can minimize the power stress on its channel. Also, for external reverse protection, see Reverse-Current
Protection for more details.
8.3.6.4 Reverse Polarity Detection
Reverse polarity detection has the same detection mechanism and behavior as open-load detection both in the
on-state and off-state. See Table 2 for more details.
In the on-state, the reverse current flows through the FET instead of the body diode, leading to less power
dissipation. Thus, the worst case occurs in the off-state. The reverse current must be limited to less than IR(2).
Set the related INx pin high to keep the power dissipation to a minimum. For external reverse-blocking circuitry,
see Reverse-Current Protection for more details.
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8.3.6.5 Thermal Fault Detection
To protect the device in severe power stressing cases, the device implements two types of thermal fault
detection, absolute temperature protection (thermal shutdown) and dynamic temperature protection (thermal
swing). Respective temperature sensors are integrated close to each power FET, so the thermal fault is reported
by each channel. This arrangement can help the device keep the cross-channel effect to a minimum when some
channels are in a thermal fault condition.
8.3.6.5.1 Thermal Shutdown
Thermal shutdown is active when the absolute temperature TJ > T(SD). When thefrmal shutdown occurs, the
respective output turns off. The THER pin is used to configure the behavior after the thermal shutdown occurs.
• When the THER pin is low, thermal shutdown operates in the auto-retry mode. The output automatically
recovers when TJ < T(SD) – T(hys), but the current is limited to ICL(TSD) to avoid repetitive thermal shutdown. The
thermal shutdown fault signal is cleared when TJ < T(SD,rst) or after toggling the related INx pin.
• When the THER pin is high, thermal shutdown operates in the latch mode. The output latches off when
thermal shutdown occurs. When the THER pin goes from high to low, thermal shutdown changes to auto-retry
mode. The thermal shutdown fault signal is cleared after toggling the related INx pin.
Thermal swing activates when the power FET temperature is increasing sharply, that is, when ΔT = T(FET) –
T(Logic) > T(sw), then the output turns off. The output automatically recovers and the fault signal clears when ΔT =
T(FET) – T(Logic) < T(sw) – T(hys). Thermal swing function improves the device reliability when subjected to repetitive
fast thermal variation. As shown in Figure 30, multiple thermal swings are triggered before thermal shutdown
occurs.
Thermal Behavior After Short to GND
V THER
V INx
T(SD)
T(SD,rst)
T(hys)
TJ
T(hys)
T(SW)
ICL
IOUTx
ICL(TSD)
VCS(H)
VCS
VFAULT
or VST
Figure 30. Thermal Behavior Diagram
24
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8.3.7 Full Protections
8.3.7.1 UVLO Protection
The device monitors the supply voltage VVS, to prevent unpredicted behaviors when VVS is too low. When VVS
falls down to VVS(uvf), the device shuts down. When VVS rises up to VVS(uvr), the device turns on.
8.3.7.2 Loss-of-GND Protection
When loss of GND occurs, output is shut down regardless of whether the INx pin is high or low. The device can
protect against two ground-loss conditions, loss of device GND and loss of module GND.
8.3.7.3
Protection for Loss of Power Supply
When loss of supply occurs, the output is shut down regardless of whether the INx pin is high or low. For a
resistive or a capacitive load, loss of supply has no risk. But for a charged inductive load, the current is driven
from all the I/O pinss to maintain the inductance current. To protect the system in this condition, TI recommends
two types of external protections: the GND network or the external free-wheeling diode.
VBAT
VS
I/Os
MCU
High-Side Switch
OUT
L
Figure 31. Protection for Loss of Power Supply, Method 1
VBAT
VS
I/Os
MCU
High-Side Switch
OUT
L
Figure 32. Protection for Loss of Power Supply, Method 2
8.3.7.4 Reverse-Current Protection
Reverse current occurs in two conditions: short to battery and reverse polarity.
• When a short to the battery occurs, there is only reverse current through the body diode. IR(1) specifies the
limit of the reverse current.
• In a reverse-polarity condition, there are reverse currents through the body diode and the device GND pin.
IR(2) specifies the limit of the reverse current. The GND pin maximum current is specified in the Absolute
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Maximum Ratings.
To protect the device, TI recommends two types of external circuitry.
• Adding a blocking diode. Both the IC and load are protected when in reverse polarity.
VBAT
VS
´
´
OUT
Load
Copyright © 2016, Texas Instruments Incorporated
Figure 33. Reverse-Current External Protection, Method 1
•
Adding a GND network. The reverse current through the device GND is blocked. The reverse current through
the FET is limited by the load itself. TI recommends a resistor in parallel with the diode as a GND network.
The recommended selection are 1-kΩ resistor in parallel with an >100-mA diode. If multiple high-side
switches are used, the resistor and diode can be shared among devices. The reverse current protection diode
in the GND network forward voltage should be less than 0.6 V in any circumstances. In addition a minimum
resistance of 4.7 K is recommended on the I/O pins.
VBAT
VS
OUT
Load
Figure 34. Reverse-Current External Protection, Method 2
8.3.7.5 MCU I/O Protection
In some severe conditions, such as the ISO7637-2 test or the loss of battery with inductive loads, a negative
pulse occurs on the GND pin This pulse can cause damage on the connected microcontroller. TI recommends
serial resistors to protect the microcontroller, for example, 4.7-kΩ when using a 3.3-V microcontroller and 10-kΩ
for a 5-V microcontroller.
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VBAT
I/Os
MCU
VS
High-Side Switch
OUT
Load
Figure 35. MCU I/O External Protection
8.4 Device Functional Modes
8.4.1 Working Modes
The device has three working modes, the normal mode, the standby mode, and the standby mode with
diagnostics.
Note that IN must be low for t > t(off,deg) to enter the standby mode, where t(off,deg) is the standby mode deglitch
time used to avoid false triggering. Figure 36 shows a working-mode diagram.
Standby Mode
(INx Low, DIAG Low)
DIAG_EN Low to High
DIAG_EN Low
AND
INx High to Low
for
t > t(off,deg)
DIAG_EN High to Low
INx Low to High
Standby Mode
With Diagnostics
(INx Low, DIAG High)
INx low to high
DIAG_EN High
AND
INx High to Low
for
t > t(off,deg)
Normal Mode
(INx High)
Figure 36. Working Modes
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS4H160-Q1 device is capable of driving a wide variety of resistive, inductive, and capacitive loads,
including the low-wattage bulbs, LEDs, relays, solenoids, heaters, and sub-modules. Full diagnostics and highaccuracy current-sense features enable intelligent control of the load. An external adjustable current limit
improves the reliability of the whole system by clamping the inrush or overload current.
9.2 Typical Application
The following figure shows an example of the external circuitry connections based on the version-B device.
VBAT
VS
R(ser)
IN1, 2, 3, 4
OUT1
LED Strings,
Small Power Bulbs
OUT2
Solenoids, Valves, Relays
OUT3
Power-Module:
Cameras, Sensors, Displays
OUT4
General Resistive, Capacitive,
Inductive Loads
R(ser)
DIAG_EN
R(ser)
SEH
MCU
R(ser)
SEL
5V
R(pu)
R(ser)
FAULT
CS
CL
R(CS)
GND
THER
R(CL)
Figure 37. Typical Application Diagram
9.2.1 Design Requirements
•
•
•
•
•
•
28
VVS range from 9 V to 16 V
Load range is from 0.1 A to 1 A for each channel
Current sense for fault monitoring
Expected current-limit value of 2.5 A
Automatic recovery mode when thermal shutdown occurs
Full diagnostics with 5-V MCU
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Typical Application (continued)
•
Reverse-voltage protection with a blocking diode in the power-supply line
9.2.2 Detailed Design Procedure
To keep the 1-A nominal current in the 0 to 4-V current-sense range, calculate the R(CS) resistor using
Equation 9. To achieve better current-sense accuracy, a 1% tolerance or better resistor is preferred.
VCS ´ K (CS) 4 ´ 300
V
R (CS) = CS =
=
= 1200 W
I CS
I OUT
1
(9)
To set the adjustable current limit value at 2.5-A, calculate R(CL) using Equation 10.
VCL(th) ´ K (CL) 0.8 ´ 2500
R (CL) =
=
= 800 W
I OUT
2.5
(10)
TI recommends R(ser) = 10 kΩ for 5-V MCU, and R(pu) = 10 kΩ as the pullup resistor.
9.2.3 Application Curves
Figure 38 shows a test example of soft-start when driving a big capacitive load. Figure 39 shows an expanded
waveform of the output current.
Overcurrent Is Clamped
at the Set Value of 1 A.
VS = 12 V
Load current = 0.4
A
CH2 = FAULT
INx = ↑
CL = 2.3 mF
Current limit = 1 A
CH1 = INx
CH3 = output
voltage
CH4 = output
current
Figure 38. Driving a Capacitive Load With Adjustable
Current Limit
VVS = 12 V
Load current = 0.4
A
CH2 = FAULT
INx = ↑
CL = 2.3 mF
Current limit = 1 A
CH1 = INx
CH3 = output
voltage
CH4 = output
current
Figure 39. Driving a Capacitive Load, Expanded Waveform
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Typical Application (continued)
Figure 40 shows a test example of PWM-mode driving. Figure 41 shows the expanded waveform of the rising
edge. Figure 42 shows the expanded waveform of the falling edge.
VVS = 13.5 V
CH2 = CS voltage
INx = 200-Hz PWM
at 50% duty cycle
CH3 = output
voltage
CH1 = INx signal
VVS = 13.5 V
CH4 = output
current
CH2 = CS voltage
Figure 40. PWM Signal Driving
VVS = 13.5 V
CH2 = CS voltage
INx = 200-Hz PWM
at 50% duty cycle
CH3 = output
voltage
CH1 = INx signal
CH4 = output
current
Figure 41. Expanded Waveform of Rising Edge
INx = 200-Hz PWM at 50% duty cycle
CH3 = output voltage
CH1 = INx signal
CH4 = output current
Figure 42. Expanded Waveform of Falling Edge
10 Power Supply Recommendations
The device is qualified for both automotive and industrial applications. The normal power supply connection is a
12-V automotive system or 24-V industrial system. Detailed supply voltage should be within the range specified
in the Recommended Operating Conditions.
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11 Layout
11.1 Layout Guidelines
To prevent thermal shutdown, TJ must be less than 150°C. The HTSSOP package has good thermal impedance.
However, the PCB layout is very important. Good PCB design can optimize heat transfer, which is absolutely
essential for the long-term reliability of the device.
• Maximize the copper coverage on the PCB to increase the thermal conductivity of the board. The major heat
flow path from the package to the ambient is through the copper on the PCB. Maximum copper is extremely
important when there are not any heat sinks attached to the PCB on the other side of the package.
• Add as many thermal vias as possible directly under the package ground pad to optimize the thermal
conductivity of the board.
• All thermal vias should either be plated shut or plugged and capped on both sides of the board to prevent
solder voids. To ensure reliability and performance, the solder coverage should be at least 85%.
11.2 Layout Examples
11.2.1 Without a GND Network
Without a GND network, tie the thermal pad directly to the board GND copper for better thermal performance.
GND
1
28
OUT1
2
27
OUT1
3
26
OUT2
4
25
OUT2
5
24
6
7
8
GND
Thermal
PAD
(GND)
23
VS
22
VS
21
VS
9
20
VS
10
19
11
18
OUT3
12
17
OUT3
13
16
OUT4
14
15
OUT4
Figure 43. Layout Example Without a GND Network
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Layout Examples (continued)
11.2.2 With a GND Network
With a GND network, tie the thermal pad as one trace to the board GND copper.
GND Network
GND
1
28
OUT1
2
27
OUT1
3
26
OUT2
4
25
OUT2
5
24
6
23
VS
22
VS
21
VS
9
20
VS
10
19
11
18
OUT3
12
17
OUT3
13
16
OUT4
14
15
OUT4
7
8
GND
Thermal
Pad
(GND)
Figure 44. Layout Example With a GND Network
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.2 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated device. This data is subject to change without notice and without
revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS4H160AQPWPRQ1
ACTIVE
HTSSOP
PWP
28
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
4H160AQ
TPS4H160BQPWPRQ1
ACTIVE
HTSSOP
PWP
28
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
4H160BQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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