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TPS53125
SLVS947C – OCTOBER 2009 – REVISED AUGUST 2014
TPS53125 Dual Synchronous Step-Down Controller for Low Voltage Power Rails
1 Features
3 Description
•
The TPS53125 is a dual, adaptive on-time D-CAP2™
mode synchronous buck controller. The part enables
system designers to cost effectively complete the
suite of various end equipment's power bus
regulators with a low external component count and
low standby consumption. The main control loop for
the TPS53125 uses the D-CAP™ Mode topology
which provides a very fast transient response with no
external component.
1
•
•
•
•
•
•
•
•
•
•
•
•
D-CAP2™ Mode Control
– Fast Transient Response
– No External Parts Required for Loop
Compensation
– Compatible With Ceramic Output Capacitors
High Initial Reference Accuracy (±1%)
Low Output Ripple
Wide Input Voltage Range: 4.5 V to 24 V
Output Voltage Range: 0.76 V to 5.5 V
Low-Side RDS(ON) Loss-Less Current Sensing
Adaptive Gate Drivers with Integrated Boost Diode
Adjustable Soft Start
Non-Sinking Pre-Biased Soft Start
350-kHz Switching Frequency
Cycle-by-Cycle Over-Current Limiting Control
30-mV to 300-mV OCP Threshold Voltage
Thermally Compensated OCP by 4000 ppm/°C at
ITRIP
2 Applications
•
The TPS53125 also has a proprietary circuit that
enables the device to adapt not only low equivalent
series resistance (ESR) output capacitors such as
POSCAP/SP-CAP, but also ceramic capacitor. The
part provides a convenient and efficient operation
with conversion voltages from 4.5 V to 24 V and
output voltage from 0.76 V to 5.5 V.
The TPS53125 is available in 24-pin RGE and PW
packages, and is specified from –40°C to 85°C
ambient temperature range.
Device Information(1)
DEVICE NAME
TPS53125
Point-of-Load Regulation in Low Power Systems
for Wide Range of Applications
– Digital TV Power Supply
– Networking Home Terminal
– Digital Set-Top Box (STB)
– DVD Player/Recorder
– Gaming Consoles
PACKAGE
BODY SIZE
VQFN (24)
4 mm x 4 mm
TSSOP (24)
4.4 mm x 7.8 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
4 Simplified Schematics
Input Voltage
4.5 V to 24 V
C9
10 µF
C10
4700 pF
R5
R4
10 kΩ
3.52 kΩ
PGND
1
SS1
GND
VFB1
VO1
VO2
VFB2
2
13 kΩ
8
VBST2
9
DRVH2
10
SW2
11
DRVL2
DRVL1 20
12
PGND2
PGND1 19
VBST1 23
Power PAD
TPS53125 RGE
(QFN )
13
14
R6
4.3 k Ω
17
18
C7
4.7µF
C11
4700 pF
Q1
FDS8878
L1
SPM6530T
1.5 µH
VO1
1.8 V/4A
Q2
FDS8690
C1
22 µFx 4
R３
3.3 kΩ
PGND
1
DRVH1
SW1 24
2
VBST1
DRVL1 23
R1
13 kΩ
3
EN1
PGND1 22
4
VO1
TRIP1 21
5
VFB1
Q2
FDS8878
C1
22 µFx4
R3
3.3 kΩ
PGND
Input Voltage
R2
13 kΩ
R5
10 kΩ
C10
SGND 4700 pF
VIN 20
VREG5 19
6
GND
7
SS1
8
VFB2
9
VO2
TRIP2 16
10 EN2
PGND2 15
TPS53125PW
TSSOP24
V5FILT 18
SS2 17
C7
4.7 µF
SGND
11 VBST2
DRVL2 14
12 DRVH2
SW2 13
4.5 V to 24 V
C9
10 µF
C8
1 µF
PGND
C11
4700 pF
PGND
R4
3.52 kΩ
C3
10 µF
VO1
1.8 V/4A
C3
10 µF
SW1 21
16
C８
1µF
C2
0.1µF
DRVH1 22
15
L1
SPM 6530T
1.5 µH
C2
0.1 µF
EN1 24
EN2
TRIP1
C4
22 µFx4
3
VIN
Q4
FDS8690
SGND
Q1
FDS8878
4
V5FILT
C5
0.1µF
5
VREG5
VO2
1.05V/4A
7
6
SS2
C6
10 µF
Q3
FDS8878
L2
SPM6530T
1.5 µH
R2
10 kΩ
R1
TRIP2
PGND
R6
4.3 kΩ
SGND
Q4
FDS8690
C5
0.1 µF
L2
SPM6530T
1.5 µH
Q3
FDS8878
PGND
C4
22 µFx4
VO2
1.05 V/4A
C6
10 µF
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS53125
SLVS947C – OCTOBER 2009 – REVISED AUGUST 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematics...........................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
4
4
4
5
5
7
Absolute Maximum Ratings ......................................
Handling Ratings.......................................................
Recommended Operating Conditions.......................
Thermal Information .................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
8.1 Overview .................................................................. 8
8.2 Functional Block Diagrams ....................................... 8
8.3 Feature Description................................................... 9
8.4 Device Functional Modes ....................................... 11
9
Application and Implementation ........................ 12
9.1 Application Information .......................................... 12
9.2 Typical Application ................................................. 12
9.3 Typical Application Circuit, TSSOP......................... 19
10 Power Supply Recommendations ..................... 20
11 Layout................................................................... 21
11.1 Layout Suggestions............................................... 21
11.2 Layout Example ................................................... 22
12 Device and Documentation Support ................. 23
12.1 Trademarks ........................................................... 23
12.2 Electrostatic Discharge Caution ............................ 23
12.3 Glossary ................................................................ 23
13 Mechanical, Packaging, and Orderable
Information ........................................................... 23
5 Revision History
Changes from Revision B (January 2010) to Revision C
Page
•
Changed revision from B-January 2010 to C-May 2014, also copied all text, tables and graphics to new data sheet
template .................................................................................................................................................................................. 1
•
Added V(ESD) value ................................................................................................................................................................. 4
•
Changed VREG5 row, Min column from 4.8 to 4.6 in ELEC CHARA table, ......................................................................... 5
•
Changed Changed the RDRVL MAX value for –100 mA From: 8 Ω To 12 Ω........................................................................... 5
•
Changed the I(SSC) Min value From: -1.5 to -2.5 μA and the Max value From: -2.5 To: -1.5 μA ....................................... 6
•
Added Application Curves section ....................................................................................................................................... 19
2
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Copyright © 2009–2014, Texas Instruments Incorporated
TPS53125
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SLVS947C – OCTOBER 2009 – REVISED AUGUST 2014
6 Pin Configuration and Functions
PGND1
DRVL1
DRVH1
VBST1
EN1
VO1
VFB1
GND
19
SW1
TSSOP PACKAGE
(TOP VIEW)
20
22
21
DRVH1
VBST1
23
24
EN1
QFN PACKAGE
(TOP VIEW)
VO1
1
18
TRIP1
VFB1
2
17
VIN
GND
3
16
VREG5
10
11
12
PGND2
13
TRIP2
DRVL2
6
9
VO2
SW2
SS 2
DRVH2
14
8
V5 FILT
VBST2
15
5
7
4
EN2
SS1
VFB2
SS1
VFB2
VO2
EN2
VBST2
DRVH2
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
SW1
DRVL1
PGND1
TRIP1
VIN
VREG5
V5FILT
SS2
TRIP2
PGND2
DRVL2
SW2
Pin Functions
PIN
NAME
QFN
24
TSSOP
24
I/O
VBST1, VBST2
23, 8
2, 11
I
Supply input for high-side NFET driver. Bypass to SWx with a high-quality 0.1-μF
ceramic capacitor. An external Schottky diode can be added from VREG5 if forward
drop is critical to drive the high-side FET.
EN1, EN2
24, 7
3, 10
I
Enable. Pull High to enable SMPS.
VO1, VO2
1, 6
4, 9
I
Output voltage inputs for on-time adjustment and output discharge. Connect directly to
the output voltage.
VFB1, VFB2
2, 5
5, 8
I
D-CAP2 feedback inputs. Connect to output voltage with resistor divider.
3
6
I
Signal ground pin. Connect to PGND1, PGND2 and system ground at a single point.
DRVH1, DRVH2
22, 9
1, 12
O
High-side N-Channel MOSFET gate driver outputs. SWx referenced drivers switch
between SWx (OFF) and VBSTx (ON).
SW1, SW2
21, 10
24, 13
I/O
Switch node connections for both the high-side drivers and the over current
comparators.
DRVL1, DRVL2
20, 11
23, 14
O
Low-side N-Channel MOSFET gate driver outputs. PGND referenced drivers switch
between PGNDx (OFF) and VREG5 (ON).
PGND1, PGND2
19, 12
22, 15
I/O
Power ground connections for both the low-side drivers and the over current
comparators. Connect PGND1, PGND2 and GND strongly together near the IC.
TRIP1, TRIP2
18, 13
21, 16
I
Over current threshold programming pin. Connect to GND with a resistor to GND to set
threshold for low-side RDS(ON) current limit.
VIN
17
20
I
Supply Input for 5-V linear regulator. Bypass to GND with a minimum high-quality 0.1-μF
ceramic capacitor.
V5FILT
15
18
I
5-V supply input for the entire control circuitry except the MOSFET drivers. Bypass to
GND with a minimum high-quality 1.0-μF ceramic capacitor. V5FILT is connected to
VREG5 via an internal 10-Ω resistor.
VREG5
16
19
O
Output of 5-V linear regulator and supply for MOSFET drivers. Bypass to GND with a
minimum high-quality 4.7-μF ceramic capacitor. VREG5 is connected to V5FILT via an
internal 10-Ω resistor.
4,14
7, 17
O
Soft-start programming pin. Connect capacitor from SSx pin to GND to program softstart time.
GND
SS1, SS2
Copyright © 2009–2014, Texas Instruments Incorporated
DESCRIPTION
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SLVS947C – OCTOBER 2009 – REVISED AUGUST 2014
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
VI
Input voltage
(1)
MIN
MAX
VIN, EN1, EN2
–0.3
26
VBST1, VBST2
–0.3
32
VBST1 - SW1, VBST2 - SW2
–0.3
6
V5FILT, VFB1, VFB2, TRIP1, TRIP2, VO1, VO2
–0.3
6
SW1, SW2
–2
26
DRVH1, DRVH2
–1
32
DRVH1 - SW1, DRVH2 - SW2
–0.3
6
DRVL1, DRVL2, VREG5, SS1, SS2
–0.3
6
PGND1, PGND2
–0.3
0.3
UNIT
V
VO
Output voltage
TA
Operating ambient temperature
–40
85
°C
TJ
Junction temperature
–40
150
°C
(1)
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 Handling Ratings
Tstg
V(ESD)
Electrostatic discharge
(1)
(2)
MIN
MAX
UNIT
–55
150
°C
Human body model (HBM), per AN/ESDA/JEDEC JS-001, all
pins (1)
–2000
2000
V
Charged device model (CDM), per JEDeC specification
JESD22-C101, all pins (2)
–500
500
V
Storage temperature range
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VIN
VI
VO
Supply input voltage
Input voltage
Output voltage
MIN
MAX
VIN
4.5
24
V5FILT
4.5
5.5
VBST1, VBST2
–0.1
30
VBST1 - SW1, VBST2 - SW2
–0.1
5.5
VFB1, VFB2, VO1, VO2
–0.1
5.5
TRIP1, TRIP2
–0.1
0.3
EN1, EN2
–0.1
24
SW1, SW2
–1.8
24
DRVH1, DRVH2
–0.1
30
VBST1 - SW1, VBST2 - SW2
–0.1
5.5
DRVL1, DRVL2, VREG5, SS1, SS2
–0.1
5.5
PGND1, PGND2
–0.1
0.1
UNIT
V
V
V
TA
Operating free-air temperature
–40
85
°C
TJ
Operating junction temperature
–40
125
°C
4
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TPS53125
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SLVS947C – OCTOBER 2009 – REVISED AUGUST 2014
7.4 Thermal Information
TPS53125
THERMAL METRIC (1)
PW 24 PINS
RGE 24 PINS
RθJA
Junction-to-ambient thermal resistance
88.9
35.4
RθJC(top)
Junction-to-case (top) thermal resistance
26.5
39.1
RθJB
Junction-to-board thermal resistance
43.5
13.6
ψJT
Junction-to-top characterization parameter
1.1
0.5
ψJB
Junction-to-board characterization parameter
43.0
13.6
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
3.8
(1)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
450
800
μA
30
60
μA
1
%
765
775
SUPPLY CURRENT
IIN
VIN supply current
VIN current, TA = 25°C, VREG5 tied to V5FILT,
EN1 = EN2 = 5 V, VFB1 = VFB2 = 0.8 V,
SW1 = SW2 = 0.5 V
IVINSDN
VIN shutdown current
VIN current, TA = 25°C, no load,
EN1 = EN2 = 0 V, VREG5 = ON
VFB VOLTAGE AND DISCHARGE RESISTANCE
VBG
Bandgap initial regulation accuracy
TA = 25°C
–1
TA = 25°C, SWinj = OFF
VVFBTHx
VFBx threshold voltage
755
TA = 0°C to 70°C, SWinj = OFF (1)
TA= -40°C to 85°C, SWinj = OFF
(1)
IVFB
VFB input current
VFBx = 0.8 V, TA = 25°C
RDischg
VO discharge resistancee
ENx = 0 V, VOx = 0.5 V, TA = 25°C
753.5
776.5
752
–100
mV
778
–10
100
nA
40
80
Ω
5.0
5.2
V
20
mV
40
mV
VREG5 OUTPUT
VVREG5
VREG5 output voltage
TA = 25°C, 5.5 V < VIN < 24 V,
0 < IVREG5 < 10 mA
VLN5
Line regulation
5.5 V < VIN < 24 V, IVREG5 = 10 mA
VLD5
Load regulation
1 mA < IVREG5 < 10 mA
IVREG5
Output current
VIN = 5.5 V, VREG5 = 4.0 V, TA = 25°C
170
Source, IDRVHx = –100 mA
5.5
11
Sink, IDRVHx = 100 mA
2.5
5
Source, IDRVLx = –100 mA
4
12
Sink, IDRVLx = 100 mA
2
4
4.6
mA
OUTPUT: N-CHANNEL MOSFET GATE DRIVERS
RDRVH
DRVH resistance
RDRVL
DRVL resistance
TD
Dead time
DRVHx-low to DRVLx-on
20
50
80
DRVLx-low to DRVHx-on
20
40
80
0.7
Ω
Ω
ns
INTERNAL BOOST DIODE
VFBST
Forward voltage
VVREG5-VBSTx, IF = 10 mA, TA = 25°C
0.8
0.9
V
IVBSTLK
VBST leakage current
VBSTx = 29 V, SWx = 24 V, TA = 25°C
0.1
1
μA
ON-TIME TIMER CONTROL
TON1L
CH1 on time
SW1 = 12 V, VO1 = 1.8 V
490
ns
TON2L
CH2 on time
SW2 = 12 V, VO2 = 1.8 V
390
ns
TOFF1L
CH1 min off time
SW1 = 0.7 V, TA = 25°C, VFB1 = 0.7 V
285
ns
TOFF2L
CH2 min off time
SW2 = 0.7 V, TA = 25°C, VFB2 = 0.7 V
285
ns
(1)
Not production tested - ensured by design.
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
–2.5
–2
–1.5
UNIT
SOFT START
ISSC
SS1/SS2 charge current
VSS1/VSS2 = 0 V, TA = 25°C
TCISSC
ISSC temperature coefficient
On the basis of 25°C (1)
ISSD
SS1/SS2 discharge current
VSS1/VSS2 = 0.5 V
100
150
Wake up
3.7
4.0
4.3
Hysteresis
0.2
0.3
0.4
2.0
–4
3
μA
nA/°C
μA
UVLO
VUV5VFILT
V5FILT UVLO threshold
V
LOGIC THRESHOLD
VENH
ENx high-level input voltage
EN 1/2
VENL
ENx low-level input voltage
EN 1/2
V
0.3
V
CURRENT SENSE
ITRIP
TRIP source current
VTRIPx = 0.1 V, TA = 25°C
TCITRIP
ITRIP temperature coefficient
On the basis of 25°C
VOCLoff
OCP compensation offset
VRtrip
Current limit threshold setting range
8.5
10
11.5
4000
μA
ppm/°C
(VTRIPx-GND-VPGNDx-SWx) voltage,
VTRIPx-GND = 60 mV, TA = 25°C
–15
(VTRIPx-GND-VPGNDx-SWx) voltage,
VTRIPx-GND = 60 mV
–20
20
30
300
mV
120
%
VTRIPx-GND voltage
0
15
mV
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
VOVP
Output OVP trip threshold
TOVPDEL
Output OVP prop delay
VUVP
Output UVP trip threshold
TUVPDEL
Output UVP delay
TUVPEN
Output UVP enable delay
OVP detect
110
UVP detect
65
115
μs
1.5
Hysteresis (recover < 20 μs)
UVP enable delay / soft-start time
70
75
10
%
17
30
40
μs
x1.4
x1.7
x2.0
ms
THERMAL SHUTDOWN
TSDN
6
Thermal shutdown threshold
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Shutdown temperature
Hysteresis
(1)
(1)
150
20
°C
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TPS53125
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SLVS947C – OCTOBER 2009 – REVISED AUGUST 2014
600
60
500
50
Shutdown Current (µA)
Supply Current (µA)
7.6 Typical Characteristics
400
300
200
100
0
–50
40
30
20
10
0
50
100
Junction Temperature (°C)
0
-50
150
0
50
100
Junction Temperature (°C)
150
VREG5 = ON
Figure 1. VIN Supply Current vs Junction Temperature
Figure 2. VIN Shutdown Current vs Junction Temperature
5.07
20
5.06
VREG5 Voltage (V)
Source Current (µA)
15
10
5
5.05
5.04
5.03
5.02
5.01
0
–50
0
50
100
Junction Temperature (°C)
5.00
–50
150
Figure 3. Trip Source Current vs Junction Temperature
0
50
Temperature (°C)
100
150
Figure 4. REG5 Voltage vs Junction Temperature
5.5
VREG5 Voltage (V)
5.3
5.1
4.9
4.7
4.5
0
5
10
15
Input Voltage (V)
20
25
Figure 5. VREG5 Voltage vs Input Voltage
Copyright © 2009–2014, Texas Instruments Incorporated
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8 Detailed Description
8.1 Overview
The TPS53125 is a dual, adaptive on-time D-CAP2™ mode synchronous buck controller. The part enables
system designers to cost effectively complete the suite of various end equipment's power bus regulators with a
low external component count and low standby consumption. The main control loop for the TPS53125 uses the
D-CAP™ Mode topology which provides a very fast transient response with no external component.
The TPS53125 also has a proprietary circuit that enables the device to adapt not only low equivalent series
resistance (ESR) output capacitors such as POSCAP/SP-CAP, but also ceramic capacitor. The part provides a
convenient and efficient operation with conversion voltages from 4.5 V to 24 V and output voltage from 0.76 V to
5.5 V.
8.2 Functional Block Diagrams
VREG5
4V/3.7V
V50K
THOK
TSD
VSFILT
VO1
VO2
VBST1
VBST2
Ref
BGR
Ref
Switcher Controller
SW2
Sdn
Sdn
DRVL2
SS2
DRVL1
Fault
SS1
Fault
ON1
SW1
PGND1
DRVH2
Switcher Controller
ON2
DRVH1
PGND2
8
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TRIP2
VFB2
SS2
GND
EN2
EN1
SS1
VFB1
TRIP1
EN/SS Control
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SLVS947C – OCTOBER 2009 – REVISED AUGUST 2014
Functional Block Diagrams (continued)
–30%
UV
V5FILT
GND
OV
+15%
Ref
SSx
ERR
COMP
V50K
VFBx
IصA
VREG5
GND
Control Logic
VBSTx
TRIPx
OCP
DRVHx
LL
1 Shot
SWx
PGNDx
XCON
VREG5
DRVLx
PGNDx
LLx
VOx
VOx
PGNDx
ENx
On/Off time
Minimun On/Off
OVP/UVP,
Discharge
Control
Fault
Sdn
8.3 Feature Description
8.3.1 PWM Operation
The main control loop of the TPS53125 is an adaptive on-time pulse width modulation (PWM) controller using a
proprietary D-CAP2™ mode control. D-CAP2™ mode control combines constant on-time control with an internal
compensation circuit for pseudo-fixed frequency and low external component count configuration with both low
ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.
At the beginning of each cycle, the synchronous high-side MOSFET is turned on. After an internal one-shot timer
expires, this MOSFET is turned off. When the feedback voltage falls below the reference voltage, the one-shot
timer is reset and the high-side MOSFET is turned back on. The one shot is set by the converter input voltage
VIN, and the output voltage VO, to maintain a pseudo-fixed frequency over the input voltage range. An internal
ramp is added to the reference voltage to simulate output ripple, eliminating the need for ESR induced output
ripple from D-CAP mode control.
8.3.2 Drivers
Each channel of the TPS53125 contains two high-current resistive MOSFET gate drivers. The low-side driver is a
PGND referenced, VREG5 powered driver designed to drive the gate of a high-current, low RDS(ON) N-channel
MOSFET whose source is connected to PGND. The high-side driver is a floating SWx referenced VBST powered
driver designed to drive the gate of a high-current, low RDS(ON) N-channel MOSFET. To maintain the VBST
voltage during the high-side driver ON time, a capacitor is placed from SWx to VBSTx. Each driver draws
average current equal to gate charge (Qg at Vgs = 5 V) times switching frequency (fSW).
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Feature Description (continued)
To prevent cross-conduction, there is a narrow dead-time when both high-side and low-side drivers are OFF
between each driver transition. During this time the inductor current is carried by one of the MOSFETs body
diodes.
8.3.3 PWM Frequency and Adaptive On-Time Control
TPS53125 employs adaptive on-time control scheme and does not have a dedicated on board oscillator.
TPS53125 runs with pseudo-constant frequency by using the input voltage and output voltage to set the on-time
one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the output voltage.
Therefore, when the duty ratio is VOUT/VIN, the frequency is constant.
8.3.4 5-Volt Regulator
The TPS53125 has an internal 5-V low-dropout (LDO) regulator to provide a regulated voltage for all both drivers
and the IC's internal logic. A high-quality 4.7-μF or greater ceramic capacitor from VREG5 to GND is required to
stabilize the internal regulator. An internal 10-Ω resistor from VREG5 filters the regulator output to the IC's
analog and logic input voltage, V5FILT. An additional high-quality 1.0-μF ceramic capacitor is required from
V5FILT to GND to filter switching noise from VREG5.
8.3.5 Soft Start
The TPS53125 has a programmable soft-start . When the ENx pin becomes high, 2.0-μA current begins charging
the capacitor connected from the SS pin to GND. The internal reference for the D-CAP2™ mode control
comparator is overridden by the soft-start voltage until the soft-start voltage is greater than the internal reference
for smooth control of the output voltage during start up.
8.3.6 Pre-Bias Support
The TPS53125 supports pre-bias start-up without sinking current from the output capacitor. When enabled, the
low-side driver is held off until the soft-start commands a voltage higher than the pre-bias level (internal soft-start
becomes greater than feedback voltage (VFB)), then the TPS53125 slowly activates synchronous rectification by
limiting the first DRVL pulses with a narrow on-time. This limited on-time is then incremented on a cycle-by-cycle
basis until it coincides with the full 1-D off-time. This scheme prevents the initial sinking of current from the prebias output, and ensure that the output voltage (VOUT) starts and ramps up smoothly into regulation and the
control loop is given time to transition from pre-biased start-up to normal mode operation.
8.3.7 Output Discharge Control
TPS53125 discharges the outputs when ENx is low, or the controller is turned off by the protection functions
(OVP, UVP, UVLO, and thermal shutdown). The device discharges output using an internal 40-Ω MOSFET which
is connected to VOx and PGNDx. The external low-side MOSFET is not turned on during the output discharge
operation to avoid the possibility of causing negative voltage at the output. This discharge ensures that on start
the regulated voltage always initializes from 0 V.
8.3.8 Over Current Limit
TPS53125 has cycle-by-cycle over current limit feature. The over current limits the inductor valley current by
monitoring the voltage drop across the low-side MOSFET RDS(ON) during the low-side driver on-time. If the
inductor current is larger than the over current limit (OCL), the TPS53125 delays the start of the next switching
cycle until the sensed inductor current falls below the OCL current. MOSFET RDS(ON) current sensing is used to
provide an accuracy and cost effective solution without external devices. To program the OCL, the TRIP pin
should be connected to GND through a trip voltage setting resistor, according to the following equations.
æ
(VIN - VO ) VO ö
VTRIP = ç IOCL ´
÷ ´ RDS(ON)
ç
2 ´ L1´ ƒSW VIN ÷ø
è
RTRIP (kW) =
10
(1)
VTRIP (mV )
ITRIP (mA)
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Feature Description (continued)
The trip voltage should be between 30 mV to 300 mV over all operational temperature, including the
4000-ppm/°C temperature slope compensation for the temperature dependency of the RDS(ON).
If the load current exceeds the over current limit, the voltage will begin to drop. If the over current conditions
continues the output voltage will fall below the under voltage protection threshold and the TPS53125 will shut
down.
In an over current condition, the current to the load exceeds the current to the output capacitor; thus the output
voltage tends to fall off. Eventually, it will end up with crossing the under voltage protection threshold and
shutdown.
8.3.9 Over/Under Voltage Protection
TPS53125 monitors a resistor divided feedback voltage to detect over and under voltage. If the feedback voltage
is higher than 115% of the reference voltage, the OVP comparator output goes high and the circuit latches the
high-side MOSFET driver OFF and the low-side MOSFET driver ON.
When the feedback voltage is lower than 70% of the reference voltage, the UVP comparator output goes high
and an internal UVP delay counter begins counting. After 30 μs, TPS53125 latches OFF both top and bottom
MOSFET drivers. This function is enabled approximately 1.7 x TSS after power-on. The OVP and UVP latch off is
reset when EN goes low level.
8.3.10 UVLO Protection
TPS53125 has V5FILT under voltage lock out protection (UVLO) that monitors the voltage of V5FILT pin.
When the V5FILT voltage is lower than UVLO threshold voltage, the device is shut off. All output drivers are OFF
and output discharge is ON. The UVLO is non-latch protection.
8.3.11 Thermal Shutdown
The TPS53125 includes an over temperature protection shut-down feature. If the TPS53125 die temperature
exceeds the OTP threshold (typically 150°C), both the high-side and low-side drivers are shut off, the output
voltage discharge function is enabled and then the device is shut off until the die temperature drops. Thermal
shutdown is a non-latch protection.
8.4 Device Functional Modes
The TPS53125 has two operating modes. The TPS53125 is in shut down mode when the EN1 and EN2 pins are
low. When the EN1 and EN2 pins is pulled high, the TPS53125 enters the normal operating mode.
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9 Application and Implementation
9.1 Application Information
9.2 Typical Application
The TPS53125 is a Dual D-CAP2™ Mode Control Step-Down Controller in a realistic cost-sensitive application.
Providing both a low core-type 1.05 V and I/O type 1.8 V output from a loosely regulated 12 V source. Idea
applications are: Digital TV Power Supply, Networking Home Pin, Digital Set-Top Box (STB), DVD
Player/Recorder, and Gaming Consoles.
Input Voltage
4.5 V to 24 V
C9
10 µF
C10
4700 pF
R5
R4
10 kΩ
3.52 kΩ
9
DRVH2
10
SW2
SGND
13 kΩ
EN1 24
VBST1 23
Power PAD
TPS53125 RGE
(QFN )
12
PGND2
PGND1 19
15
R6
4.3 k Ω
TRIP1
DRVL2
14
16
17
18
C7
4.7µF
C８
1µF
Q1
FDS8878
L1
SPM6530T
1.5 µH
C3
10 µF
SW1 21
DRVL1 20
13
C2
0.1µF
DRVH1 22
11
C4
22 µFx4
PGND
VO1
SS1
VBST2
1
GND
VFB2
EN2
2
VFB1
VO2
7
8
3
VREG5
Q4
FDS8690
4
VIN
C5
0.1µF
5
V5FILT
VO2
1.05V/4A
Q3
FDS8878
L2
SPM6530T
1.5 µH
6
SS2
C6
10 µF
R2
10 kΩ
R1
TRIP2
PGND
VO1
1.8 V/4A
Q2
FDS8690
C1
22 µFx 4
R３
3.3 kΩ
PGND
C11
4700 pF
PGND
SGND
Figure 6. TPS53125 Typical Application Circuit (QFN)
9.2.1 Design Requirements (QFN)
Table 1. Design Parameters
PARAMETERS
EXAMPLE VALUES
Input voltage
12 V
Output voltage
VO1 = 1.8 V, VO2 = 1.05 V
9.2.2 Detailed Design Procedure (QFN)
9.2.2.1 Choose Inductor
The inductance value is selected to provide approximately 30% peak to peak ripple current at maximum load.
Larger ripple current increases output ripple voltage, improve S/N ratio and contribute to stable operation.
Equation 3 can be used to calculate L1.
L1 =
(VIN(MAX) - VO1)´
IL1(RIPPLE) ´ ƒSW
VO 1
VIN(MAX)
=
(VIN(MAX) - VO1)´
0.3 ´ IO 1´ ƒSW
VO 1
VIN(MAX)
(3)
The inductors current ratings needs to support both the RMS (thermal) current and the Peak (saturation) current.
The RMS and peak inductor current can be estimated as follows.
12
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IL1(RIPPLE) =
IL1(PEAK)
(VIN(MAX) - VO1)´
L1´ ƒSW
VO 1
VIN(MAX)
(4)
VTRIP
=
+ IL1(RIPPLE)
RDS(ON)
IL1(RMS) = IO 12 +
1
IL1(RIPPLE)
12
(
(5)
2
)
(6)
Note: The calculation above shall serve as a general reference. To further improve transient response, the output
inductance could be reduced further. This needs to be considered along with the selection of the output
capacitor.
9.2.2.2 Choose Output Capacitor
The capacitor value and ESR determines the amount of output voltage ripple and load transient response. it is
recommended to use a ceramic output capacitor.
IL1(RIPPLE)
1
C1 =
´
8 ´ VO 1(RIPPLE) ƒSW
(7)
C1 =
DIload2 ´ L1
2 ´ VO 1´ DVOS
(8)
2
C1 =
DIload ´ L1
2 ´ K ´ DVUS
(9)
Where
K = (VIN - VO 1)´
Ton 1
Ton 1 + Tmin(off )
(10)
Select the capacitance value greater than the largest value calculated from Equation 7, Equation 8 and
Equation 9. The capacitance for C1 should be greater than 66 μF.
Where
ΔVOS = The allowable amount of overshoot voltage in load transition
ΔVUS = The allowable amount of undershoot voltage in load transition
Tmin(off) = Minimum off time
9.2.2.3 Choose Input Capacitor
The TPS53125 requires an input decoupling capacitor and a bulk capacitor is needed depending on the
application. A minimum 10-μF high-quality ceramic capacitor is recommended for the input capacitor. The
capacitor voltage rating needs to be greater than the maximum input voltage.
9.2.2.4 Choose Bootstrap Capacitor
The TPS53125 requires a bootstrap capacitor from SW to VBST to provide the floating supply for the high-side
drivers. A minimum 0.1-μF high-quality ceramic capacitor is recommended. The voltage rating should be greater
than 10 V.
9.2.2.5 Choose VREG5 and V5FILT Capacitor
The TPS53125 requires both the VREG5 regulator and V5FILT input are bypassed. A minimum 4.7-μF highquality ceramic capacitor must be connected between the VREG5 and GND for proper operation. A minimum 1μF high-quality ceramic capacitor must be connected between the V5FILT and GND for proper operation. Both of
these capacitors’ voltage ratings should be greater than 10 V.
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9.2.2.6 Choose Output Voltage Set Point Resistors
The output voltage is set with a resistor divider from the output voltage node to the VFBx pin. It is recommended
to use 1% tolerance or better resisters. Select R2 between 10 kΩ and 100 kΩ and use Equation 11 or
Equation 12 to calculate R1.
æ 1 ö æ VO 1 ö
Vswinj = (VIN - VO 1´ 0.5875 )´ ç
÷´ç
÷ ´ 4975
è ƒSW ø è VIN ø
(11)
æ
ö
ç
÷
VO 1
- 1÷ ´ R2
R1 = ç
VFB(RIPPLE) + Vswinj
ç
÷
ç VFB +
÷
2
è
ø
(12)
Where
VFB(RIPPLE) = Ripple voltage at VFB
Vswinj = Ripple voltage at error comparator
9.2.2.7 Choose Over Current Set Point Resistor
æ
(VIN - VO ) VO ö
VTRIP = ç IOCL ´
÷ ´ RDS(ON)
ç
2 ´ L1´ ƒSW VIN ÷ø
è
(13)
æ
(VIN - VO ) VO ö
VTRIP = ç IOCL ´
÷ ´ RDS(ON)
ç
2 ´ L1´ ƒSW VIN ÷ø
è
(14)
Where
RDS(ON) = Low side FET on-resistance
ITRIP(min) = TRIP pin source current （8.5 μA）
VOCL0ff = Minimum over current limit offset voltage (–20 mV)
IOCL = Over current limit
9.2.2.8 Choose Soft Start Capacitor
Soft start time equation is as follows.
T ´I
CSS = SS SSC
VFB
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500
500
400
400
Switching Frequency (kHz)
Switching Frequency (kHz)
9.2.3 Application Curves (QFN)
300
200
100
0
300
200
100
0
0
5
10
15
Input Voltage (V)
IO1 = 3 A
VO1 = 1.8 V
20
0
25
5
10
15
Input Voltage (V)
IO2 = 3 A
VO2 = 1.05 V
25
Figure 8. Switching Frequency
vs Input Voltage (CH2)
500
500
400
400
Switching Frequency (kHz)
Switching Frequency (kHz)
Figure 7. Switching Frequency
vs Input Voltage (CH1)
20
300
200
100
0
300
200
100
0
0.0
0.5
1.0
VIN = 12 V
1.5
2.0
2.5
Output Current (A)
3.0
VO1 = 1.8 V
Figure 9. Switching Frequency
vs Output Current (CH1)
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3.5
4.0
0.0
0.5
1.0
VIN = 12 V
1.5
2.0
2.5
Output Current (A)
3.0
3.5
4.0
VO2 = 1.05 V
Figure 10. Switching Frequency
vs Output Current (CH2)
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1.85
1.10
1.84
1.09
1.83
1.08
1.82
1.07
Output Voltage (V)
Output Voltage (V)
SLVS947C – OCTOBER 2009 – REVISED AUGUST 2014
1.81
1.80
1.79
1.78
1.06
1.05
1.04
1.03
1.77
1.02
1.76
1.01
1.75
0.0
0.5
1.0
VIN = 12 V
1.5
2.0
2.5
Output Current (A)
3.0
3.5
1.00
0.0
4.0
VO1 = 1.8 V
0.5
1.0
VIN = 12 V
1.85
1.10
1.84
1.09
1.83
1.08
1.82
1.07
1.81
1.80
1.79
1.78
3.5
4.0
VO2 = 1.05 V
1.06
1.05
1.04
1.03
1.02
1.77
1.01
1.76
1.00
1.75
0
5
VIN = 12 V
10
15
Input Voltage (V)
VO1 = 1.85 V
Figure 13. Output Voltage
vs Input Voltage (CH1)
16
3.0
Figure 12. Output Voltage
vs Output Current (CH2)
Output Voltage (V)
Output Voltage (V)
Figure 11. Output Voltage
vs Output Current (CH1)
1.5
2.0
2.5
Output Current (A)
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20
25
5
10
15
Input Voltage (V)
VIN = 12 V
VO2 = 1.05 V
0
20
25
Figure 14. Output Voltage
vs Input Voltage (CH2)
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Figure 15. Load Transient Response
Figure 16. Load Transient Response
Figure 17. Start-up Waveforms
Figure 18. Start-up Waveforms
80
80
Efficiency (%)
100
Efficiency (%)
100
60
40
20
60
40
20
0
0.0
0.5
1.0
1.5
2.0
2.5
Output Current (A)
3.0
3.5
4.0
VO1 = 1.8 V
Figure 19. 1.8-V Efficiency vs Output Current (CH1)
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0
0.0
0.5
1.0
1.5
2.0
2.5
Output Current (A)
3.0
3.5
4.0
VO2 = 1.05 V
Figure 20. 1.05-V Efficiency vs Output Current (CH2)
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VO1 = 1.8 V
Figure 21. 1.8-V Output Ripple Voltage
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VO2 = 1.05 V
Figure 22. 1.05-V Output Ripple Voltage
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9.3 Typical Application Circuit, TSSOP
The TPS53125 is a Dual D-CAP2™ Mode Control Step-Down Controller in a realistic cost-sensitive application.
Providing both a low core-type 1.05 V and I/O type 1.8V output from a loosely regulated 12 V source.
Q1
FDS8878
L1
SPM 6530T
1.5 µH
C2
0.1 µF
R1
13 kΩ
R4
3.52 kΩ
DRVH1
SW1 24
2
VBST1
DRVL1 23
3
EN1
PGND1 22
4
VO1
TRIP1 21
5
VFB1
6
GND
7
SS1
8
VFB2
9
VO2
VO1
1.8 V/4A
Q2
FDS8878
C1
22 µFx4
R3
3.3 kΩ
PGND
Input Voltage
R2
13 kΩ
R5
10 kΩ
1
C3
10 µF
C10
SGND 4700 pF
VIN 20
TPS53125PW
TSSOP24
VREG5 19
V5FILT 18
SS2 17
C7
4.7 µF
C8
1 µF
PGND2 15
11 VBST2
DRVL2 14
12 DRVH2
SW2 13
PGND
C11
4700 pF
TRIP2 16
10 EN2
4.5 V to 24 V
C9
10 µF
R6
4.3 kΩ
SGND
PGND
C4
22 µFx4
Q4
FDS8690
C5
0.1 µF
L2
SPM6530T
1.5 µH
Q3
FDS8878
VO2
1.05 V/4A
C6
10 µF
Figure 23. TSSOP
9.3.1 Design Requirements
For the Design Requirements, refer to Design Requirements (QFN).
9.3.2 Detailed Design Procedure
For the Detailed Design Procedure, refer to Detailed Design Procedure (QFN).
9.3.3 Application Curves
For Application Curves, refer to Application Curves (QFN).
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10 Power Supply Recommendations
The devices are designed to operate from an input voltage supply range between 4.5 V and 24 V. This input
supply must be well regulated. If the input supply is located more than a few inches from the TPS53125 device
additional 0.1 µF ceramic capacitance may be required in addition to the ceramic bypass capacitors, 10 µF.
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11 Layout
11.1 Layout Suggestions
•
•
•
•
•
•
•
•
•
•
Keep the input switching current loop as small as possible. (VIN ≥ C3 ≥ PNGD ≥ Sync FET ≥ SW ≥ Control
FET)
Place the input capacitor (C3) close to the top switching FET. The output current loop should also be kept as
small as possible.
Keep the SW node as physically small and short as possible as to minimize parasitic capacitance and
inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the
feedback terminal (FBx) of the device.
Keep analog and non-switching components away from switching components.
Make a single point connection from the signal ground to power ground.(1)
Do not allow switching current to flow under the device.
DRVH and DRVL line should not run close to SW node or minimize it. (2)
GND terminals for capacitors of SSx and V5FILT and resistors of feedback and TRIPx should be connected
to SGND. (3)
GND terminals for capacitors of VREG5 and VIN should be connected to PGND. (4)
Signal lines should not run under/near Output Inductor or minimize it. (5)
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11.2 Layout Example
VIN
Q3
Q1
SW2
SW1
C3
C6
Q4
Q2
(4)
C9
(5)
(5)
L1
L2
(3) R6
C8
R3
(3)
C7
TRIP2
TEST2
V5FILT
12 PGND2
C4, 1
16
17
18
TRIP1
15
VREG5
14
VIN
13
PGND1 19
C1, 1
DRVL1 20
11 DRVL2
(QFN )
10 SW2
C4, 2
TPS53125
9 DRVH2
C5
VFB2
TEST1
GND
VFB1
VO1
5
4
3
2
1
TO EN 1
C1, 3
R1
R4
C4, 4
C1, 2
EN1 24
6
R2
R5
VOUT2
C2
VBST1 23
VO2
7 EN2
TO EN 2
DRVH1 22
RGE
Thermal PAD
8 VBST2
C4, 3
SW1 21
PGND
(3)
C1, 4
VOUT1
(1)
Top Side Component or Via
Bottom Side Component
Top Side Etch
Bottom Side Etch
Component Pads Shown in White
SGND
Figure 24.
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12 Device and Documentation Support
12.1 Trademarks
D-CAP2 is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2009–2014, Texas Instruments Incorporated
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS53125PW
ACTIVE
TSSOP
PW
24
60
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TPS53125
TPS53125PWR
ACTIVE
TSSOP
PW
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TPS53125
TPS53125RGER
ACTIVE
VQFN
RGE
24
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
53125
TPS53125RGET
ACTIVE
VQFN
RGE
24
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
53125
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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