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TPS53129
SLVSAE6A – JULY 2010 – REVISED AUGUST 2014
TPS53129 Dual Synchronous Step-Down Controller with Auto-Skip
Eco-mode™ for Low Voltage Power Rails
1 Features
3 Description
•
The TPS53129 is a dual, adaptive on-time D-CAP2™
mode synchronous buck controller. The TPS53129
enables system designers to complete the suite of
various end equipment’s power bus regulators with
cost effective, low component count, and low standby
current solution. The main control loop for the
TPS53129 uses the D-CAP2™ mode control which
provides a very fast transient response with no
external components. The TPS53129 also has a
circuit that enables the device to adapt to both low
equivalent series resistance (ESR) output capacitors
such as POSCAP or SP-CAP, and ultra-low ESR,
ceramic capacitors. The fixed frequency emulated
adaptive on-time control supports seamless operation
between PWM mode at heavy load condition and
reduced frequency operation at light load for high
efficiency down to milliampere range.The device
provides convenient and efficient operation with input
voltages from 4.5 V to 24 V and output voltages from
0.76 V to 5.5 V.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
D-CAP2™ Mode Control
– Fast Transient Response
– No External Parts Required for Loop
Compensation
– Compatible With Ceramic Output Capacitors
High Initial Reference Accuracy (±1%)
Low Output Ripple
Wide Input Voltage Range: 4.5 V to 24 V
Output Voltage Range: 0.76 V to 5.5 V
Low-Side RDS(ON) Loss-Less Current Sensing
Adaptive Gate Drivers with Integrated Boost Diode
Adjustable Soft Start
Non-Sinking Pre-Biased Soft Start
700-kHz Switching Frequency
Cycle-by-Cycle Over-Current Limiting Control
30-mV to 300-mV OCP Threshold Voltage
Thermally Compensated OCP by 4000 ppm/°C at
ITRIP
Auto-Skip Eco-mode™ for High Efficiency at Light
Load
Device Information(1)
2 Applications
•
The TPS53129 is available in 4-mm x 4-mm 24-pin
QFN (RGE) or 24-pin TSSOP (PW) packages, and is
specified from -40°C to 85°C ambient temperature
range.
PART NUMBER
Point-of-Load Regulation in Low Power Systems
for Wide Range of Applications
– Digital TV Power Supply
– Networking Home Terminal
– Digital Set-Top Box (STB)
– DVD Player/Recorder
– Gaming Consoles
PACKAGE
TPS53129
BODY SIZE (NOM)
VQFN (24)
4.00 mm x 4.00 mm
TSSOP (24)
4.40 mm x 7.80 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
4 Simplified Schematics
Input Voltage
4.5V to 24V
C9
10uF
C10
4700pF
C6
10uF
VO2
1.05V/4A
R5
10kΩ
Q3
FDS8878
L2
SPM6530T
1.5uH
C5
0.1uF
7
EN2
8
VBST2
4
3
2
1
SS1
VFB1
VO1
5
GND
6
VO2
R2
10kΩ
VFB2
R4
3.63kΩ
PGND
SGND
R1
13.5kΩ
C2
0.1uF
EN1
9
DRVH2
10
SW2
11
12
24
VBST1 23
Power PAD
C2
0.1uF
DRVH1 22
TPS53129 RGE
SW1
Q1
FDS8878
L1
SPM6530T
1.5uH
21
L1
DRVL2
DRVL1 20
PGND2
PGND1 19
Q2
FDS8690
C3
10uF
VO1
1.8V/4A
PGND
SS2
V5FILT
VREG5
VIN
TRIP1
C4
22uFx2
TRIP2
(QFN )
Q4
FDS8690
13
14
15
16
17
18
R6
4.7kΩ
C7
4.7uF
C８
1uF
R1
13.5k
Ω
R３
4.3kΩ
PGND
R4
3.63kΩ
DRVH1
2
VBST1
3
R2
10kΩ
R5
10kΩ
C1
22uFx2
1
C10
SGND4700pF
SW1
PGND1
22
TRIP1
21
VIN
20
4
VO1
5
VFB1
6
GND
7
SS1
8
VFB2
9
VO2
TRIP2 16
10
EN2
PGND2 15
11
VBST2
DRVL2
14
SW2
13
12
DRVH2
VO1
1.8V/4A
Q2
FDS8690
SGND
C1
22uFx2
R３
4.3kΩ
PGND
Input Voltage
TPS53129PW
TSSOP24
VREG5 19
V5FILT 18
SS2
17
C7
4.7uF
4.5V to 24V
C9
10uF
C８
1uF
PGND
C11
4700pF
R6
4.7kΩ
SGND
PGND
Q4
FDS8690
PGND
C11
4700pF
C3
10uF
24
DRVL1 23
EN1
Q1
FDS8878
L1
SPM6530T
1.5uH
C5
0.1uF
L2
SPM6530T
1.5uH
Q3
FDS8878
C4
22uFx2
C6
10uF
VO2
1.05V/4A
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS53129
SLVSAE6A – JULY 2010 – REVISED AUGUST 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematics...........................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
4
4
4
5
5
6
Absolute Maximum Ratings ......................................
Handling Ratings ......................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics.......................................... 7
Detailed Description .............................................. 8
9.1 Overview .................................................................. 8
9.2 Functional Block Diagrams ....................................... 8
9.3 Feature Description................................................... 9
9.4 Device Functional Modes........................................ 11
10 Application and Implementation........................ 12
10.1 Application Information ........................................ 12
10.2 Typical Application ............................................... 12
11 Power Supply Recommendations ..................... 19
12 Layout................................................................... 20
12.1 Layout Suggestions............................................... 20
12.2 Layout Example ................................................... 20
13 Device and Documentation Support ................. 21
13.1 Trademarks ........................................................... 21
13.2 Electrostatic Discharge Caution ............................ 21
13.3 Glossary ................................................................ 21
14 Mechanical, Packaging, and Orderable
Information ........................................................... 21
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (July 2010) to Revision A
Page
•
Changed format to meet latest data sheet standards; added new sections and moved existing sections............................ 1
•
Added Eco-mode on first page ............................................................................................................................................... 1
•
Added QFN and TSSOP schematics .................................................................................................................................... 1
•
Added V(ESD) value ................................................................................................................................................................. 4
•
Added Thermal Information ................................................................................................................................................... 5
•
Changed min for VVREG5 ......................................................................................................................................................... 5
•
Changed max for RDRVL at -100 mA ....................................................................................................................................... 5
•
Changed the I(SSC) Min value From: -1.44 to -2.56 μA and the Max value From: -2.56 To: -1.44 μA................................. 6
•
Added Timing Requirements table ........................................................................................................................................ 6
•
Added Overview .................................................................................................................................................................... 8
•
Added Device Functional Modes section ............................................................................................................................ 11
•
Added Application Information ............................................................................................................................................. 12
•
Added Design Parameters table .......................................................................................................................................... 13
•
Added Power Supply Recommendations ............................................................................................................................ 19
•
Updated Layout Example .................................................................................................................................................... 20
2
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Copyright © 2010–2014, Texas Instruments Incorporated
TPS53129
www.ti.com
SLVSAE6A – JULY 2010 – REVISED AUGUST 2014
6 Pin Configuration and Functions
PGND1
TSSOP PACKAGE
(TOP VIEW)
DRVH1
VBST1
EN1
VO1
VFB1
GND
19
DRVL1
20
SW1
21
DRVH1
22
VBST1
23
24
EN1
QFN PACKAGE
(TOP VIEW)
VO1
1
18
TRIP1
VFB1
2
17
VIN
GND
3
16
VREG5
10
11
12
PGND2
13
TRIP2
DRVL2
6
9
VO2
SW2
SS 2
DRVH2
14
8
V5 FILT
VBST2
15
5
7
4
EN2
SS1
VFB2
SS1
VFB2
VO2
EN2
VBST2
DRVH2
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
SW1
DRVL1
PGND1
TRIP1
VIN
VREG5
V5FILT
SS2
TRIP2
PGND2
DRVL2
SW2
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
RGE
PW
VBST1,
VBST2
23, 8
2, 11
I
Supply input for high-side NFET driver. Bypass to SWx with a high-quality 0.1-μF
ceramic capacitor. An external schottky diode can be added from VREG5 if
forward drop is critical to drive the high-side FET.
EN1, EN2
24, 7
3, 10
I
Enable. Pull High to enable SMPS.
VO1, VO2
1, 6
4, 9
I
Output voltage inputs for on-time adjustment and output discharge. Connect
directly to the output voltage.
VFB1, VFB2
2, 5
5, 8
I
D-CAP2 feedback inputs. Connect to output voltage with resistor divider.
3
6
I
Signal ground pin. Connect to PGND1, PGND2 and system ground at a single
point.
DRVH1,
DRVH2
22, 9
1, 12
O
High-side N-Channel MOSFET gate driver outputs. SWx referenced drivers
switch between SWx (OFF) and VBSTx (ON).
SW1, SW2
21, 10
24, 13
I/O
Switch node connections for both the high-side drivers and the over current
comparators.
DRVL1,
DRVL2
20, 11
23, 14
O
Low-side N-Channel MOSFET gate driver outputs. PGND referenced drivers
switch between PGNDx (OFF) and VREG5 (ON).
PGND1,
PGND2
19, 12
22, 15
I/O
Power ground connections for both the low-side drivers and the over current
comparators. Connect PGND1, PGND2 and GND strongly together near the IC.
TRIP1,
TRIP2
18, 13
21, 16
I
Over current threshold programming pin. Connect to GND with a resistor to GND
to set threshold for low-side RDS(ON) current limit.
VIN
17
20
I
Supply Input for 5-V linear regulator. Bypass to GND with a minimum high-quality
0.1-μF ceramic capacitor.
V5FILT
15
18
I
5-V supply input for the entire control circuitry except the MOSFET drivers.
Bypass to GND with a minimum high-quality 1.0-μF ceramic capacitor. V5FILT is
connected to VREG5 via an internal 10-Ω resistor.
VREG5
16
19
O
Output of 5-V linear regulator and supply for MOSFET drivers. Bypass to GND
with a minimum high-quality 4.7-μF ceramic capacitor. VREG5 is connected to
V5FILT via an internal 10-Ω resistor.
4,14
7, 17
I
Soft-start programming pin. Connect capacitor from SSx pin to GND to program
soft-start time.
GND
SS1, SS2
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SLVSAE6A – JULY 2010 – REVISED AUGUST 2014
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
VI
Input voltage
(1)
MIN
MAX
VIN, EN1, EN2
-0.3
26
VBST1, VBST2
-0.3
32
VBST1 - SW1, VBST2 - SW2
-0.3
6
V5FILT, VFB1, VFB2, TRIP1, TRIP2,
VO1, VO2
-0.3
6
SW1, SW2
-2
26
DRVH1, DRVH2
-1
32
DRVH1 - SW1, DRVH2 - SW2
-0.3
6
DRVL1, DRVL2, VREG5, SS1, SS2
-0.3
6
PGND1, PGND2
UNIT
V
VO
Output voltage
-0.3
0.3
TA
Operating ambient temperature
-40
85
°C
TJ
Junction temperature
-40
150
°C
(1)
V
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" are not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 Handling Ratings
Tstg
Storage temperature range
V(ESD)
Electrostatic discharge
(1)
(2)
MIN
MAX
UNIT
-55
150
°C
Human body model (HBM), per AN/ESDA/JEDEC JS-001, all
pins (1)
–2000
2000
V
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
–500
500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VIN
VI
VO
Supply input voltage
Input voltage
Output voltage
MIN
MAX
VIN
4.5
24
V5FILT
4.5
5.5
VBST1, VBST2
–0.1
30
VBST1 - SW1, VBST2 - SW2
–0.1
5.5
VFB1, VFB2, VO1, VO2
–0.1
5.5
TRIP1, TRIP2
–0.1
0.3
EN1, EN2
–0.1
24
SW1, SW2
–1.8
24
DRVH1, DRVH2
–0.1
30
VBST1 - SW1, VBST2 - SW2
–0.1
5.5
DRVL1, DRVL2, VREG5, SS1, SS2
–0.1
5.5
PGND1, PGND2
–0.1
0.1
UNIT
V
V
V
TA
Operating free-air temperature
–40
85
°C
TJ
Operating junction temperature
–40
125
°C
4
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TPS53129
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SLVSAE6A – JULY 2010 – REVISED AUGUST 2014
7.4 Thermal Information
TPS53129
THERMAL METRIC (1)
RGE
PW
24 PIN
24 PIN
RθJA
Junction-to-ambient thermal resistance
35.4
88.9
RθJC(top)
Junction-to-case (top) thermal resistance
39.1
26.5
RθJB
Junction-to-board thermal resistance
13.6
43.5
ψJT
Junction-to-top characterization parameter
0.5
1.1
ψJB
Junction-to-board characterization parameter
13.6
43
RθJC(bot)
Junction-to-case (bottom) thermal resistance
3.8
N/A
(1)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
450
800
μA
30
60
μA
1
%
758
768
SUPPLY CURRENT
IIN
VIN supply current
VIN current, TA = 25°C, VREG5 tied
to V5FILT, EN1 = EN2 = 5 V,
VFB1 = VFB2 = 0.8 V,
SW1 = SW2 = 0.5 V
IVINSDN
VIN shutdown current
VIN current, TA = 25°C,
no load , EN1 = EN2 = 0 V,
VREG5 = ON
VFB VOLTAGE AND DISCHARGE RESISTANCE
VBG
Bandgap initial regulation accuracy
TA = 25°C
TA = 25°C, SWinj = OFF
VVFBTHx
VFBx threshold voltage
TA = 0°C to 70°C,
SWinj = OFF (1)
TA = -40°C to 85°C,
SWinj = OFF (1)
IVFB
VFB input current
VFBx = 0.8 V, TA = 25°C
RDischg
VO discharge resistance
ENx = 0 V, VOx = 0.5 V, TA = 25°C
–1
748
746.6
769.4
745
771
–100
mV
–10
100
nA
40
80
Ω
5.0
5.2
V
VREG5 OUTPUT
VVREG5
VREG5 output voltage
TA = 25°C, 5.5 V < VIN < 24 V,
0 < IVREG5 < 10 mA
VLN5
Line regulation
5.5 V < VIN < 24 V, IVREG5 = 10 mA
20
mV
VLD5
Load regulation
1 mA < IVREG5 < 10 mA
40
mV
Output current
VIN = 5.5 V, VREG5 = 4.0 V,
TA = 25°C
IVREG5
4.6
170
mA
OUTPUT: N-CHANNEL MOSFET GATE DRIVERS
RDRVH
DRVH resistance
RDRVL
DRVL resistance
TD
Dead time
Source, IDRVHx = –100 mA
5.5
11
Sink, IDRVHx = 100 mA
2.5
5
Source, IDRVLx = –100 mA
4
12
Sink, IDRVLx = 100 mA
2
4
Ω
Ω
DRVHx-low to DRVLx-on
20
50
80
DRVLx-low to DRVHx-on
20
40
80
0.7
0.8
0.9
V
0.1
1
μA
ns
INTERNAL BOOST DIODE
VFBST
Forward voltage
VVREG5-VBSTx, IF = 10 mA, TA = 25°C
IVBSTLK
VBST leakage current
VBSTx = 29 V, SWx = 24 V,
TA = 25°C
SOFT START
(1)
Not production tested - ensured by design.
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
–2.56
–2
–1.44
ISSC
SS1/SS2 charge current
VSS1/VSS2 = 0 V, TA = 25°C
TCISSC
ISSC temperature coefficient
On the basis of 25°C (1)
–3.3
ISSD
SS1/SS2 discharge current
VSS1/VSS2 = 0.5 V
100
150
V5FILT rising
3.7
4.0
4.3
Hysteresis
0.2
0.3
0.4
2.0
3.3
UNIT
μA
nA/°C
μA
UVLO
VUV5VFILT
V5FILT UVLO threshold
V
LOGIC THRESHOLD
VENH
ENx high-level input voltage
EN 1/2
VENL
ENx low-level input voltage
EN 1/2
V
0.3
V
CURRENT SENSE
ITRIP
TRIP source current
VTRIPx = 0.1 V, TA = 25°C
TCITRIP
ITRIP temperature coefficient
On the basis of 25°C
VOCLoff
OCP compensation offset
8.5
(VTRIPx-GND-VPGNDx-SWx) voltage,
VTRIPx-GND = 60 mV, TA = 25°C
–15
(VTRIPx-GND-VPGNDx-SWx) voltage,
VTRIPx-GND = 60 mV
–20
VZC
Zero cross detection comparator
offset
VPGNDx-LLx voltage
VRtrip
Current limit threshold setting range
VTRIPx-GND voltage
10
11.5
4000
μA
ppm/°C
0
15
mV
20
0.5
mV
30
300
mV
%
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
VOVP
Output OVP trip threshold
VUVP
Output UVP trip threshold
OVP detect
110
115
120
UVP detect
65
70
75
Hysteresis (recover < 20 μs)
10
%
THERMAL SHUTDOWN
TSDN
Thermal shutdown threshold
Shutdown temperature
Hysteresis
(1)
150
(1)
°C
20
7.6 Timing Requirements
MIN
TYP
TON1L
CH1 on time
SW1 = 12 V, VO1 = 1.8 V
165
TON2L
CH2 on time
SW2 = 12 V, VO1 = 1.8 V
140
TOFF1L
CH1 min off time
SW1 = 0.7 V, TA = 25°C, VFB1 = 0.7 V
216
TOFF2L
CH2 min off time
SW2 = 0.7 V, TA = 25°C, VFB2 = 0.7 V
216
TOVPDEL
Output OVP prop
delay
TUVPDEL
Output UVP delay
TUVPEN
Output UVP enable
delay
6
MAX
UNIT
ns
1.5
μs
UVP enable delay / soft-start time
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17
30
40
x1.4
x1.7
x2.0
ms
Copyright © 2010–2014, Texas Instruments Incorporated
TPS53129
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SLVSAE6A – JULY 2010 – REVISED AUGUST 2014
600
60
500
50
Shutdown Current (µA)
Supply Current (µA)
8 Typical Characteristics
400
300
200
100
0
–50
40
30
20
10
0
50
100
Junction Temperature (°C)
0
-50
150
0
50
100
Junction Temperature (°C)
150
VREG5 = ON
Figure 1. VIN Supply Current vs Junction Temperature
Figure 2. VIN Shutdown Current vs Junction Temperature
5.07
20
5.06
VREG5 Voltage (V)
Source Current (µA)
15
10
5
5.05
5.04
5.03
5.02
5.01
0
–50
0
50
100
Junction Temperature (°C)
5.00
–50
150
Figure 3. Trip Source Current vs Junction Temperature
0
50
Temperature (°C)
100
150
Figure 4. REG5 Voltage vs Junction Temperature
5.5
VREG5 Voltage (V)
5.3
5.1
4.9
4.7
4.5
0
5
10
15
Input Voltage (V)
20
25
Figure 5. VREG5 Voltage vs Input Voltage
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9 Detailed Description
9.1 Overview
The TPS53129 is a dual, adaptive on-time D-CAP2™ mode synchronous buck controller. The TPS53129
enables system designers to cost complete the suite of various end equipment power bus regulators with a low
external component count and low standby current consumption. The main control loop for the TPS53129 uses
the D-CAP™ Mode topology, which provides a fast transient response with no external component. The
TPS53129 also has a proprietary circuit that enables the device to adapt to both low equivalent series resistance
(ESR) output capacitors such as POSCAP/SP-CAP, and ceramic capacitors. The fixed frequency emulated
adaptive on-time control supports seamless operation between PWM mode at heavy load condition, and reduced
frequency operation at light load for high efficiency.
9.2 Functional Block Diagrams
VREG5
4V/3.7V
V50K
THOK
TSD
VSFILT
VO1
VO2
VBST1
VBST2
Ref
BGR
Ref
Switcher Controller
SW2
Sdn
Sdn
DRVL2
SS2
DRVL1
Fault
SS1
Fault
ON1
SW1
PGND1
DRVH2
Switcher Controller
ON2
DRVH1
PGND2
8
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TRIP2
VFB2
SS2
GND
EN2
EN1
SS1
VFB1
TRIP1
EN/SS Control
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Functional Block Diagrams (continued)
–30%
UV
V5FILT
GND
OV
+15%
Ref
SSx
ERR
COMP
V50K
VFBx
IصA
VREG5
GND
Control Logic
VBSTx
TRIPx
OCP
DRVHx
LL
1 Shot
SWx
PGNDx
XCON
VREG5
DRVLx
PGNDx
LLx
VOx
VOx
PGNDx
ENx
On/Off time
Minimun On/Off
OVP/UVP,
Discharge
Control
Fault
Sdn
9.3 Feature Description
9.3.1 PWM Operation
The main control loop of the TPS53129 is an adaptive on-time pulse width modulation (PWM) controller using a
proprietary D-CAP2™ mode control. D-CAP2™ mode control combines constant on-time control with an internal
compensation circuit for pseudo-fixed frequency and low external component count configuration with both low
ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.
At the beginning of each cycle, the synchronous high-side MOSFET is turned on. After an internal one-shot timer
expires, this MOSFET is turned off. When the feedback voltage falls below the reference voltage, the one-shot
timer is reset and the high-side MOSFET is turned back on. The one shot is set by the converter input voltage
VIN, and the output voltage VO, to maintain a pseudo-fixed frequency over the input voltage range. An internal
ramp is added to the reference voltage to simulate output ripple, eliminating the need for ESR induced output
ripple from D-CAP mode control. The low-side MOSFET is turned off when the inductor current information
detects zero level. This enables seamless transition to the reduced frequency operation at light-load conditions
so that high efficiency is kept over a broad range of load current.
9.3.2 Light-Load Condition
TPS53129 automatically reduces switching frequency at light-load conditions to maintain high efficiency. This
reduction of frequency is achieved smoothly and without increase of Vout ripple or load regulation. Detail
operation is described as follows. As the output current decreases from heavy-load condition, the inductor
current is also reduced, and eventually comes to the point that its valley touches zero current, which is the
boundary between continuous conduction and discontinuous condition modes. The low-side MOSFET is turned
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Feature Description (continued)
off when this zero inductor current is detected. As the load current is further decreased, the converter runs in
discontinuous conduction mode and it takes longer and longer to discharge the output capacitor to the level that
requires the next ON cycle. The ON time is kept the same as that in the heavy-load condition. In reverse, when
the output current increases from light load to heavy load, the switching frequency increases to the preset value
as the inductor current reaches the continuous conduction. The transition load point to the light load operation,
IOUT(LL) (i.e., threshold between continuous and discontinuous condition mode) can be calculated as follows.
1
I OUT ( LL ) = 2 ´ L ´ fsw
VIN - Vox
´ Vox
VIN
(1)
Where fSW is the PWM switching frequency.
Switching frequency versus output current in the light-load condition is a function of L, fSW, VIN and VOUT, but it
decreases almost proportional to the output current from the IOUT(LL) given in Equation 1.
9.3.3 Drivers
Each channel of the TPS53129 contains two high-current resistive MOSFET gate drivers. The low-side driver is a
PGND referenced, VREG5 powered driver designed to drive the gate of a high-current, low RDS(ON) N-channel
MOSFET whose source is connected to PGND. The high-side driver is a floating SWx referenced VBST powered
driver designed to drive the gate of a high-current, low RDS(ON) N-channel MOSFET. To maintain the VBST
voltage during the high-side driver ON time, a capacitor is placed from SWx to VBSTx. Each driver draws
average current equal to gate charge (Qg at Vgs = 5 V) times switching frequency (fSW).
To prevent cross-conduction, there is a narrow dead-time when both high-side and low-side drivers are OFF
between each driver transition. During this time the inductor current is carried by one of the MOSFETs body
diodes.
9.3.4 PWM Frequency and Adaptive On-Time Control
TPS53129 employs adaptive on-time control scheme and does not have a dedicated on board oscillator.
TPS53129 runs with pseudo-constant frequency by using the input voltage and output voltage to set the on-time
one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the output voltage.
Therefore, when the duty ratio is VOUT/VIN, the frequency is constant.
9.3.5 5-Volt Regulator
The TPS53129 has an internal 5-V low-dropout (LDO) regulator to provide a regulated voltage for all both drivers
and the IC's internal logic. A high-quality 4.7-μF or greater ceramic capacitor from VREG5 to GND is required to
stabilize the internal regulator. An internal 10-Ω resistor from VREG5 filters the regulator output to the IC's
analog and logic input voltage, V5FILT. An additional high-quality 1.0-μF ceramic capacitor is required from
V5FILT to GND to filter switching noise from VREG5.
9.3.6 Soft Start
The TPS53129 has a programmable soft-start . When the ENx pin becomes high, 2.0-μA current begins charging
the capacitor connected from the SS pin to GND. The internal reference for the D-CAP2™ mode control
comparator is overridden by the soft-start voltage until the soft-start voltage is greater than the internal reference
for smooth control of the output voltage during start up.
9.3.7 Pre-Bias Support
The TPS53129 supports pre-bias start-up without sinking current from the output capacitor. When enabled, the
low-side driver is held off until the soft-start commands a voltage higher than the pre-bias level (internal soft-start
becomes greater than feedback voltage (VFB)), then the TPS53129 slowly activates synchronous rectification by
limiting the first DRVL pulses with a narrow on-time. This limited on-time is then incremented on a cycle-by-cycle
basis until it coincides with the full 1-D off-time. This scheme prevents the initial sinking of current from the prebias output, and ensure that the output voltage (VOUT) starts and ramps up smoothly into regulation and the
control loop is given time to transition from pre-biased start-up to normal mode operation.
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9.4 Device Functional Modes
9.4.1 Output Discharge Control
TPS53129 discharges the outputs when ENx is low, or the controller is turned off by the protection functions
(OVP, UVP, UVLO, and thermal shutdown). The device discharges output using an internal 40-Ω MOSFET which
is connected to VOx and PGNDx. The external low-side MOSFET is not turned on during the output discharge
operation to avoid the possibility of causing negative voltage at the output. This discharge ensures that on start
the regulated voltage always initializes from 0 V.
9.4.2 Over Current Limit
TPS53129 has cycle-by-cycle over current limit feature. The over current limits the inductor valley current by
monitoring the voltage drop across the low-side MOSFET RDS(ON) during the low-side driver on-time. If the
inductor current is larger than the over current limit (OCL), the TPS53129 delays the start of the next switching
cycle until the sensed inductor current falls below the OCL current. MOSFET RDS(ON) current sensing is used to
provide an accuracy and cost effective solution without external devices. To program the OCL, the TRIP pin
should be connected to GND through a trip voltage setting resistor, according to the following equations.
(
)
(VIN - VO) VO
VTRIP = IOCL - ¾
· ¾
2 · L1 · fSW VIN
·
RDS(ON)
(2)
VTRIP (mV)
RTRIP (kW) = ¾
ITRIP (mA)
(3)
The trip voltage should be between 30 mV to 300 mV over all operational temperature, including the 4000ppm/°C temperature slope compensation for the temperature dependency of the RDS(ON).
If the load current exceeds the over current limit, the voltage will begin to drop. If the over current conditions
continues the output voltage will fall below the under voltage protection threshold and the TPS53129 will shut
down.
In an over current condition, the current to the load exceeds the current to the output capacitor; thus the output
voltage tends to fall off. Eventually, it will end up with crossing the under voltage protection threshold and
shutdown.
9.4.3 Over/Under Voltage Protection
TPS53129 monitors a resistor divided feedback voltage to detect over and under voltage. If the feedback voltage
is higher than 115% of the reference voltage, the OVP comparator output goes high and the circuit latches the
high-side MOSFET driver OFF and the low-side MOSFET driver ON.
When the feedback voltage is lower than 70% of the reference voltage, the UVP comparator output goes high
and an internal UVP delay counter begins counting. After 30 μs, TPS53129 latches OFF both top and bottom
MOSFET drivers. This function is enabled approximately 1.7 x TSS after power-on. The OVP and UVP latch off is
reset when EN goes low level.
9.4.4 UVLO Protection
TPS53129 has V5FILT under voltage lock out protection (UVLO) that monitors the voltage of V5FILT pin.
When the V5FILT voltage is lower than UVLO threshold voltage, the device is shut off. All output drivers are OFF
and output discharge is ON. The UVLO is non-latch protection.
9.4.5 Thermal Shutdown
The TPS53129 includes an over temperature protection shut-down feature. If the TPS53129 die temperature
exceeds the OTP threshold (typically 150°C), both the high-side and low-side drivers are shut off, the output
voltage discharge function is enabled and then the device is shut off until the die temperature drops. Thermal
shutdown is a non-latch protection.
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10 Application and Implementation
10.1 Application Information
The TPS53129 is a Dual D-CAP2™ Mode control step-down controller in a realistic cost-sensitive application,
that provides both a low core-type 1.05 V and I/O type 1.8 V output from a loosely regulated 12 V source. Ideal
applications include: digital TV power supplies, networking home pins, digital set-top boxes (STB), DVD players
and recorders, and gaming consoles.
10.2 Typical Application
10.2.1 Typical Application Circuits
Input Voltage
4.5V to 24V
C9
10uF
C10
4700pF
C5
0.1uF
EN2
8
VBST2
9
DRVH2
10
SW2
3
2
1
VFB1
VO1
VO2
VFB2
7
4
SS1
5
GND
6
EN1
24
VBST1 23
Power PAD
C2
0.1uF
DRVH1 22
TPS53129 RGE
SW1
Q1
FDS8878
L1
SPM6530T
1.5uH
21
L1
Q2
FDS8690
C3
10uF
VO1
1.8V/4A
(QFN )
12
PGND2
PGND1 19
C4
22uFx2
PGND
TRIP1
DRVL1 20
VIN
DRVL2
VREG5
11
V5FILT
Q4
FDS8690
SS2
VO2
1.05V/4A
Q3
FDS8878
L2
SPM6530T
1.5uH
SGND
R1
13.5kΩ
R2
10kΩ
TRIP2
C6
10uF
R5
10kΩ
R4
3.63kΩ
PGND
13
14
15
16
17
18
R6
4.7kΩ
C7
4.7uF
C８
1uF
C1
22uFx2
R３
4.3kΩ
PGND
PGND
C11
4700pF
SGND
Figure 6. QFN
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Typical Application (continued)
Q1
FDS8878
L1
SPM6530T
1.5uH
C2
0.1uF
R1
13.5k
Ω
R2
10kΩ
R5
10kΩ
C10
SGND4700pF
R4
3.63kΩ
1
DRVH1
2
VBST1
3
EN1
PGND1
22
4
VO1
TRIP1
21
5
VFB1
VIN
20
6
GND
7
SS1
8
VFB2
SW1
VO1
1.8V/4A
24
Q2
FDS8690
DRVL1 23
C1
22uFx2
R３
4.3kΩ
PGND
Input Voltage
TPS53129PW
TSSOP24
C3
10uF
VREG5 19
V5FILT 18
SS2
17
9
VO2
TRIP2 16
10
EN2
PGND2 15
11
VBST2
DRVL2
14
12
DRVH2
SW2
13
C7
4.7uF
4.5V to 24V
C9
10uF
C８
1uF
PGND
C11
4700pF
R6
4.7kΩ
SGND
PGND
Q4
FDS8690
C5
0.1uF
L2
SPM6530T
1.5uH
Q3
FDS8878
C4
22uFx2
C6
10uF
VO2
1.05V/4A
Figure 7. TSSOP
10.2.2 Design Requirements
Table 1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage
12 V
Output voltage
Vo1 = 1.8 V, Vo2 = 1.05 V
10.2.3 Detailed Design Procedure
1. Choose inductor.
The inductance value is selected to provide approximately 30% peak to peak ripple current at maximum load.
Larger ripple current increases output ripple voltage, improve S/N ratio and contribute to stable operation.
Equation 4 can be used to calculate L1.
L1 =
(V
IN (max)
)´
- Vo1
I L1( ripple) ´ fsw
3´
Vo1
V
=
IN (max)
(V
IN (max)
)´
- Vo1
Io1´ fsw
Vo1
V
(4)
IN (max)
The inductors current ratings needs to support both the RMS (thermal) current and the Peak (saturation)
current. The RMS and peak inductor current can be estimated as follows.
VIN(MAX) - VO1
IL1(RIPPLE) = ¾
L1 · fSW
·
Vo1
¾
VIN(MAX)
(5)
VTRIP
¾
IL1(PEAK) = R
+ IL1(RIPPLE)
DS(ON)
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IL1(RMS) =
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¾
2
1 (I
)
IO 12 + ¾
12 L1(RIPPLE)
(7)
Note: The calculation above shall serve as a general reference. To further improve transient response, the
output inductance could be reduced further. This needs to be considered along with the selection of the
output capacitor.
2. Choose output capacitor.
The capacitor value and ESR determines the amount of output voltage ripple and load transient response. it
is recommended to use a ceramic output capacitor.
IL1(RIPPLE)
C1 = ¾
8 · VO1(RIPPLE)
·
1
¾
fSW
(8)
2
D Iload · L1
C1 = ¾
2 · VO1 · DVOS
(9)
2
load ·
L1
DI
C1 = ¾
2 · K · DVUS
(10)
Where
Ton1
K = (VIN - VO 1) · ¾
Ton1 + Tmin(off)
(11)
Select the capacitance value greater than the largest value calculated from Equation 8, Equation 9 and
Equation 10. The capacitance for C1 should be greater than 66 μF.
Where
ΔVOS = The allowable amount of overshoot voltage in load transition
ΔVUS = The allowable amount of undershoot voltage in load transition
Tmin(off) = Minimum off time
3. Choose input capacitor.
The TPS53129 requires an input decoupling capacitor and a bulk capacitor is needed depending on the
application. A minimum 10-μF high-quality ceramic capacitor is recommended for the input capacitor. The
capacitor voltage rating needs to be greater than the maximum input voltage.
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4. Choose bootstrap capacitor.
The TPS53129 requires a bootstrap capacitor from SW to VBST to provide the floating supply for the highside drivers. A minimum 0.1-μF high-quality ceramic capacitor is recommended. The voltage rating should be
greater than 10 V.
5. Choose VREG5 and V5FILT capacitor.
The TPS53129 requires both the VREG5 regulator and V5FILT input are bypassed. A minimum 4.7-μF highquality ceramic capacitor must be connected between the VREG5 and GND for proper operation. A minimum
1-μF high-quality ceramic capacitor must be connected between the V5FILT and GND for proper operation.
Both of these capacitors’ voltage ratings should be greater than 10 V.
6. Choose output voltage divider resistors.
The output voltage is set with a resistor divider from the output voltage node to the VFBx pin. It is
recommended to use 1% tolerance or better resisters. Select R2 between 10 kΩ and 100 kΩ and use
Equation 12 or Equation 13 to calculate R1.
Vswinj = (VIN - VO1 · 0.5875) ·
R1 =
( )( )
1
¾
fSW
(
VO1
¾
VIN
·
)
VO 1
-1
¾
VFB(RIPPLE) + Vswinj
VFB + ¾
2
·
·
4975
(12)
R2
(13)
Where
VFB(RIPPLE) = Ripple voltage at VFB
Vswinj = Ripple voltage at error comparator
7. Choose register setting for over current limit.
VTRIP =
(
)
(VIN - VO) VO
·¾
IOCL - ¾
2 · L1 · fSW VIN
·
RDS(ON)
(14)
VTRIP (mV) - VOCLoff
RTRIP (kW) = ¾
ITRIP(min) (mA)
(15)
Where
RDS(ON) = Low side FET on-resistance
ITRIP(min) = TRIP pin source current （8.5 μA）
VOCL0ff = Minimum over current limit offset voltage (–20 mV)
IOCL = Over current limit
8. Choose soft start capacitor.
Soft start time equation is as follows.
TSS · ISSC
CSS = ¾
VFB
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10.2.4 Application Curves
800
800
Switching Frequency (KHz)
700
600
VO1 = 1.8V
500
VO1 = 1.2V
400
VO1 = 1.05V
300
200
VO2 = 5V
Switching Frequency (KHz)
VO1 = 5V
VO1 = 3.3V
VO1 = 2.5V
700
VO2 = 3.3V
VO2 = 2.5V
600
VO2 = 1.8V
500
VO2 = 1.2V
400
VO2 = 1.05V
300
200
100
100
0
0
0
5
10
15
Input Voltage (V)
20
0
25
5
IO1 = 3 A
600
600
500
Switching Frequency (KHz)
700
500
400
300
200
100
400
300
200
100
0
0.01
0.1
1
10
0.01
0.1
Output Current (A)
1
10
Output Current (A)
vO1 = 1.8 V
vO2 = 1.05 V
Figure 10. Switching Frequency vs Output Current (CH1)
Figure 11. Switching Frequency vs Output Current (CH2)
1.880
1.100
1.870
1.090
1.860
1.080
1.850
Output Voltage (V)
Output Voltage (V)
25
Figure 9. Switching Frequency vs Input Voltage (CH2)
0
1.840
1.830
1.820
1.810
1.800
1.790
1.070
1.060
1.050
1.040
1.030
1.020
1.780
1.010
1.770
1.760
0.001
0.01
0.1
1
10
1.000
0.001
0.01
vO1 = 1.8 V
Figure 12. Output Voltage vs Output Current (CH1)
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0.1
1
10
Output Current (A)
Output Current (A)
VIN = 12 V
16
20
IO2 = 3 A
Figure 8. Switching Frequency vs Input Voltage (CH1)
Switching Frequency (KHz)
10
15
Input Voltage (V)
VIN = 12 V
vO2 = 1.05 V
Figure 13. Output Voltage vs Output Current (CH2)
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1.880
1.100
1.870
1.090
1.860
1.850
1.080
Output Voltage (V)
Output Voltage (V)
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1.840
1.830
1.820
1.810
1.800
1.790
1.070
1.060
1.050
1.040
1.030
1.780
1.020
1.770
1.010
1.760
1.000
0
5
10
15
20
25
0
5
Input Voltage (V)
VIN = 12 V
vO1 = 1.8 V
Figure 14. Output Voltage vs Input Voltage (CH1)
VIN = 12 V
10
15
Input Voltage (V)
20
25
vO2 = 1.05 V
Figure 15. Output Voltage vs Input Voltage (CH2)
VO1=1.8V (50mV/div)
VO2=1.05V (50mV/div)
Iout1 (2A/div)
Iout2 (2A/div)
Figure 16. Load Transient Response
Figure 17. Load Transient Response
Figure 18. Start-Up Waveforms
Figure 19. Start-Up Waveforms
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100
90
90
80
80
70
Efficiency (%)
Efficiency (%)
70
60
50
40
30
60
50
40
30
20
20
10
10
0
0
0.001
0.01
0.1
1
10
0.001
0.01
Output Current (A)
1
10
vO1 = 1.8 V
vO2 = 1.05 V
Figure 20. 1.8-V Efficiency vs Output Current (CH1)
Figure 21. 1.05-V Efficiency vs Output Current (CH2)
VO1 (20mV/div)
VO1=1.8V
vO1 = 1.8 V
Figure 22. 1.8-V Output Ripple Voltage
18
0.1
Output Current (A)
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VO2 (20mV/div)
VO2=1.05V
vO2 = 1.05 V
Figure 23. 1.05-V Output Ripple Voltage
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11 Power Supply Recommendations
The devices are designed to operate from an input voltage supply range between 4.5 and 24 V. This input supply
must be well-regulated. If the input supply is located more than a few inches from the TPS53129 device, an
additional 0.1 μF ceramic capacitance may be required in addition to the 10 μF of the ceramic bypass capacitors.
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12 Layout
12.1 Layout Suggestions
•
•
•
•
•
•
Keep the input switching current loop as small as possible.
Place the input capacitor (C3,C6) close to the top switching FET. The output current loop should also be kept
as small as possible.
Keep the SW node as physically small and short as possible as to minimize parasitic capacitance and
inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the
feedback pin (FBx) of the device.
Keep analog and non-switching components away from switching components.
Make a single point connection from the signal ground to power ground.
Do not allow switching current to flow under the device.
12.2 Layout Example
VIN
Q3
Q1
SW2
SW1
C3
C6
Q4
Q2
(4)
C9
(5)
(5)
L2
L1
(3) R6 C11 C8
R3
(3)
C7
TRIP2
SS2
V5FILT
12 PGND2
C4, 1
16
17
18
TRIP1
15
VREG5
14
VIN
13
PGND1 19
C1, 1
DRVL1 20
11 DRVL2
(QFN )
10 SW2
TPS53129
9 DRVH2
C5
DRVH1 22
RGE
Thermal PAD
8 VBST2
C4, 2
SW1 21
VO2
VFB2
SS1
GND
VFB1
VO1
TO EN 2
C1, 2
EN1 24
7 EN2
VOUT2
C2
VBST1 23
6
5
4
3
2
1
C10
R4
TO EN 1
R2
R5
VOUT1
R1
(3)
PGND
(1)
Top Side Component or Via
Bottom Side Component
Top Side Etch
Bottom Side Etch
Component Pads Shown in White
SGND
Figure 24. Board Layout
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13 Device and Documentation Support
13.1 Trademarks
Eco-mode, D-CAP2 are trademarks of Texas Instruments.
13.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS53129PW
ACTIVE
TSSOP
PW
24
60
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TPS53129
TPS53129PWR
ACTIVE
TSSOP
PW
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TPS53129
TPS53129RGER
ACTIVE
VQFN
RGE
24
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
53129
TPS53129RGET
ACTIVE
VQFN
RGE
24
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
53129
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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