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TPS54140
SLVS889C – OCTOBER 2008 – REVISED NOVEMBER 2014
TPS54140 1.5-A, 42-V Step-Down DC-DC Converter With Eco-mode™
1 Features
3 Description
•
•
•
The TPS54140 device is a 42-V, 1.5-A, step-down
regulator with an integrated high-side MOSFET.
Current mode control provides simple external
compensation and flexible component selection. A
low-ripple pulse-skip mode reduces the no load,
regulated output-supply current to 116 μA. Using the
enable pin, the shutdown supply current is reduced to
1.3 μA.
1
•
•
•
•
•
•
•
•
•
•
3.5- to 42-V Input Voltage Range
200-mΩ High-Side MOSFET
High Efficiency at Light Loads with a Pulse
Skipping Eco-mode™
116-μA Operating Quiescent Current
1.3-μA Shutdown Current
100-kHz to 2.5-MHz Switching Frequency
Synchronizes to External Clock
Adjustable Slow Start and Sequencing
UV and OV Power-Good Output
Adjustable UVLO Voltage and Hysteresis
0.8-V Internal Voltage Reference
MSOP10 Package With PowerPAD™
Supported by WEBENCH® Software Tool
(www.TI.com/WEBENCH)
2 Applications
•
•
12-V and 24-V Industrial and Commercial Low
Power Systems
Aftermarket Auto Accessories: Video, GPS,
Entertainment
Undervoltage lockout is internally set at 2.5 V, but
can be increased using the enable pin. The outputvoltage startup ramp is controlled by the slow-start
pin that can also be configured for sequencing and
tracking. An open-drain power-good signal indicates
the output is within 94% to 107% of the nominal
voltage.
A wide switching frequency range allows efficiency
and external component size to be optimized.
Frequency foldback and thermal shutdown protects
the device during an overload condition.
The TPS54140 device is available in a 10-pin
thermally enhanced MSOP PowerPAD package.
Device Information(1)
PART NUMBER
TPS54140
PACKAGE
MSOP (10)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
4 Simplified Schematic
Efficiency vs Load Current
VIN
PWRGD
90
TPS54140
80
BOOT
PH
SS /TR
RT /CLK
COMP
VSENSE
Efficiency - %
EN
85
75
70
65
VI = 12 V,
VO = 3.3 V,
fsw = 1200 kHz
60
55
GND
50
0
0.25
0.50
0.75
1
1.25
Load Current - A
1.50
1.75
2
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS54140
SLVS889C – OCTOBER 2008 – REVISED NOVEMBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
4
4
4
5
5
6
Absolute Maximum Ratings .....................................
Handling Ratings.......................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 11
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram ....................................... 12
8.3 Feature Description................................................. 12
8.4 Device Functional Modes........................................ 27
9
Application and Implementation ........................ 29
9.1 Application Information............................................ 29
9.2 Typical Application .................................................. 29
10 Power Supply Recommendations ..................... 40
11 Layout................................................................... 40
11.1 Layout Guidelines ................................................. 40
11.2 Layout Example .................................................... 41
12 Device and Documentation Support ................. 41
12.1
12.2
12.3
12.4
12.5
Device Support......................................................
Documentation Support ........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
41
41
42
42
42
13 Mechanical, Packaging, and Orderable
Information ........................................................... 42
5 Revision History
Changes from Revision B (September 2013) to Revision C
•
Added the Handling Ratings table and the following sections:Feature Description, Device Functional Modes,
Application and Implementation, Power Supply Recommendations, Device and Documentation Support, and
Mechanical, Packaging, and Orderable Information............................................................................................................... 1
Changes from Revision A (August 2012) to Revision B
•
Page
Page
Deleted SWIFT from the data sheet Title and Features......................................................................................................... 1
Changes from Original (October 2008) to Revision A
Page
•
Changed Features Item From: 300kHz to 2.5MHz Switching Frequency To: 100kHz to 2.5MHz Switching Frequency ...... 1
•
Changed Description text From: "within 93% to 107% of its nom voltage." To: "within 94% to 107% of its nom voltage."... 1
•
Changed Enable threshold +50 mV TYP value From: ±3.8 To: –3.8..................................................................................... 5
•
Changed Enable threshold ±50 mV TYP value From: ±0.9 To: –0.98 ................................................................................... 5
•
Changed Hysteresis current TYP value From: ±2.9 To: –2.9 ................................................................................................ 5
•
Changed Error amplifier transconductance (gM) Test Condition From: ±2 μA < ICOMP < 2 μA, VCOMP = 1 V To: –2 μA
< ICOMP < 2 μA, VCOMP = 1 V ................................................................................................................................................... 5
•
Changed Error amplifier transconductance (gM) during slow start From: ±2 μA < ICOMP < 2 μA, VCOMP = 1 V To: –2
μA < ICOMP < 2 μA, VCOMP = 1 V.............................................................................................................................................. 5
•
Changed text in the Error Amplifier section From: "the gm is 25 μA/V" To: "the gm is 26 μA/V" ....................................... 14
•
Changed text in the Slow Start and Tracking Pin (SS/TR) section From: "VIN UVLO is exceeded, EN pin pulled
below 1.25V" To: "VIN pin is below the VIN UVLO, EN pin pulled below 1.25V" ................................................................ 15
•
Changed Start Input Voltage (rising VIN) voltage From: 7.25 V To: 7.7 V........................................................................... 29
•
Changed Start Input Voltage (falling VIN) voltage From: 6.25 V To: 6.7 V.......................................................................... 29
•
Changed Equation 29........................................................................................................................................................... 30
•
Changed 7.25V to 7.7V and 6.25V to 6.7V in the Under Voltage Lock Out Set Point section. ........................................... 34
•
Changed Equation 47........................................................................................................................................................... 36
•
Changed Equation 49........................................................................................................................................................... 36
2
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SLVS889C – OCTOBER 2008 – REVISED NOVEMBER 2014
6 Pin Configuration and Functions
DGQ Package
10-Pin MSOP With PowerPAD™
Top View
BOOT
1
VIN
2
10
Thermal Pad
(11)
PH
9
GND
8
COMP
EN
3
SS/TR
4
7
VSENSE
RT/CLK
5
6
PWRGD
Pin Functions
PIN
I/O
DESCRIPTION
NO.
NAME
1
BOOT
O
A bootstrap capacitor is required between the BOOT and PH pins. If the voltage on this capacitor is below
the minimum required by the device, the output is forced to switch off until the capacitor is refreshed.
2
VIN
I
This pin is the 3.5- to 42-V input supply voltage.
3
EN
I
This pin is the enable pin and internal pullup current source. To disable, pull below 1.2 V. Float this pin to
enable. Adjust the input undervoltage lockout with two resistors.
4
SS/TR
I
This pin is the slow-start and tracking pin. An external capacitor connected to this pin sets the output rise
time. Because the voltage on this pin overrides the internal reference, it can be used for tracking and
sequencing.
5
RT/CLK
I
This pin is the resistor timing and external clock pin. An internal amplifier holds this pin at a fixed voltage
when using an external resistor to ground to set the switching frequency. If the pin is pulled above the PLL
upper threshold, a mode change occurs and the pin becomes a synchronization input. The internal amplifier
is disabled and the pin is a high impedance clock input to the internal PLL. If clocking edges stop, the
internal amplifier is re-enabled and the mode returns to a resistor set function.
6
PWRGD
O
This pin is an open drain output. This pin is asserted low if the output voltage is low because of thermal
shutdown, dropout, overvoltage, or EN shut down.
7
VSENSE
I
This pin is the inverting node of the transconductance (gm) error amplifier.
8
COMP
O
This pin is the error amplifier output and input to the output-switch current comparator. Connect frequency
compensation components to this pin.
9
GND
—
Ground pin
10
PH
O
This pin is the source of the internal high-side power MOSFET.
11
Thermal Pad
—
The GND pin must be electrically connected to the exposed pad on the printed circuit board for proper
operation.
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SLVS889C – OCTOBER 2008 – REVISED NOVEMBER 2014
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7 Specifications
7.1 Absolute Maximum Ratings (1)
Over operating temperature range (unless otherwise noted).
MIN
MAX
VIN
–0.3
47
EN
–0.3
BOOT
Input voltage
VSENSE
–0.3
3
COMP
–0.3
3
PWRGD
–0.3
6
SS/TR
–0.3
3
RT/CLK
–0.3
3.6
–0.6
47
–2
47
Source current
±200
EN
100
μA
BOOT
100
mA
10
μA
VSENSE
mV
Current Limit
RT/CLK
A
100
VIN
μA
Current Limit
A
100
μA
PWRGD
10
mA
SS/TR
200
μA
150
°C
COMP
Operating junction temperature
(1)
V
PAD to GND
PH
Sink current
V
8
PH
PH, 10-ns Transient
Voltage Difference
5
55
PH–BOOT
Output voltage
UNIT
–40
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 Handling Ratings
Tstg
Storage temperature range
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
MIN
MAX
UNIT
–65
150
°C
–1
1
kV
–500
500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
TJ
4
Operating input voltage on the VIN pin
3.5
Output voltage
Output current
Operating junction temperature
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NOM
MAX
UNIT
42
V
0.8
39
V
0
1.5
A
–40
150
°C
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SLVS889C – OCTOBER 2008 – REVISED NOVEMBER 2014
7.4 Thermal Information
DGQ
THERMAL METRIC (1)
RθJA
Junction-to-ambient thermal resistance
67.4
RθJC(top)
Junction-to-case (top) thermal resistance
46.7
RθJB
Junction-to-board thermal resistance
38.4
ψJT
Junction-to-top characterization parameter
1.9
ψJB
Junction-to-board characterization parameter
38.4
RθJC(bot)
Junction-to-case (bottom) thermal resistance
46.7
(1)
UNIT
10 PINS
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.5 Electrical Characteristics
TJ = –40°C to 150°C, VIN = 3.5 to 42V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE (VIN PIN)
Operating input voltage
3.5
Internal undervoltage lockout threshold
No voltage hysteresis, rising and falling
Shutdown supply current
EN = 0 V, 25°C, 3.5 V ≤ VIN ≤ 42 V
42
2.5
Operating : nonswitching supply current VSENSE = 0.83 V, VIN = 12 V, 25°C
V
V
1.3
4
116
136
1.25
1.55
μA
ENABLE AND UVLO (EN PIN)
Enable threshold voltage
Input current
No voltage hysteresis, rising and falling, 25°C
0.9
Enable threshold 50 mV
–3.8
Enable threshold ±50 mV
–0.9
Hysteresis current
V
μA
μA
–2.9
VOLTAGE REFERENCE
Voltage reference
TJ = 25°C
0.792
0.8
0.808
0.784
0.8
0.816
V
HIGH-SIDE MOSFET
On-resistance
VIN = 3.5 V, BOOT-PH = 3 V
300
VIN = 12 V, BOOT-PH = 6 V
200
410
mΩ
ERROR AMPLIFIER
Input current
50
nA
Error amplifier transconductance (gM)
–2 μA < ICOMP < 2 μA, VCOMP = 1 V
97
μMhos
Error amplifier transconductance (gM)
during slow start
–2 μA < ICOMP < 2 μA, VCOMP = 1 V,
VVSENSE = 0.4 V
26
μMhos
Error amplifier dc gain
VVSENSE = 0.8 V
Error amplifier bandwidth
Error amplifier source/sink
V(COMP) = 1 V, 100 mV overdrive
COMP to switch current
transconductance
10 000
V/V
2700
kHz
±7
μA
6
A/V
CURRENT LIMIT
Current limit threshold
VIN = 12 V, TJ = 25°C
1.8
2.7
A
182
°C
THERMAL SHUTDOWN
Thermal shutdown
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
Switching Frequency Range using RT
mode
fSW
Switching frequency
100
RT = 200 kΩ
Switching Frequency Range using CLK
mode
450
300
581
2500
kHz
720
kHz
2200
kHz
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Electrical Characteristics (continued)
TJ = –40°C to 150°C, VIN = 3.5 to 42V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
Minimum CLK pulse width
40
RT/CLK high threshold
1.9
RT/CLK low threshold
0.5
RT/CLK falling edge to PH rising edge
delay
Measured at 500 kHz with RT resistor in series
PLL lock in time
Measured at 500 kHz
MAX
UNIT
ns
2.2
V
0.7
V
60
ns
100
μs
SLOW START AND TRACKING (SS/TR)
Charge current
VSS/TR = 0.4 V
2
μA
SS/TR-to-VSENSE matching
VSS/TR = 0.4 V
45
mV
SS/TR-to-reference crossover
98% nominal
1.0
V
SS/TR discharge current (overload)
VSENSE = 0 V, V(SS/TR) = 0.4 V
112
μA
SS/TR discharge voltage
VSENSE = 0 V
54
mV
VSENSE falling
92%
POWER GOOD (PWRGD PIN)
VVSENSE
VSENSE rising
94%
VSENSE rising
109%
VSENSE falling
107%
Hysteresis
VSENSE falling
2%
Output high leakage
VSENSE = VREF, V(PWRGD) = 5.5 V, 25°C
10
nA
On resistance
I(PWRGD) = 3 mA, VSENSE < 0.79 V
50
Ω
Minimum VIN for defined output
V(PWRGD) < 0.5 V, II(PWRGD) = 100 μA
VSENSE threshold
0.95
1.5
V
0.816
500
VI = 12 V
VI = 12 V
375
Vref - Voltage Reference - V
RDSON - Static Drain-Source On-State Resistance - mW
7.6 Typical Characteristics
BOOT-PH = 3 V
250
BOOT-PH = 6 V
125
0
-50
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
150
Figure 1. On Resistance vs Junction Temperature
6
0.808
0.800
0.792
0.784
-50
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
150
Figure 2. Voltage Reference vs Junction Temperature
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Typical Characteristics (continued)
3.5
610
VI = 12 V,
RT = 200 kW
VI = 12 V
fs - Switching Frequency - kHz
Switch Current - A
600
3
2.5
590
580
570
560
2
-50
-25
0
25
50
75
100
125
550
-50
150
-25
0
TJ - Junction Temperature - °C
25
50
75
100
TJ - Junction Temperature - °C
125
150
Figure 4. Switching Frequency vs Junction Temperature
Figure 3. Switch Current Limit vs Junction Temperature
500
2500
2000
Switching Frequency (kHz)
fs - Switching Frequency - kHz
VI = 12 V,
TJ = 25°C
1500
1000
500
400
300
200
100
0
200
0
0
25
50
75
100
125
RT/CLK - Resistance - kW
150
175
200
Figure 5. Switching Frequency vs RT/CLK Resistance, High
Frequency Range
300
400
500 600 700 800 900 1000 1100 1200
RT/CLK Resistance (kW)
C006
Figure 6. Switching Frequency vs RT/CLK Resistance, Low
Frequency Range
150
40
VI = 12 V
VI = 12 V
130
gm - mA/V
gm - mA/V
30
110
90
20
70
10
-50
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
150
50
-50
-25
0
25
50
75
100
125
150
TJ - Junction Temperature - °C
Figure 7. EA Transconductance During Slow Start vs
Junction Temperature
Figure 8. EA Transconductance vs Junction Temperature
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Typical Characteristics (continued)
1.40
-3.25
VI = 12 V,
VI(EN) = Threshold +50 mV
VI = 12 V
-3.5
I(EN) - mA
EN - Threshold - V
1.30
-3.75
1.20
-4
1.10
-50
-25
0
25
50
75
100
125
150
-4.25
-50
-25
0
25
Figure 9. EN Pin Voltage vs Junction Temperature
75
100
125
150
Figure 10. EN Pin Current vs Junction Temperature
-1
-0.8
VI = 12 V,
VI(EN) = Threshold -50 mV
VI = 12 V
-0.85
-1.5
I(SS/TR) - mA
I(EN) - mA
50
TJ - Junction Temperature - °C
TJ - Junction Temperature - °C
-0.9
-0.95
-2
-2.5
-1
-50
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
-3
-50
150
Figure 11. EN Pin Current vs Junction Temperature
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
150
Figure 12. SS/TR Charge Current vs Junction Temperature
120
100
VI = 12 V
VI = 12 V,
TJ = 25°C
80
% of Nominal fsw
II(SS/TR) - mA
115
110
60
40
105
20
100
-50
0
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
150
Figure 13. SS/TR Discharge Current vs Junction
Temperature
8
0
0.2
0.4
VSENSE - V
0.6
0.8
Figure 14. Switching Frequency vs VSENSE
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Typical Characteristics (continued)
2
2
VI = 12 V
TJ = 25°C
1.5
I(VIN) - mA
I(VIN) - mA
1.5
1
0.5
1
0.5
0
-50
0
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
150
0
Figure 15. Shutdown Supply Current vs Junction
Temperature
10
o
TJ = 25 C,
VI(VSENSE) = 0.83 V
130
120
120
I(VIN) - mA
I(VIN) - mA
130
110
100
110
100
90
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
0
150
20
VI - Input Voltage - V
40
Figure 18. VIN Supply Current vs Input Voltage
Figure 17. VIN Supply Current vs Junction Temperature
115
100
VI = 12 V
VI = 12 V
PWRGD Threshold - % of Vref
80
RDSON - W
40
140
VI = 12 V,
VI(VSENSE) = 0.83 V
60
40
20
VSENSE Rising
110
VSENSE Falling
105
100
VSENSE Rising
95
VSENSE Falling
90
0
-50
30
Figure 16. Shutdown Supply Current vs Input Voltage (VIN)
140
90
-50
20
VI - Input Voltage - V
-25
0
25
50
75
100
125
150
85
-50
-25
TJ - Junction Temperature - °C
Figure 19. PWRGD On Resistance vs Junction Temperature
0
25
50
75
100
TJ - Junction Temperature - °C
125
150
Figure 20. PWRGD Threshold vs Junction Temperature
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2.5
3
2.3
2.75
VI(VIN) - V
VI(BOOT-PH) - V
Typical Characteristics (continued)
2
1.8
2.50
2.25
1.5
-50
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
2
-50
150
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
150
Figure 22. Input Voltage (UVLO) vs Junction Temperature
Figure 21. BOOT-PH UVLO vs Junction temperature
60
500
V(SS/TR) = 0.2 V
VI = 12 V
VI = 12 V,
o
TJ = 25 C
55
400
Offset - mV
Offset - mV
50
300
200
45
40
100
0
0
35
100
200
300
400
500
600
700
800
30
-50
Figure 23. SS/TR to VSENSE Offset vs VSENSE
10
-25
0
25
50
75
100
125
150
TJ - Junction Temperature - °C
VSENSE - mV
Figure 24. SS/TR to VSENSE Offset vs Temperature
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8 Detailed Description
8.1 Overview
The TPS54140 device is a 42-V, 1.5-A, step-down (buck) regulator with an integrated high-side n-channel
MOSFET. To improve performance during line and load transients, the device implements a constant-frequency,
current mode control which reduces output capacitance and simplifies external frequency compensation design.
The wide switching frequency of 100 kHz to 2500 kHz allows for efficiency and size optimization when selecting
the output filter components. The switching frequency is adjusted using a resistor to ground on the RT/CLK pin.
The device has an internal phase-lock loop (PLL) on the RT/CLK pin that is used to synchronize the powerswitch turn on to a falling edge of an external system clock.
The TPS54140 device has a default startup voltage of approximately 2.5 V. The EN pin has an internal pullup
current-source that can be used to adjust the input-voltage undervoltage-lockout (UVLO) threshold with two
external resistors. In addition, the pullup current provides a default condition. The device operates when the EN
pin is floating. The operating current is 116 μA when not switching and under no load. When the device is
disabled, the supply current is 1.3 μA.
The integrated 200-mΩ high-side MOSFET allows for high-efficiency power-supply designs capable of delivering
1.5 A of continuous current to a load. The TPS54140 device reduces the external component count by
integrating the boot-recharge diode. The bias voltage for the integrated high-side MOSFET is supplied by a
capacitor on the BOOT to PH pin. The boot-capacitor voltage is monitored by an UVLO circuit and turns the highside MOSFET off when the boot voltage falls below a preset threshold. The TPS54140 device can operate at
high duty cycles because of the boot UVLO. The output voltage can be stepped down to as low as the 0.8-V
reference.
The TPS54140 device has a power good comparator (PWRGD) which asserts when the regulated output voltage
is less than 92% or greater than 109% of the nominal output voltage. The PWRGD pin is an open drain output
which deasserts when the VSENSE pin voltage is between 94% and 107% of the nominal output voltage
allowing the pin to transition high when a pullup resistor is used.
The TPS54140 device minimizes excessive-output overvoltage (OV) transients by taking advantage of the OV
power-good comparator. When the OV comparator is activated, the high-side MOSFET is turned off and masked
from turning on until the output voltage is lower than 107%.
The SS/TR (slow start/tracking) pin is used to minimize inrush currents or provide power-supply sequencing
during power up. A small value capacitor should be coupled to the pin to adjust the slow-start time. A resistor
divider can be coupled to the pin for critical power-supply sequencing requirements. The SS/TR pin is discharged
before the output powers up. This discharging ensures a repeatable restart after an over-temperature fault,
UVLO fault, or a disabled condition.
The TPS54140 device also discharges the slow-start capacitor during overload conditions with an overload
recovery circuit. The overload recovery circuit slow starts the output from the fault voltage to the nominal
regulation voltage when a fault condition is removed. A frequency -foldback circuit reduces the switching
frequency during startup and overcurrent fault conditions to help control the inductor current.
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8.2 Functional Block Diagram
PWRGD
6
EN
3
VIN
2
Shutdown
UO
Thermal
Shutdown
Enable
Comparator
Logic
UVLO
Shutdown
Shutdown
Logic
OV
Enable
Threshold
Boot
Charge
Voltage
Reference
Boot
UVLO
Minimum
Clamp
Pulse
Skip
ERROR
AMPLIFIER
PWM
Comparator
VSENSE 7
Current
Sense
1 BOOT
Logic
And
PWM Latch
SS/TR 4
Shutdown
Slope
Compensation
10 PH
COMP 8
11 POWERPAD
Frequency
Shift
Overload
Recovery
Maximum
Clamp
Oscillator
with PLL
TPS54140 Block Diagram
9 GND
5
RT/CLK
8.3 Feature Description
8.3.1 Fixed Frequency PWM Control
The TPS54140 device uses an adjustable fixed-frequency, peak-current mode control. The output voltage is
compared through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier
which drives the COMP pin. An internal oscillator initiates the turn on of the high-side MOSFET power switch.
The error amplifier output is compared to the high-side MOSFET power-switch current. When the power-switch
current reaches the COMP voltage level the power switch is turned off. The COMP pin voltage increases and
decreases as the output current increases and decreases. The device implements a current limit by clamping the
COMP pin voltage to a maximum level. The Eco-mode is implemented with a minimum clamp on the COMP pin.
8.3.2 Slope Compensation Output Current
The TPS54140 device adds a compensating ramp to the switch-current signal. This slope compensation
prevents sub-harmonic oscillations. The available peak inductor current remains constant over the full duty-cycle
range.
12
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Feature Description (continued)
8.3.3 Bootstrap Voltage (BOOT)
The TPS54140 device has an integrated boot regulator and requires a small ceramic capacitor between the
BOOT and PH pins to provide the gate-drive voltage for the high-side MOSFET. The value of the ceramic
capacitor should be 0.1 μF. A ceramic capacitor with an X7R- or X5R-grade dielectric is recommended because
of the stable characteristics over temperature and voltage. To improve drop out, the TPS54140 device is
designed to operate at 100% duty cycle as long as the BOO-to-PH pin voltage is greater than 2.1 V. When the
voltage from the BOOT to PH pins drops below 2.1 V, the high-side MOSFET is turned off using an UVLO circuit
allowing for the low-side diode to conduct which allows refreshing of the BOOT capacitor. Because the supply
current sourced from the BOOT capacitor is low, the high-side MOSFET can remain on for more switching cycles
than it refreshes, thus, the effective duty-cycle limitation that is attributed to the boot regulator system is high.
8.3.4 Low Dropout Operation
The duty cycle during dropout of the regulator is mainly determined by the voltage drops across the power
MOSFET, inductor, low-side diode, and printed circuit-board resistance. During operating conditions in which the
input voltage drops, the high-side MOSFET can remain on for 100% of the duty cycle to maintain output
regulation or until the BOOT-to-PH voltage falls below 2.1 V.
When the high-side MOSFET is off, the low-side diode conducts and the BOOT capacitor recharges. During this
boot-capacitor recharge time, the inductor current ramps down until the high-side MOSFET turns on. The
recharge time is longer than the typical high-side MOSFET off time of previous switching cycles, and thus, the
inductor current ripple is larger. The larger ripple current results in more ripple voltage on the output. The
recharge time is a function of the input voltage, boot capacitor value, and the impedance of the internal bootrecharge diode.
Attention must be given to maximum duty-cycle applications that experience extended time periods without a
load current. The high-side MOSFET turns off when the voltage across the BOOT capacitors falls below the 2.1V threshold in applications that have a difference in the input voltage and output voltage that is less than 3 V.
However, the inductor does not have enough current to pull the PH pin down to recharge the boot capacitor. The
regulator does not switch because the boot capacitor is less than 2.1 V and the output capacitor decays until the
difference in the input voltage and output voltage is 2.1 V. At this time the boot undervoltage lockout is exceeded
and the device switches until the desired output voltage is reached.
Figure 25 and Figure 26 show the start and stop voltages for 3.3-V and 5-V applications. The voltages are
plotted versus the load current. The start voltage is defined as the input voltage required to regulate the output
voltage with 1%. The stop voltage is defined as the input voltage at which the output drops by 5% or stops
switching.
4
5.6
VO = 3.3 V
VO = 5 V
5.4
VI - Input Voltage - V
VI - Input Voltage - V
3.8
3.6
Start
3.4
Stop
3.2
5.2
Start
5
Stop
4.8
3
4.6
0
0.05
0.10
IO - Output Current - A
0.15
0.20
0
Figure 25. 3.3-V Start and Stop Voltage
0.05
0.10
IO - Output Current - A
0.15
Figure 26. 5-V Start and Stop Voltage
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Feature Description (continued)
8.3.5 Error Amplifier
The TPS54140 device has a transconductance amplifier for the error amplifier. The error amplifier compares the
VSENSE voltage to the lower voltage of either the SS/TR pin voltage or the internal 0.8-V voltage reference. The
transconductance (gm) of the error amplifier is 97 μA/V during normal operation. During the slow-start operation,
the transconductance is a fraction of the normal operating gm. When the voltage of the VSENSE pin is below 0.8
V and the device is regulating using the SS/TR voltage, the gm is 26 μA/V.
The frequency compensation components (capacitor, series resistor, and capacitor) are added to the COMP pin
to ground.
8.3.6 Voltage Reference
The voltage reference system produces a precise ±2% voltage reference over temperature by scaling the output
of a temperature-stable bandgap circuit.
8.3.7 Adjusting the Output Voltage
The output voltage is set with a resistor divider from the output node to the VSENSE pin. Using divider resistors
with a tolerance of 1% or better is recommended. Begin with a value of 10 kΩ for the R2 resistor and use
Equation 1 to calculate the value of R1. To improve efficiency at very light loads, consider using larger value
resistors. If the values are too high the regulator will be more susceptible to noise and voltage errors from the
VSENSE input current will be noticeable
æ (VOUT - 0.8 V ) ö
R1 = R2 ´ ç
÷
ç
÷
0.8 V
è
ø
(1)
8.3.8 Enable and Adjusting Undervoltage Lockout
The TPS54140 device is disabled when the VIN pin voltage falls below 2.5 V. If an application requires a higher
undervoltage lockout (UVLO), use the EN pin as shown in Figure 27 to adjust the input voltage UVLO by using
the two external resistors. Using the UVLO to adjust registers is not required but is highly recommended for
operation to provide consistent power-up behavior. The EN pin has an internal pullup-current source, I1, of 0.9
μA that provides the default condition of the TPS54140 device while operating when the EN pin is floating. When
the EN pin voltage exceeds 1.25 V, an additional 2.9 μA of hysteresis, Ihys, is added. This additional current
facilitates input voltage hysteresis. Use Equation 2 to calculate R1 which sets the external hysteresis for the input
voltage. Use Equation 3 to calculate R2 which sets the input start voltage.
TPS54140
VIN
Ihys
I1
0.9 mA
R1
2.9 mA
+
R2
EN
1.25 V
-
Figure 27. Adjustable Undervoltage Lockout (UVLO)
V
- VSTOP
R1 = START
IHYS
R2 =
14
(2)
VENA
VSTART - VENA
+ I1
R1
(3)
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Feature Description (continued)
Figure 28 shows another technique for adding input voltage hysteresis. This method can be used if the
resistance values are high from the previous method and a wider voltage hysteresis is needed. The resistor, R3,
sources additional hysteresis current into the EN pin.
TPS54140
VIN
R1
Ihys
I1
0.9 mA
2.9 mA
+
R2
EN
1.25 V
R3
-
VOUT
Figure 28. Adding Additional Hysteresis
VSTART - VSTOP
V
IHYS + OUT
R3
R1 =
R2 =
(4)
VENA
VSTART - VENA
V
+ I1 - ENA
R1
R3
(5)
8.3.9 Slow Start and Tracking Pin (SS/TR)
The TPS54140 device effectively uses the lower voltage of the internal voltage reference or the SS/TR pin
voltage as the reference voltage of the power supply and regulates the output accordingly. A capacitor on the
SS/TR pin to ground implements a slow-start time. The TPS54140 device has an internal pullup-current source
of 2 μA that charges the external slow-start capacitor. Use Equation 6 to calculate the value of the slow-start
capacitor, CSS, which sets the slow-start time, tSS (10% to 90%). The slow-start capacitor should remain lower
than 0.47μF and greater than 0.47nF.
CSS (nF ) =
tSS (ms )´ ISS (mA )
VREF (V )´ 0.8
where
•
•
The voltage reference (VREF) is 0.8 V
The slow start current (ISS) is 2 μA
(6)
At power up, the TPS54140 device does not begin switching until the slow-start pin is discharged to less than 40
mV to ensure a proper power up (see Figure 29).
Also, during normal operation, the TPS54140 device stops switching and the SS/TR must be discharged to 40
mV when the voltage at the VIN pin is below the VIN UVLO, EN pin pulled below 1.25 V, or a thermal shutdown
event occurs.
The VSENSE voltage follows the SS/TR pin voltage with a 45-mV offset up to 85% of the internal voltage
reference. When the SS/TR voltage is greater than 85% on the internal reference voltage the offset increases as
the effective system reference transitions from the SS/TR voltage to the internal voltage reference (see
Figure 23). The SS/TR voltage ramps linearly until clamped at 1.7 V.
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Feature Description (continued)
EN
SS/TR
VSENSE
VOUT
Figure 29. Operation of SS/TR Pin When Starting
8.3.10 Overload-Recovery Circuit
The TPS54140 device has an overload-recovery (OLR) circuit. The OLR circuit slow starts the output from the
overload voltage to the nominal regulation voltage when the fault condition is removed. The OLR circuit
discharges the SS/TR pin to a voltage slightly greater than the VSENSE pin voltage using an internal pulldown of
100 μA when the error amplifier is changed to a high voltage from a fault condition. When the fault condition is
removed, the output slow starts from the fault voltage to nominal output voltage.
8.3.11 Sequencing
Many of the common power-supply sequencing methods can be implemented using the SS/TR, EN, and
PWRGD pins. The sequential method can be implemented using an open-drain output of the power-on reset pin
of another device. Figure 30 shows the sequential method using two TPS54140 devices. The power good is
coupled to the EN pin on the TPS54140 device which enables the second power supply when the primary supply
reaches regulation. If needed, a 1-nF ceramic capacitor on the EN pin of the second power supply provides a 1ms startup delay. Figure 31 shows the results of Figure 30.
16
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Feature Description (continued)
TPS54140
EN
PWRGD
EN
EN1
SS /TR
SS /TR
PWRGD1
PWRGD
VOUT1
VOUT2
Figure 30. Schematic for Sequential Startup
Sequence
Figure 31. Sequential Startup using EN and
PWRGD
TPS54140
TPS54160
3
EN
4
SS/TR
6
PWRGD
EN1, EN2
VOUT1
TPS54160
TPS54140
VOUT2
3
EN
4
SS/TR
6
PWRGD
Figure 32. Schematic for Ratiometric Startup
Sequence
Figure 33. Ratio-Metric Startup using Coupled
SS/TR pins
Figure 32 shows a method for ratiometric start up sequence by connecting the SS/TR pins together. The
regulator outputs will ramp up and reach regulation at the same time. When calculating the slow-start time the
pullup current source must be doubled in Equation 6. Figure 33 shows the results of Figure 32.
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Feature Description (continued)
TPS54140
EN
VOUT 1
SS/TR
PWRGD
TPS54140
VOUT 2
EN
R1
SS/ TR
R2
PWRGD
R3
R4
Figure 34. Schematic for Ratiometric and Simultaneous Startup Sequence
Ratiometric and simultaneous power supply sequencing can be implemented by connecting the resistor network
of R1 and R2 shown in Figure 34 to the output of the power supply that needs to be tracked or another voltage
reference source. Using Equation 7 and Equation 8, the tracking resistors can be calculated to initiate VOUT2
slightly before, after, or at the same time as VOUT1. Equation 9 is the voltage difference between VOUT1 and VOUT2
at the 95% of nominal output regulation.
The ΔV variable is 0 V for simultaneous sequencing. To minimize the effect of the inherent SS/TR to VSENSE
offset (VSS(offset)) in the slow-start circuit and the offset created by the pullup current source (ISS) and tracking
resistors. VSS(offset) and ISS are included as variables in the equations.
To design a ratiometric startup in which the VOUT2 voltage is slightly greater than the VOUT1 voltage when VOUT2
reaches regulation, use a negative number in Equation 7 through Equation 9 for ΔV. Equation 9 results in a
positive number for applications which the VOUT2 is slightly lower than VOUT1 when VOUT2 regulation is achieved.
Because the SS/TR pin must be pulled below 40 mV before starting after an EN, UVLO, or thermal shutdown
fault, careful selection of the tracking resistors is needed to ensure the device restarts after a fault. To ensure the
device can recover from a fault, the calculated value of R1 from Equation 7 must be greater than the value
calculated in Equation 10.
As the SS/TR voltage becomes more than 85% of the nominal reference voltage, VSS(offset) becomes larger as the
slow-start circuits gradually handoff the regulation reference to the internal voltage reference. The SS/TR pin
voltage must be greater than 1.3 V for a complete handoff to the internal voltage reference as shown in
Figure 23.
V
+ DV VSS(offset )
R1 = OUT2
+
VREF
ISS
(7)
R2 =
VREF ´ R1
VOUT2 + DV - VREF
(8)
DV = VOUT1 - VOUT2
18
(9)
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Feature Description (continued)
R1 > 2800 ´ VOUT1 - 180 ´ DV
(10)
EN
EN
VOUT1
VOUT1
VOUT2
Figure 35. Ratiometric Startup with Tracking Resistors
VOUT2
Figure 36. Ratiometric Startup with Tracking Resistors
EN
VOUT1
VOUT2
Figure 37. Simultaneous Startup With Tracking Resistor
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Feature Description (continued)
8.3.12 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
The switching frequency of the TPS54140 device is adjustable over a wide range from approximately 100 kHz to
2500 kHz by placing a resistor on the RT/CLK pin. The RT/CLK pin voltage is typically 0.5 V and must have a
resistor to ground to set the switching frequency. To determine the timing resistance for a given switching
frequency, use Equation 11 or the curves in Figure 38 or Figure 39. To reduce the solution size, a user typically
sets the switching frequency as high as possible, but tradeoffs of the supply efficiency, maximum input voltage
and minimum controllable on time should be considered.
The minimum controllable on time is 130 ns (typical) and limits the maximum operating input voltage.
The maximum switching frequency is also limited by the frequency shift circuit. The following sections describe
the maximum switching frequency in detail.
206033
RRT (kW ) =
1.0888
fSW (kHz )
(11)
500
2500
2000
Switching Frequency (kHz)
fs - Switching Frequency - kHz
VI = 12 V,
TJ = 25°C
1500
1000
500
0
0
25
50
75
100
125
150
RT/CLK - Clock Resistance - kW
175
200
400
300
200
100
0
200
300
Figure 38. High Range RT
400
500 600 700 800 900 1000 1100 1200
RT/CLK Resistance (kW)
C006
Figure 39. Low Range RT
8.3.13 Overcurrent Protection and Frequency Shift
The TPS54140 device implements current mode control which uses the COMP pin voltage to turn off the highside MOSFET on a cycle-by-cycle basis. During each cycle the switch current and COMP pin voltage are
compared. When the peak inductor current intersects the COMP pin voltage, the high-side switch is turned off.
During overcurrent conditions that pull the output voltage low, the error amplifier responds by driving the COMP
pin high, causing the switch current to increase. The COMP pin has a maximum clamp internally, which limits the
output current.
To increase the maximum operating switching frequency at high input voltages the TPS54140 device implements
a frequency shift. The switching frequency is divided by 8, 4, 2, and 0 as the voltage ramps from 0 to 0.8 V on
VSENSE pin.
The device implements a digital frequency shift to enable synchronizing to an external clock during normal
startup and fault conditions. Because the device can only divide the switching frequency by 8 at the most, a
maximum input voltage limit exists in which the device can operate and still have frequency shift protection.
During short-circuit events (particularly with high input-voltage applications), the control loop has a finite,
minimum controllable on time and the output has a very low voltage. During the switch on time, the inductor
current ramps to the peak current limit because of the high input voltage and minimum on time. During the switch
off time, the inductor would normally not have enough off time and output voltage for the inductor to ramp down
by the ramp up amount. The frequency shift effectively increases the off time allowing the current to ramp down.
20
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Feature Description (continued)
8.3.14 Selecting the Switching Frequency
The switching frequency that is selected should be the lower value of the Equation 12 and Equation 13. Use
Equation 12 to calculate the maximum switching frequency limitation set by the minimum controllable on time.
Setting the switching frequency above this value causes the regulator to skip switching pulses.
Use Equation 13 to calculate the maximum switching-frequency limit set by the frequency shift protection. For
adequate output short-circuit protection at high input voltages, the switching frequency should be set to a value
less than the fsw(maxshift) frequency. In Equation 13, to calculate the maximum switching frequency, consider that
the output voltage decreases from the nominal voltage to 0 V and that the fdiv integer increases from 1 to 8
corresponding to the frequency shift.
In Figure 40, the solid line indicates a typical, safe operating area in regard to frequency shift. The following
assumptions can be made: the output voltage is 0 V, the resistance of the inductor is 0.1 Ω, the FET onresistance is 0.2 Ω, and the diode voltage drop is 0.5 V. The dashed line indicates the maximum switching
frequency to avoid pulse skipping. Enter these equations in a spreadsheet or software to determine the switching
frequency. Texas Instrument's WEBENCH software tool can also be used to determine the switching frequency.
æ I ´R + V
ö
1
dc
OUT + Vd ÷
´ç L
fSW (max skip ) =
ton(min) ç VIN - IL ´ RDS(on ) + Vd ÷
è
ø
where
•
•
•
•
•
•
ton(min) is the minimum controllable on time
IL is the inductor current
Rdc is the inductor resistance
VOUT is the output voltage
Vd is the diode voltage drop
RDS(on) is the switch on resistance
fSW (shift ) =
(12)
fSW (DIV ) æ IL ´ Rdc + VOUT(SC) + Vd
´ç
ton(min) ç VIN - IL ´ RDS(on ) + Vd
è
ö
÷
÷
ø
where
•
•
ƒDIV is the frequency divide (equal to 1, 2, 4, or 8)
VOUT(sc) is the output voltage during a short
(13)
2500
fs - Switching Frequency - kHz
VO = 3.3 V
2000
Shift
1500
Skip
1000
500
0
10
20
30
VI - Input Voltage - V
40
Figure 40. Maximum Switching Frequency vs. Input Voltage
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Feature Description (continued)
8.3.15 How to Interface to RT/CLK Pin
The RT/CLK pin can be used to synchronize the regulator to an external system clock. To implement the
synchronization feature connect a square wave to the RT/CLK pin through the circuit network shown in
Figure 41. The square wave amplitude must transition lower than 0.5 V and higher than 2.2 V on the RT/CLK pin
and have an on time greater than 40 ns and an off time greater than 40 ns. The synchronization frequency range
is 300 kHz to 2200 kHz. The rising edge of the PH pin synchronizes to the falling edge of RT/CLK signal. The
external synchronization circuit should be designed in such a way that the device has the default-frequency set
resistor connected from the RT/CLK pin to ground if the synchronization signal turns off. Using a frequency set
resistor connected through a 50-Ω resistor to ground is recommended as shown in Figure 41. The resistor should
set the switching frequency close to the external CLK frequency. TI recommends to AC couple the
synchronization signal through a 10-pF ceramic capacitor to the RT/CLK pin and a 4-kΩ series resistor. The
series resistor reduces PH jitter in heavy load applications when synchronizing to an external clock and in
applications which transition from synchronizing to RT mode. The first time the CLK is pulled above the CLK
threshold the device switches from the RT resistor frequency to PLL mode. The internal 0.5-V voltage source is
removed and the CLK pin becomes high impedance as the PLL begins to lock onto the external signal. Because
the regulator has a PLL, the switching frequency can be higher or lower than the frequency set with the external
resistor. The device transitions from the resistor mode to the PLL mode and then increases or decreases the
switching frequency until the PLL locks onto the CLK frequency within 100 ms.
When the device transitions from the PLL to resistor mode, the switching frequency slows down from the CLK
frequency to 150 kHz and then reapplies the 0.5-V voltage. The resistor then sets the switching frequency. The
switching frequency is divided by 1, 2, 4, and 8 as the voltage ramps from 0 to 0.8 V on VSENSE pin. The device
implements a digital frequency shift to enable synchronizing to an external clock during normal startup and fault
conditions. Figure 42, Figure 43 and Figure 44 show the device synchronized to an external system clock in
continuous conduction mode (CCM) discontinuous conduction (DCM) and pulse-skip mode (PSM).
TPS54140
10 pF
4 kW
PLL
Rfset
EXT
Clock
Source
50 W
RT/CLK
Figure 41. Synchronizing to a System Clock
22
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Feature Description (continued)
EXT
EXT
VOUT
IL
PH
PH
IL
Figure 42. Plot of Synchronizing in CCM
Figure 43. Plot of Synchronizing in DCM
EXT
IL
PH
Figure 44. Plot of Synchronizing in PSM
8.3.16 Power Good (PWRGD Pin)
The PWRGD pin is an open drain output. When the VSENSE pin is between 94% and 107% of the internal
voltage reference, the PWRGD pin is deasserted and the pin floats. Using a pullup resistor with a value between
10 and 100 kΩ connected to a voltage source that is 5.5 V or less is recommended. The PWRGD pin is in a
defined state when the VIN input voltage is greater than 1.5 V but has reduced current sinking capability. The
PWRGD achieves full current-sinking capability as the VIN input voltage approaches 3 V.
The PWRGD pin is pulled low when the VSENSE pin is lower than 92% or greater than 109% of the nominal
internal reference voltage. Also, the PWRGD pin is pulled low if the UVLO or thermal shutdown are asserted or
the EN pin is pulled low.
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Feature Description (continued)
8.3.17 Overvoltage Transient Protection
The TPS54140 device incorporates an overvoltage transient-protection (OVTP) circuit to minimize voltage
overshoot when recovering from output-fault conditions or strong unload transients on power-supply designs with
low-value output capacitance. For example, when the power-supply output is overloaded the error amplifier
compares the actual output voltage to the internal reference voltage. If the VSENSE pin voltage is lower than the
internal reference voltage for a considerable time, the output of the error amplifier responds by clamping the error
amplifier output to a high voltage. Thus, requesting the maximum output current. When the condition is removed,
the regulator output rises and the error amplifier output transitions to the steady-state duty cycle. In some
applications, the power-supply output voltage can respond faster than the error-amplifier output can respond
which leads to the possibility of an output overshoot. The OVTP feature minimizes the output overshoot when
using a low-value output capacitor by implementing a circuit to compare the VSENSE pin voltage to OVTP
threshold which is 109% of the internal voltage reference. If the VSENSE pin voltage is greater than the OVTP
threshold, the high-side MOSFET is disabled which prevents current from flowing to the output and minimizing
output overshoot. When the VSENSE voltage drops lower than the OVTP threshold, the high-side MOSFET is
allowed to turn on at the next clock cycle.
8.3.18 Thermal Shutdown
The device implements an internal thermal shutdown to protect the device if the junction temperature exceeds
182°C. The thermal shutdown forces the device to stop switching when the junction temperature exceeds the
thermal trip threshold. When the die temperature decreases below 182°C, the device reinitiates the power-up
sequence by discharging the SS/TR pin.
8.3.19 Small-Signal Model for Loop Response
Figure 45 shows an equivalent model for the TPS54140 control loop which can be modeled in a circuit simulation
program to check frequency response and dynamic load response. The error amplifier is a transconductance
amplifier with a gmEA of 97 μA/V. The error amplifier can be modeled using an ideal voltage-controlled current
source. The resistor, Ro, and capacitor, Co, model the open loop gain and frequency response of the amplifier.
The 1-mV AC voltage source between the nodes a and b effectively breaks the control loop for the frequency
response measurements. Plotting c-a shows the small-signal response of the frequency compensation. Plotting
a-b shows the small-signal response of the overall loop. The dynamic loop response can be checked by
replacing RL with a current source that has the appropriate load-step amplitude and step rate in a time domain
analysis. This equivalent model is only valid for continuous-conduction mode designs.
PH
VO
Power Stage
gmps 6 A/V
a
b
R1
RESR
RL
COMP
c
0.8 V
CO
R3
C2
RO
VSENSE
COUT
gmea
97 mA/V
R2
C1
Figure 45. Small-Signal Model for Loop Response
24
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Feature Description (continued)
8.3.20 Simple Small-Signal Model for Peak-Current Mode Control
Figure 46 describes a simple small-signal model that can be used to understand how to design the frequency
compensation. The TPS54140 power stage can be approximated to a voltage-controlled current source (dutycycle modulator) that supplies current to the output capacitor and load resistor. Equation 14 shows the control to
the output transfer function and consists of a DC gain, one dominant pole, and one ESR zero. The quotient of
the change in the switch current and the change in the COMP pin voltage (node c in Figure 45) is the power
stage transconductance. The gmPS for the TPS54140 device is 6 A/V. The low-frequency gain of the power-stage
frequency response is the product of the transconductance and the load resistance as shown in Equation 15.
As the load current increases and decreases, the low-frequency gain decreases and increases, respectively. This
variation with the load may seem problematic at first glance, but fortunately the dominant pole moves with the
load current (see Equation 16). The combined effect is highlighted by the dashed line in the right half of
Figure 46. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB
crossover frequency the same for the varying load conditions which makes designing the frequency
compensation easier. The type of selected output capacitor determines whether the ESR zero has a profound
effect on the frequency compensation design. Using high ESR aluminum electrolytic capacitors may reduce the
number frequency compensation components needed to stabilize the overall loop because the phase margin
increases from the ESR zero at the lower frequencies (see Equation 17).
VO
Adc
VC
RESR
fp
RL
gmps
COUT
fz
Figure 46. Simple Small-Signal Model and Frequency Response for Peak-Current Mode Control
æ
s
ç1 +
fZ
2
p
´
VOUT
= Adc ´ è
VC
æ
s
ç1 +
2p ´ fP
è
Adc = gmps ´ RL
fP =
ö
÷
ø
ö
÷
ø
(14)
(15)
1
COUT ´ RL ´ 2p
(16)
1
fZ =
COUT ´ RESR ´ 2p
(17)
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Feature Description (continued)
8.3.21 Small-Signal Model for Frequency Compensation
The TPS54140 device uses a transconductance amplifier for the error amplifier and readily supports three of the
commonly-used frequency compensation circuits. Compensation circuits Type 2A, Type 2B, and Type 1 are
shown in Figure 47. Type 2 circuits most likely implemented in high bandwidth power-supply designs using low
ESR output capacitors. The Type 1 circuit is used with power-supply designs with high-ESR aluminum
electrolytic or tantalum capacitors. Equation 18 and Equation 19 show how to relate the frequency response of
the amplifier to the small-signal model in Figure 47. Figure 47 shows the open-loop gain and bandwidth are
modeled using RO and CO. See the Typical Application section for a design example using a Type 2A network
with a low-ESR output capacitor.
Equation 18 through Equation 27 are provided as a reference for those who prefer to compensate using their
preferred methods. Those who prefer to use prescribed method can use the method outlined in the Typical
Application section or use switched information.
VO
R1
VSENSE
gmea
Type 2A
COMP
Type 2B
Type 1
Vref
R2
RO
R3
CO
C2
C1
R3
C2
C1
Figure 47. Types of Frequency Compensation
Aol
A0
P1
Z1
P2
A1
BW
Figure 48. Frequency Response of the Type 2A and Type 2B Frequency Compensation
Ro =
COUT
26
Aol(V/V)
gmea
gmea
=
2p ´ BW (Hz)
(18)
(19)
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Feature Description (continued)
æ
ö
s
ç1 +
÷
2p ´ fZ1 ø
è
EA = A0 ´
æ
ö æ
ö
s
s
ç1 +
÷ ´ ç1 +
÷
2
2
p
´
p
´
f
f
P1 ø è
P2 ø
è
(20)
R2
R1 + R2
R2
´ Ro| | R3 ´
R1 + R2
A0 = gmea ´ Ro ´
A1 = gmea
P1 =
Z1 =
(21)
(22)
1
2p ´ Ro ´ C1
(23)
1
2p ´ R3 ´ C1
(24)
1
P2 =
type 2a
2p ´ R3 | | R ´ (C2 + COUT )
(25)
1
P2 =
type 2b
2p ´ R3 | | R ´ COUT
(26)
P2 =
1
type 1
2p ´ R ´ (C2 + COUT )
(27)
8.4 Device Functional Modes
8.4.1 Pulse Skip Eco-mode
The TPS54140 device enters the pulse-skip mode when the voltage on the COMP pin is the minimum clamp
value. The TPS54140 device operates in a pulse-skip mode at light-load currents to improve efficiency. The peak
switch current during the pulse-skip mode is the greater value of either 50 mA or the peak inductor current that is
a function of the minimum on time, input voltage, output voltage, and inductance value. When the load current is
low and the output voltage is within regulation the device enters a sleep mode and draws only 116-μA input
quiescent current. While the device is in sleep mode the output power is delivered by the output capacitor. As the
load current decreases, the time the output capacitor supplies the load current increases and the switching
frequency decreases reducing gate drive and switching losses. As the output voltage drops, the TPS54140
device wakes up from the sleep mode and the power switch turns on to recharge the output capacitor (see
Figure 49). The internal PLL remains operating when in sleep mode. When operating at light-load currents in the
pulse-skip mode the switching transitions occur synchronously with the external clock signal.
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Device Functional Modes (continued)
VOUT(ac)
IL
PH
Figure 49. Pulse-Skip Mode Operation
8.4.2 Operation With VIN < 3.5 V
The device is recommended to operate with input voltages above 3.5 V. The typical VIN UVLO threshold is not
specified and the device can operate at input voltages down to the UVLO voltage. At input voltages below the
actual UVLO voltage, the device does not switch. If the EN pin is externally pulled up or left floating, the device
becomes active when the VIN pin passes the UVLO threshold. Switching begins when the slow-start sequence is
initiated.
8.4.3 Operation With EN Control
The enable threshold voltage is 1.25 V (typical). With the EN pin is held below that voltage the device is disabled
and switching is inhibited even if the VIN pin is above the UVLO threshold. The IC quiescent current is reduced
in this state. If the EN voltage increases above the threshold while the VIN pin is above the UVLO threshold, the
device becomes active. Switching is enabled, and the slow-start sequence is initiated.
28
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS54140 device is typically used as a step-down converter, which converts a voltage from 3.5 V to 42 V to
a lower voltage. WEBENCH software is available to aid in the design and analysis of circuits.
9.2 Typical Application
L1
10 mH
U1
TPS54140DGQ
BOOT
VIN
C2
C3
C4
2.2 mF 2.2 mF 0.1 mF
R3
EN
SS/TR
RT/CLK
332 kW
CSS
RT
0.01 mF
90.9 kW
R4
61.9 kW
D1
B220A
COMP
VSNS
PWRGD
CF
6.8 pF
COUT
+
47 mF/6.3 V
PH
GND
PwPd
8 - 18 V
3.3 V at 1.5 A
0.1 mF
C1
RC
76.8 kW
CC
2700 pF
R1
31.6 kW
R2
10 kW
Figure 50. High Frequency, 3.3-V Output Power Supply Design With Adjusted UVLO
9.2.1 Design Requirements
For this design example, use the parameters listed in Table 1 as the input parameters.
Table 1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Output voltage
3.3 V
ΔVOUT = 4%
Transient response 0 to 1.5-A load step
Maximum output current
1.5 A
Input voltage
12 V nominal, 8 to 18 V
Output voltage ripple
< 33 mVpp
Start input voltage (rising VIN)
7.7 V
Stop input voltage (falling VIN)
6.7 V
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9.2.2 Detailed Design Procedure
This example details the design of a high-frequency switching-regulator design using ceramic output capacitors.
A few parameters must be known to start the design process. These parameters are typically determined at the
system level.
9.2.2.1 Selecting the Switching Frequency
The first step of the design process is to decide on a switching frequency for the regulator. Typically, the user
selects the highest switching frequency possible because it produces the smallest solution size. The high
switching frequency allows for lower valued inductors and smaller output capacitors compared to a power supply
that switches at a lower frequency. The switching frequency that can be selected is limited by the minimum ontime of the internal power switch, the input voltage, and the output voltage and the frequency shift limitation.
Equation 12 and Equation 13 must be used to find the maximum switching frequency for the regulator. Select the
lower value of the two equations. Switching frequencies higher than these values result in pulse skipping or the
lack of overcurrent protection during a short circuit.
The typical minimum on time, tonmin, is 130 ns for the TPS54140 device. For this example, the output voltage is
3.3 V and the maximum input voltage is 18 V, which allows for a maximum switch frequency up to 1600 kHz
when including the inductor resistance, on resistance, and diode voltage in Equation 12. To ensure that
overcurrent runaway is not a concern during short circuits in the design use Equation 13 or the solid curve in
Figure 40 to determine the maximum switching frequency. The maximum switching frequency is approximately
1600 kHz with a maximum input voltage of 20 V and assuming the following: a diode voltage of 0.5 V, inductor
resistance of 100 mΩ, switch resistance of 200 mΩ, and an output current of 2.8 A.
Selecting the lower of the two values and adding some margin, a switching frequency of 1200 kHz is used. To
determine the timing resistance for a given switching frequency, use Equation 11 or the curve in Figure 38.
The switching frequency is set by resistor Rt shown in Figure 50.
9.2.2.2 Output Inductor Selection (LO)
Use Equation 28 to calculate the minimum value of the output inductor.
VIN(max ) - VOUT
VOUT
´
LO(min ) =
IOUT ´ KIND
VIN(max ) ´ fSW
where
•
KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output
current
(28)
The inductor ripple current is filtered by the output capacitor. Therefore, selecting high inductor ripple currents
impacts the selection of the output capacitor because the output capacitor must have a ripple current rating equal
to or greater than the inductor ripple current. In general, the inductor ripple value is at the discretion of the
designer; however, the following guidelines may be used.
For designs using low-ESR output capacitors such as ceramics, a value as high as KIND = 0.3 can be used.
When using higher ESR output capacitors, KIND = 0.2 yields better results. Because the inductor ripple current is
part of the PWM control system, the inductor ripple current should always be greater than 100 mA for
dependable operation. In a wide input voltage regulator, selecting an inductor ripple current on the larger side is
best which allows the inductor to still have a measurable ripple current with the input voltage at the minimum.
For this design example, use KIND = 0.2 and the minimum inductor value which is calculated as 7.6 μH. For this
design, the nearest standard value of 10 μH was selected. For the output filter inductor, the RMS current and
saturation current ratings must not be exceeded. Use Equation 30 to calculate the inductor ripple current, IRIPPLE.
VOUT ´ (VIN(max ) - VOUT )
IRIPPLE =
VIN(max ) ´ LO ´ fSW
(29)
30
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Use Equation 30 to calculate the RMS inductor current, IL(rms).
(
æ
1 ç VOUT ´ VIN(max ) - VOUT
2
IL(rms ) = (IOUT ) +
´
12 çç
VIN(max ) ´ LO ´ fSW
è
)ö÷
2
÷
÷
ø
(30)
Use Equation 31 to calculate the peak inductor current.
I
IL(peak ) = IOUT + RIPPLE
2
(31)
For this design, the RMS inductor current is 1.506 A and the peak inductor current is 1.62 A. The selected
inductor is a MSS6132-103 and has a saturation current rating of 1.64 A and an RMS current rating of 1.9 A.
As the equation set demonstrates, lower ripple currents reduce the output voltage ripple of the regulator but
require a larger value of inductance. Selecting higher ripple currents increases the output voltage ripple of the
regulator but allows for a lower inductance value.
The current flowing through the inductor is the inductor ripple current plus the output current. During power up,
faults, or transient load conditions, the inductor current can increase above the peak-inductor current level that
was calculated using Equation 31. In transient conditions, the inductor current can increase up to the switch
current limit of the device. For this reason, the most conservative approach is to specify an inductor with a
saturation-current rating equal to or greater than the switch current limit rather than the peak inductor current.
9.2.2.3 Output Capacitor
Consider three primary factors when selecting the value of the output capacitor. The output capacitor determines
the modulator pole, the output voltage ripple, and how the regulator responds to a large change in load current.
The output capacitance must be selected based on the more stringent of these three criteria.
The desired response to a large change in the load current is the first criterion. The output capacitor must supply
the load with current when the regulator cannot. This situation occurs if the desired hold-up times are present for
the regulator. In this case, the output capacitor must hold the output voltage above a certain level for a specified
amount of time after the input power is removed. The regulator is also temporarily unable to supply sufficient
output current if a large, fast increase occurs affecting the current requirements of the load, such as a transition
from no load to full load. The regulator usually requires two or more clock cycles for the control loop to notice the
change in load current and output voltage and to adjust the duty cycle to react to the change. The output
capacitance must be large enough to supply the difference in current for 2 clock cycles while only allowing a
tolerable amount of droop in the output voltage. Use Equation 32 to calculate the minimum output capacitance
required to supply the difference in current.
2 ´ DIOUT
COUT >
fSW ´ DVOUT
where
•
•
•
ΔIOUT is the change in output current
ƒSW is the regulators switching frequency
ΔVOUT is the allowable change in the output voltage
(32)
For this example, the transient load response is specified as a 4% change in VOUT for a load step from 0 A (no
load) to 1.5 A (full load). For this example, ΔIOUT = 1.5 – 0 = 1.5 A and ΔVOUT = 0.04 × 3.3 = 0.132 V. Using
these values results in a minimum capacitance of 18.9 μF. This value does not consider the ESR of the output
capacitor in the output voltage change. For ceramic capacitors, the ESR is usually small enough to ignore in this
calculation. Aluminum electrolytic and tantalum capacitors have higher ESR which should be taken into
consideration.
The catch diode of the regulator cannot sink current and therefore any stored energy in the inductor produces an
output-voltage overshoot when the load current rapidly decreases (see Figure 51). The output capacitor must
also be sized to absorb energy stored in the inductor when transitioning from a high load current to a lower load
current. The excess energy that is stored in the output capacitor increases the voltage on the capacitor. The
capacitor must be sized to maintain the desired output voltage during these transient periods. Use Equation 33 to
calculate the minimum capacitance to keep the output voltage overshoot to a desired value.
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((I ) - (I ) )
´
((V ) - (V ) )
2
2
OH
COUT > LO
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OL
2
f
2
i
where
•
•
•
•
•
L is the value of the inductor
IOH is the output current under heavy load
IOL is the output under light load
Vf is the final peak output voltage
Vi is the initial capacitor voltage
(33)
For this example, the worst-case load step is be from 1.5 A to 0 A. The output voltage increases during this load
transition and the stated maximum in the specification is 4% of the output voltage. Therefore Vf = 1.04 × 3.3 =
3.432. The initial capacitor voltage, Vi, is the nominal output voltage of 3.3 V. Using these values in Equation 33
yields a minimum capacitance of 25.3 μF.
Use Equation 34 to calculate the minimum output capacitance required to meet the output voltage ripple
specification.
1
1
COUT >
´
8 ´ fSW æ VOUT(ripple ) ö
ç
÷
ç IRIPPLE ÷
è
ø
where
•
•
•
ƒSW is the switching frequency
VOUT(ripple) is the maximum allowable output voltage ripple
IRIPPLE is the inductor ripple current
(34)
Equation 35 yields 0.7μF.
Use Equation 35 to calculate the maximum ESR an output capacitor can have to meet the output-voltage ripple
specification. Equation 35 indicates the ESR should be less than 144 mΩ.
VOUT(ripple )
RESR =
IRIPPLE
(35)
The most stringent criterion for the output capacitor is 25.3 μF of capacitance to maintain the output voltage in
regulation during an unload transient.
Additional capacitance deratings for aging, temperature, and DC bias should be considered which increases this
minimum value. For this example, a 47-μF 6.3-V X7R ceramic capacitor with 5 mΩ of ESR is used.
Capacitors generally have limits to the amount of ripple current they can handle without failing or producing
excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor
data sheets specify the root-mean-square (RMS) value of the maximum ripple current. Use Equation 36 to
calculate the RMS ripple current that the output capacitor must support. For this application, Equation 36 yields
66 mA.
ICOUT(rms) =
(
VOUT ´ VIN(max ) - VOUT
)
12 ´ VIN(max ) ´ LO ´ fSW
(36)
9.2.2.4 Catch Diode
The TPS54140 device requires an external catch diode between the PH and GND pins. The selected diode must
have a reverse voltage rating equal to or greater than VIN(max). The peak current rating of the diode must be
greater than the maximum inductor current. The diode should also have a low forward voltage. Schottky diodes
are typically a good choice for the catch diode because of the low forward voltage of these diodes. The lower the
forward voltage of the diode, the higher the efficiency of the regulator will be.
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Typically, the higher the voltage and current ratings of the diode, the higher the forward voltage will be. Because
the design example has an input voltage up to 18 V, a diode with a minimum of 20-V reverse voltage is selected.
For the example design, the B220A Schottky diode is selected because of the lower forward voltage and
because it comes in a larger package size which has good thermal characteristics over small devices. The typical
forward voltage of the B220A is 0.5 V.
The diode must also be selected with an appropriate power rating. The diode conducts the output current during
the off-time of the internal power switch. The off-time of the internal switch is a function of the maximum input
voltage, the output voltage, and the switching frequency. The output current during the off-time is multiplied by
the forward voltage of the diode which equals the conduction losses of the diode. At higher switch frequencies,
the AC losses of the diode must be considered. The AC losses of the diode are because of the charging and
discharging of the junction capacitance and reverse recovery. Use Equation 37 to calculate the total power
dissipation, conduction losses, and AC losses of the diode.
The B220A diode has a junction capacitance of 120 pF. Using Equation 37, the selected diode dissipates 0.632
W. Depending on mounting techniques, this power dissipation should produce a 16°C temperature rise in the
diode when the input voltage is 18 V and the load current is 1.5 A.
If the power supply spends a significant amount of time at light-load currents or in sleep mode, consider using a
diode that has a low leakage current and slightly-higher forward-voltage drop.
PD
(V
=
IN(max ) - VOUT
)´ I
OUT
´ Vf d
VIN(max )
2
C j ´ fSW ´ (VIN + Vf d)
+
2
(37)
9.2.2.5 Input Capacitor
The TPS54140 device requires a high-quality ceramic, type X5R or X7R, input decoupling capacitor with an
effective capacitance value of at least 3 μF and in some applications additional bulk capacitance. The effective
capacitance includes any DC bias effects. The voltage rating of the input capacitor must be greater than the
maximum input voltage. The capacitor must also have a ripple-current rating greater than the maximum input
current ripple of the TPS54140 device. Use Equation 38 to calculate the input ripple current, ICI(rms).
ICI(rms ) = IOUT ´
(
VIN(min ) - VOUT
VOUT
´
VIN(min )
VIN(min )
)
(38)
The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the
capacitor. The capacitance variations because temperature can be minimized by selecting a dielectric material
that is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power-regulator
capacitors because these dielectrics have a high capacitance-to-volume ratio and are fairly stable over
temperature. The output capacitor must also be selected with the DC bias taken into account. The capacitance
value of a capacitor decreases as the DC bias across a capacitor increases.
For this example design, a ceramic capacitor with at least a 20-V voltage rating is required to support the
maximum input voltage. Common standard ceramic-capacitor voltage ratings include 4 V, 6.3 V, 10 V, 16 V, 25
V, 50 V, or 100 V. Therefore, a 25-V capacitor should be selected. For this example, two 2.2-μF, 25-V capacitors
in parallel have been selected. Table 2 lists a selection of high-voltage capacitors. The input capacitance value
determines the input ripple voltage of the regulator. Use Equation 39 to calculate the input voltage ripple.
IOUT(max ) ´ 0.25
DVIN =
CIN ´ fSW
(39)
Using the design example values, IOUT(max) = 1.5 A, CIN = 4.4 μF, ƒSW = 1200 kHz, yields an input voltage ripple
of 71 mV and an RMS input ripple current of 0.701 A.
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Table 2. Capacitor Types
VENDOR
VALUE (μF)
1 to 2.2
Murata
1 to 4.7
1
1 to 2.2
1 to 1.8
Vishay
1 to 1.2
1 to 3.9
1 to 1.8
1 to 2.2
TDK
1.5 to 6.8
1 to 2.2
1 to 3.3
1 to 4.7
AVX
1
1 to 4.7
1 to 2.2
EIA Size
1210
1206
2220
2225
1812
1210
1210
1812
VOLTAGE (V)
DIALECTRIC
100
COMMENTS
GRM32 series
50
100
GRM31 series
50
50
100
VJ X7R series
50
100
100
50
100
50
X7R
C series C4532
C series C3225
50
100
50
X7R dielectric series
100
9.2.2.6 Slow-Start Capacitor
The slow-start capacitor determines the minimum amount of time required for the output voltage to reach the
nominal programmed value during power up which is useful if a load requires a controlled-voltage slew rate. This
feature is also used if the output capacitance is very large and requires large amounts of current to quickly
charge the capacitor to the output voltage level. The large currents required to charge the capacitor may make
the TPS54140 device reach the current limit, or excessive current draw from the input power supply may cause
the input voltage rail to sag. Limiting the output-voltage slew rate solves both of these problems.
The slow-start time must be long enough to allow the regulator to charge the output capacitor up to the output
voltage without drawing excessive current. Use Equation 40 to calculate the minimum slow-start time, tSS,
required to charge the output capacitor, COUT, from 10% to 90% of the output voltage, VOUT, with an average
slow start current of ISS(avg).
´ VOUT ´ 0.8
C
tSS > OUT
ISS(avg)
(40)
In the example, to charge the 47-μF output capacitor up to 3.3 V while only allowing the average input current to
be 0.125 A requires a 1-ms slow-start time.
When the slow-start time is known, the slow-start capacitor value can be calculated using Equation 6. For the
example circuit, the slow-start time is not too critical because the output capacitor value is 47 μF which does not
require much current to charge to 3.3 V. The example circuit has the slow-start time set to an arbitrary value of 1
ms which requires a 3.3-nF capacitor.
9.2.2.7 Bootstrap Capacitor Selection
A 0.1-μF ceramic capacitor must be connected between the BOOT and PH pins for proper operation. Using a
ceramic capacitor with X5R or better grade dielectric is recommended. The capacitor should have a 10-V or
higher voltage rating.
9.2.2.8 Undervoltage-Lockout Set Point
The undervoltage lockout (UVLO) can be adjusted using an external voltage divider on the EN pin of the
TPS54140 device. The UVLO has two thresholds, one for power up when the input voltage is rising and one for
power down or brown outs when the input voltage is falling. For the example design, the supply should turn on
and begin switching when the input voltage increases above 7.7 V (enabled). After the regulator begins
switching, it should continue to do so until the input voltage falls below 6.7 V (UVLO stop).
34
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The programmable UVLO and enable voltages are set using a resistor divider between VIN and ground to the
EN pin. Equation 2 through Equation 3 can be used to calculate the resistance values necessary. For the
example application, a 332 kΩ between VIN and EN and a 61.9 kΩ between EN and ground are required to
produce the 7.7-V and 6.7-V start and stop voltages.
9.2.2.9 Output Voltage and Feedback Resistors Selection
For the example design, a value of 10 kΩ was selected for R2. Using Equation 1, the value of R1 is calculated as
31.25 kΩ. The nearest standard 1% resistor is 31.6 kΩ. Because of the current leakage of the VSENSE pin, the
current flowing through the feedback network should be greater than 1 μA to maintain the output voltage
accuracy. This requirement makes the maximum value of R2 equal to 800 kΩ. Selectinging higher resistor values
decreases quiescent current and improves efficiency at low output currents but may introduce noise immunity
problems.
9.2.2.10 Compensation
Several possible methods exist to design closed loop compensation for DC-DC converters. The method
presented here yields high phase margins. For most conditions, the regulator has a phase margin between 60
and 90 degrees. The method presented here ignores the effects of the slope compensation that is internal to the
TPS54140 device. Because the slope compensation is ignored, the actual crossover frequency is usually lower
than the crossover frequency used in the calculations.
For a more accurate design use the WEBENCH software.
The uncompensated regulator has a dominant pole that is typically located between 300 Hz and 3 kHz because
the output capacitor and load resistance and a pole from the error amplifier. One zero exists because of the
output capacitor and the ESR. The zero frequency is higher than either of the two poles.
If left uncompensated, the double pole created by the error amplifier and the modulator can lead to an unstable
regulator. To stabilize the regulator, one pole must be canceled out. One design approach is to locate a
compensating zero at the modulator pole. Then select a crossover frequency that is higher than the modulator
pole. The gain of the error amplifier can be calculated to achieve the desired crossover frequency. The capacitor
used to create the compensation zero along with the output impedance of the error amplifier form a low
frequency pole to provide a minus-one slope through the crossover frequency. Then a compensating pole is
added to cancel the zero because of the ESR of the output capacitor. If the ESR zero resides at a frequency
higher than the switching frequency then it can be ignored.
To compensate the TPS54140 device using this method, first calculate the modulator pole and zero using the
following equations:
IOUT(max )
fP(mod) =
2 ´ p ´ VOUT ´ COUT
where
•
•
•
IOUT(max) is the maximum output current
VOUT is the nominal output voltage
COUT is the output capacitance
f Z(mod) =
(41)
1
2 ´ p ´ RESR ´ COUT
(42)
For the example design, the modulator pole is located at 1.5 kHz and the ESR zero is located at 338 kHz.
Next, the
crossover
crossover
frequency
designer must select a crossover frequency to determine the bandwidth of the control loop. The
frequency must be located at a frequency at least five times higher than the modulator pole. The
frequency must also be selected so that the available gain of the error amplifier at the crossover
is high enough to allow for proper compensation.
Use Equation 47 to calculate the maximum crossover frequency when the ESR zero is located at a frequency
that is higher than the desired crossover frequency which is usually the case for ceramic or low-ESR tantalum
capacitors. Aluminum Electrolytic and Tantalum capacitors will typically produce a modulator zero at a low
frequency due to their high ESR.
The example application is using a low ESR ceramic capacitor with 10 mΩ of ESR making the zero at 338 kHz.
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This value is much higher than typical crossover frequencies so the maximum crossover frequency is calculated
using both Equation 43 and Equation 46.
Using Equation 46 results in a minimum crossover frequency of 7.6 kHz and Equation 43 results in a maximum
crossover frequency of 45.3 kHz.
A crossover frequency of 45 kHz is arbitrarily selected from this range.
For ceramic capacitors use Equation 43:
fC(max ) £ 2100
fP(mod)
VOUT
(43)
For tantalum or aluminum capacitors use Equation 44:
51442
fC(max ) £
VOUT
For all cases use Equation 45 and Equation 46:
f
fC(max ) £ SW
5
fC(min ) ³ 5 ´ fP(mod)
(44)
(45)
(46)
When a crossover frequency, ƒC, is selected, the gain of the modulator at the crossover frequency is calculated.
Use Equation 47 to calculate the gain of the modulator at the crossover frequency.
gm(PS ) ´ RLOAD ´ (2p ´ fC ´ COUT ´ RESR + 1)
GMOD( f c ) =
2p ´ fC ´ COUT ´ (RLOAD + RESR ) + 1
(47)
For the example problem, the gain of the modulator at the crossover frequency is 0.542. Next, the compensation
components are calculated. A resistor in series with a capacitor is used to create a compensating zero. A
capacitor in parallel to these two components forms the compensating pole. However, calculating the values of
these components varies depending on if the ESR zero is located above or below the crossover frequency. For
ceramic or low-ESR tantalum output capacitors, the zero is usually be located above the crossover frequency.
For aluminum electrolytic and tantalum capacitors, the modulator zero is usually located lower in frequency than
the crossover frequency. For cases where the modulator zero frequency is higher than the crossover frequency
(for example using ceramic capacitors) use Equation 48, Equation 49, and Equation 50 to calculate the RC, CC,
and Cƒ values.
VOUT
RC =
GMOD( f c ) ´ gm(EA ) ´ VREF
(48)
1
CC =
2p ´ RC ´ fP(mod)
(49)
C
´ RESR
Cf = OUT
RC
(50)
For cases where the modulator zero is less than the crossover frequency (Aluminum or Tantalum capacitors), the
equations are as follows:
VOUT
RC =
GMOD( f c ) ´ f Z(mod) ´ gm(EA ) ´ VREF
(51)
1
2p ´ RC ´ fP(mod)
(52)
1
Cf =
2p ´ RC ´ f Z(mod)
(53)
CC =
36
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For the example problem, the ESR zero is located at a higher frequency compared to the crossover frequency so
Equation 48 through Equation 50 are used to calculate the compensation components. For the example problem,
the components are calculated to be: RC = 76.2kΩ, CC = 2710pF, and Cƒ = 6.17pF.
The calculated value of the Cƒ capacitor is not a standard value, so a value of 2700pF is used. A value of 6.8 pF
is used for CC. The RC resistor sets the gain of the error amplifier which determines the crossover frequency. The
calculated value of the RC resistor is not a standard value, so a value of 76.8 kΩ is used.
9.2.2.11 Power Dissipation Estimate
The following formulas show how to estimate the device power dissipation under continuous-conduction mode
(CCM) operation. These equations should not be used if the device is working in discontinuous conduction mode
(DCM).
The power dissipation of the device includes conduction loss (PCOND), switching loss (PSW), gate drive loss (PGD)
and supply current (PQ).
æV
ö
2
PCOND = (IOUT ) ´ RDS(on ) ´ ç OUT ÷
è VIN ø
where
•
•
•
RDS(on) is the on-resistance of the high-side MOSFET (Ω)
VOUT is the output voltage (V)
VIN is the input voltage (V)
(54)
2
PSW = (VIN ) ´ fSW ´ IOUT ´ 0.25 ´ 10-9
where
•
•
IOUT is the output current (A)
ƒSW is the switching frequency (Hz)
PGD = VIN ´ 3 ´ 10
PQ = 116 ´ 10
-6
-9
(55)
´ fSW
(56)
´ VIN
(57)
PTOT = PCOND ´ PSW ´ PGD ´ PQ
where
•
PTOT s the total device power dissipation (W)
(58)
For given TA:
TJ = TA + RTH ´ PTOT
where
•
•
•
TJ is the junction temperature (°C)
TA is the ambient temperature (°C)
RTH is the thermal resistance of the package (°C/W)
(59)
For given TJMAX = 150°C:
TA (max ) = TJ(max ) - RTH ´ PTOT
where
•
•
TA(max) is maximum ambient temperature (°C).
TJ(max) is maximum junction temperature (°C)
(60)
Additional power losses occur in the regulator circuit because of the inductor AC and DC losses, the catch diode,
and trace resistance that impact the overall efficiency of the regulator.
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9.2.3 Application Curves
VIN
VO
VOUT
EN
IO
IL
Figure 51. Load Transmit
Figure 52. Startup With EN
VOUT
VOUT
IL
PH
VIN
IL
Figure 53. VIN Power Up
Figure 54. Output Ripple CCM
VOUT
VOUT
IL
IL
PH
PH
Figure 55. Output Ripple, DCM
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Figure 56. Output Ripple, PSM
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VIN
VIN
IL
IL
PH
PH
Figure 57. Input Ripple CCM
Figure 58. Input Ripple DCM
95
VO = 3.3 V,
fsw = 1200 kHz
VI = 8 V
90
VIN
85
Efficiency - %
80
IL
VI = 12 V
75
VI = 16 V
70
65
PH
60
55
50
0
0.25
Figure 59. Input Ripple PSM
0.50
0.75
1
1.25
IL - Load Current - A
1.5
1.75
2
Figure 60. Efficiency vs Load Current
1.015
60
150
VI = 12 V
1.010
40
100
Phase
0
-50
-100
-20
Phase - o
Gain - dB
0
Gain
Regulation (%)
1.005
50
20
1.000
0.995
0.990
-150
-40
100
1-103
1-104
f - Frequency - Hz
1-105
1-106
0.985
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
Load Current - A
Figure 61. Overall Loop Frequency Response
Figure 62. Regulation vs Load Current
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1.015
IO = 0.5 A
1.010
Regulation (%)
1.005
1.000
0.995
0.990
0.985
5
10
15
20
VI - Input Voltage - V
Figure 63. Regulation vs Input Voltage
10 Power Supply Recommendations
The device is designed to operate from an input-voltage supply range between 3.5 V and 42 V. This input supply
should be well regulated. If the input supply is located more than a few inches from the converter additional bulk
capacitance may be required in addition to the ceramic bypass capacitors. An electrolytic capacitor with a value
of 100 μF is a typical choice.
11 Layout
11.1 Layout Guidelines
Layout is a critical portion of good power-supply design. Several signals paths that conduct fast changing
currents or voltages can interact with stray inductance or parasitic capacitance to generate noise or degrade the
power supplies performance. To help eliminate these problems, the VIN pin should be bypassed to ground with a
low-ESR ceramic bypass capacitor with a X5R- or X7R- dielectric. Care should be taken to minimize the loop
area formed by the bypass capacitor connections, the VIN pin, and the anode of the catch diode. See Figure 64
for a PCB layout example. The GND pin should be tied directly to the thermal pad under the IC and the thermal
pad.
The thermal pad should be connected to any internal PCB ground planes using multiple vias directly under the
IC. The PH pin should be routed to the cathode of the catch diode and to the output inductor. Because the PH
connection is the switching node, the catch diode and output inductor should be located very close to the PH
pins, and the area of the PCB conductor minimized to prevent excessive capacitive coupling. For operation at full
rated load, the top-side ground area must provide adequate heat dissipating area. The RT/CLK pin is sensitive to
noise so the RT resistor should be located as close as possible to the IC and routed with minimal lengths of
trace. The additional external components can be placed approximately as shown. Obtaining acceptable
performance with alternate PCB layouts may be possible, however this layout has been shown to produce good
results and is meant as a guideline.
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11.2 Layout Example
Vout
Output
Capacitor
Topside
Ground
Area
Output
Inductor
Route Boot Capacitor
Trace on another layer to
provide wide path for
topside ground
Input
Bypass
Capacitor
BOOT
Vin
UVLO
Adjust
Resistors
Slow Start
Capacitor
Catch
Diode
PH
VIN
GND
EN
COMP
SS/TR
VSENSE
RT/CLK
PWRGD
Frequency
Set Resistor
Compensation
Network
Resistor
Divider
Thermal VIA
Signal VIA
Figure 64. PCB Layout Example
12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.1.2 Development Support
For the WEBENCH Software Tool, go to www.TI.com/WEBENCH.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
• Designing Type III Compensation for Current Mode Step-Down Converters, SLVA352
• TPS54140EVM-429 1.5-A, SWIFT™ Regulator Evaluation Module, SLVU285
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12.3 Trademarks
Eco-mode, PowerPAD are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
42
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS54140DGQ
ACTIVE
HVSSOP
DGQ
10
80
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 150
54140
TPS54140DGQR
ACTIVE
HVSSOP
DGQ
10
2500
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 150
54140
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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