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TPS54140A
SLVSB55C – MAY 2012 – REVISED OCTOBER 2015
TPS54140A 1.5-A, 42-V Step-Down DC/DC Converter with Eco-mode™
1 Features
3 Description
•
•
•
The TPS54140A device is a 42-V, 1.5-A, step-down
regulator with an integrated high-side MOSFET.
Current-mode control provides simple external
compensation and flexible component selection. A
low ripple-pulse skip mode reduces the no-load,
regulated output supply current to 116 μA. Using the
enable pin, shutdown supply current is reduced to 1.3
μA.
1
•
•
•
•
•
•
•
•
•
•
•
3.5-V to 42-V Input Voltage Range
200-mΩ High-Side MOSFET
High Efficiency at Light Loads with a Pulse
Skipping Eco-mode™
Tighter Enable Threshold than TPS54140 for
More Accurate UVLO Voltage
Adjustable UVLO Voltage and Hysteresis
116-μA Operating Quiescent Current
1.3-μA Shutdown Current
100-kHz to 2.5-MHz Switching Frequency
Synchronizes to External Clock
Adjustable Slow Start/Sequencing
UV and OV Power Good Output
0.8-V Internal Voltage Reference
MSOP10 and 3-mm × 3-mm VSON-10 Package
With PowerPAD™
Supported by WEBENCH® and SwitcherPro™
Software Tool
Undervoltage lockout is internally set at 2.5 V, but
can be increased using the enable pin. The output
voltage startup ramp is controlled by the slow start
pin
that
can
also
be
configured
for
sequencing/tracking. An open drain power good
signal indicates the output is within 94% to 107% of
its nominal voltage.
A wide switching frequency range allows efficiency
and external component size to be optimized.
Frequency fold back and thermal shutdown protects
the part during an overload condition.
Device Information(1)
PART NUMBER
2 Applications
•
•
TPS54140A
12-V and 24-V Industrial and Commercial Low
Power Systems
Aftermarket Auto Accessories: Video, GPS,
Entertainment
SPACE
Simplified Schematic
VIN
3.00 mm × 3.00 mm
90
85
BOOT
PH
RT /CLK
COMP
VSENSE
GND
80
V OUT
Efficiency - %
SS /TR
MSOP (10)
Efficiency vs Load Current
TPS54140A
EN
BODY SIZE (NOM)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
PWRGD
VIN
PACKAGE
VSON (10)
75
70
65
VI = 12 V,
VO = 3.3 V,
fsw = 1200 kHz
60
55
50
0
0.25
0.50
0.75
1
1.25
Load Current - A
1.50
1.75
2
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS54140A
SLVSB55C – MAY 2012 – REVISED OCTOBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
5
5
6
8
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 12
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
12
13
13
17
8
Application and Implementation ........................ 18
8.1 Application Information............................................ 18
8.2 Typical Application ................................................. 25
8.3 System Examples ................................................... 35
9
Power Supply Recommendations...................... 39
9.1 Sequencing ............................................................. 39
10 Layout................................................................... 43
10.1 Layout Guidelines ................................................. 43
10.2 Layout Example .................................................... 43
10.3 Power Dissipation Estimate .................................. 43
11 Device and Documentation Support ................. 45
11.1
11.2
11.3
11.4
11.5
Device Support ....................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
45
45
45
45
45
12 Mechanical, Packaging, and Orderable
Information ........................................................... 45
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (January 2014) to Revision C
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1
Changes from Revision A (July 2012) to Revision B
•
Page
Page
Deleted SWIFT from the data sheet Title and Features ........................................................................................................ 1
Changes from Original (May 2012) to Revision A
Page
•
Changed Description text From: "within 93% to 107% of its nominal voltage." To: "within 94% to 107% of its nominal
voltage." .................................................................................................................................................................................. 1
•
Changed the values of the Hysteresis current in the Electrical Characteristics table ............................................................ 6
•
Changed text in the Slow Start and Tracking Pin (SS/TR) section From: "VIN UVLO is excedded, EN pin pulled
below 1.25V" To: "VIN pin is below the VIN UVLO, EN pin pulled below 1.25V" ................................................................ 20
•
Changed Start Input Voltage (rising VIN) voltage From: 7.25 V To: 7.7 V........................................................................... 25
•
Changed Start Input Voltage (falling VIN) voltage From: 6.25 V To: 6.7 V.......................................................................... 25
•
Changed Equation 11........................................................................................................................................................... 26
•
Changed 7.25V to 7.7V and 6.25V to 6.7V in the Under Voltage Lock Out Set Point section. ........................................... 30
•
Changed Equation 29........................................................................................................................................................... 31
•
Changed Equation 30 and Equation 31 ............................................................................................................................... 31
•
Changed Equation 33........................................................................................................................................................... 32
2
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SLVSB55C – MAY 2012 – REVISED OCTOBER 2015
5 Pin Configuration and Functions
DRC Package
10-Pin VSON
Top View
BOOT 1
DGQ Package
10-Pin MSOP
Top View
BOOT
1
9 GND
VIN
2
8 COMP
EN
3
SS/TR
RT/CLK
10 PH
VIN 2
Thermal
Pad
(11)
EN 3
SS/TR 4
7 VSENSE
RT/CLK 5
6 PWRGD
10
PH
9
GND
8
COMP
4
7
VSENSE
5
6
PWRGD
Thermal
Pad
(11)
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
BOOT
1
O
A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the
minimum required by the device, the output is forced to switch off until the capacitor is refreshed.
COMP
8
O
Error amplifier output, and input to the output switch current comparator. Connect frequency compensation
components to this pin.
EN
3
I
Enable pin, internal pull-up current source. Pull below 1.2V to disable. Float to enable. Adjust the input
undervoltage lockout with two resistors.
GND
9
–
Ground
PH
10
O
The source of the internal high-side power MOSFET.
PWRGD
6
O
An open drain output, asserts low if output voltage is low due to thermal shutdown, dropout, over-voltage or
EN shut down.
Resistor Timing and External Clock. An internal amplifier holds this pin at a fixed voltage when using an
external resistor to ground to set the switching frequency. If the pin is pulled above the PLL upper
threshold, a mode change occurs and the pin becomes a synchronization input. The internal amplifier is
disabled and the pin is a high impedance clock input to the internal PLL. If clocking edges stop, the internal
amplifier is re-enabled and the mode returns to a resistor set function.
RT/CLK
5
I
SS/TR
4
I/O
VIN
2
I
Input supply voltage, 3.5 V to 42 V.
VSENSE
7
I
Inverting node of the transconductance ( gm) error amplifier.
Thermal Pad
11
–
GND pin must be electrically connected to the exposed pad on the printed circuit board for proper
operation.
Slow-start and Tracking. An external capacitor connected to this pin sets the output rise time. Since the
voltage on this pin overrides the internal reference, it can be used for tracking and sequencing.
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SLVSB55C – MAY 2012 – REVISED OCTOBER 2015
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6 Specifications
6.1 Absolute Maximum Ratings (1)
Over operating temperature range (unless otherwise noted).
MIN
MAX
VIN
–0.3
47
EN (2)
–0.3
5
BOOT
Input voltage
55
VSENSE
–0.3
3
COMP
–0.3
3
PWRGD
–0.3
6
SS/TR
–0.3
3
RT/CLK
–0.3
3.6
–0.6
47
–2
47
PH–BOOT
Output voltage
Source current
V
PAD to GND
±200
EN
100
μA
BOOT
100
mA
10
μA
100
μA
100
μA
PWRGD
10
mA
SS/TR
200
μA
VSENSE
PH
Current Limit
RT/CLK
VIN
Sink current
V
8
PH
PH, 10-ns Transient
Voltage Difference
UNIT
A
Current Limit
COMP
mV
A
Operating junction temperature
–40
150
°C
Storage temperature
–65
150
°C
(1)
(2)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
See the Enable and Adjusting Undervoltage Lockout section of this data sheet for details.
6.2 ESD Ratings
VALUE
UNIT
DRC package (VSON)
V(ESD)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±500
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±500
V
DGQ package (MSOP)
V(ESD)
(1)
(2)
4
Electrostatic discharge
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible if necessary precautions are taken.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible if necessary precautions are taken.
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SLVSB55C – MAY 2012 – REVISED OCTOBER 2015
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VIN
Supply input voltage range
3.5
42
V
VO
Output voltage range
0.8
39
V
6.4 Thermal Information
TPS54140A
THERMAL METRIC (1)
DGQ (MSOP)
DRC (VSON)
10 PINS
10 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance (standard board)
52.3
45.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
46.3
51.9
°C/W
RθJB
Junction-to-board thermal resistance
33
20.5
°C/W
ψJT
Junction-to-top characterization parameter
1.6
0.8
°C/W
ψJB
Junction-to-board characterization parameter
32.7
20.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
5.9
5.1
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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TPS54140A
SLVSB55C – MAY 2012 – REVISED OCTOBER 2015
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6.5 Electrical Characteristics
TJ = –40°C to 150°C, VIN = 3.5 to 42 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE (VIN PIN)
Operating input voltage
3.5
42
Internal undervoltage lockout
threshold
No voltage hysteresis, rising and falling
2.5
Shutdown supply current
EN = 0 V, 25°C, 3.5 V ≤ VIN ≤ 42 V
1.3
4
Operating : nonswitching supply
current
VSENSE = 0.83 V, VIN = 12 V, 25°C
116
136
1.25
1.36
V
V
μA
ENABLE AND UVLO (EN PIN)
Enable threshold voltage
Input current
No voltage hysteresis, rising and falling
1.11
Enable threshold +50 mV
–3.8
Enable threshold –50 mV
–0.9
Hysteresis current
V
μA
1.91
2.95
3.99
0.792
0.8
0.808
0.784
0.8
0.816
μA
VOLTAGE REFERENCE
Voltage reference
TJ = 25°C
V
HIGH-SIDE MOSFET
On-resistance
VIN = 3.5 V, BOOT-PH = 3 V
300
VIN = 12 V, BOOT-PH = 6 V
200
410
mΩ
ERROR AMPLIFIER
Input current
50
nA
Error amplifier transconductance (gM) ±2 μA < I(COMP) < 2 μA, V(COMP) = 1 V
97
μS
Error amplifier transconductance (gM) ±2 μA < I(COMP) < 2 μA, V(COMP) = 1 V,
during slow start
VSENSE = 0.4 V
26
μS
Error amplifier dc gain
VSENSE = 0.8 V
Error amplifier bandwidth
Error amplifier source/sink
V(COMP) = 1 V, 100 mV overdrive
COMP to switch current
transconductance
10000
V/V
2700
kHz
±7
μA
6
A/V
CURRENT LIMIT
Current limit threshold
VIN = 12 V, TJ = 25°C
1.8
2.7
A
182
°C
THERMAL SHUTDOWN
Thermal shutdown
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
Switching Frequency Range using
RT mode
fSW
Switching frequency
100
RT = 200 kΩ
450
Switching Frequency Range using
CLK mode
581
300
Minimum CLK pulse width
40
RT/CLK high threshold
1.9
RT/CLK low threshold
0.5
RT/CLK falling edge to PH rising
edge delay
Measured at 500 kHz with RT resistor in series
PLL lock in time
Measured at 500 kHz
2500
kHz
720
kHz
2200
kHz
ns
2.2
V
0.7
V
60
ns
100
μs
SLOW START AND TRACKING (SS/TR)
6
Charge current
VSS/TR = 0.4 V
2
μA
SS/TR-to-VSENSE matching
VSS/TR = 0.4 V
45
mV
SS/TR-to-reference crossover
98% nominal
1.0
V
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Electrical Characteristics (continued)
TJ = –40°C to 150°C, VIN = 3.5 to 42 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SS/TR discharge current (overload)
VSENSE = 0 V, V(SS/TR) = 0.4 V
112
μA
SS/TR discharge voltage
VSENSE = 0 V
54
mV
VSENSE falling
92%
POWER GOOD (PWRGD PIN)
VVSENSE
VSENSE rising
94%
VSENSE rising
109%
VSENSE falling
107%
Hysteresis
VSENSE falling
2%
Output high leakage
VSENSE = VREF, V(PWRGD) = 5.5 V, 25°C
10
nA
On resistance
I(PWRGD) = 3 mA, VSENSE < 0.79 V
50
Ω
Minimum VIN for defined output
V(PWRGD) < 0.5 V, I(PWRGD) = 100 μA
0.95
VSENSE threshold
1.5
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0.816
500
VI = 12 V
VI = 12 V
375
Vref - Voltage Reference - V
RDSON - Static Drain-Source On-State Resistance - mW
6.6 Typical Characteristics
BOOT-PH = 3 V
250
BOOT-PH = 6 V
125
0
-50
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
0.808
0.800
0.792
0.784
-50
150
Figure 1. ON Resistance vs Junction Temperature
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
150
Figure 2. Voltage Reference vs Junction Temperature
3.5
610
VI = 12 V,
RT = 200 kW
VI = 12 V
fs - Switching Frequency - kHz
Switch Current - A
600
3
2.5
590
580
570
560
2
-50
-25
0
25
50
75
100
125
550
-50
150
-25
0
TJ - Junction Temperature - °C
25
50
75
100
TJ - Junction Temperature - °C
125
150
Figure 4. Switching Frequency vs Junction Temperature
Figure 3. Switch Current Limit vs Junction Temperature
500
2500
2000
Switching Frequency (kHz)
fs - Switching Frequency - kHz
VI = 12 V,
TJ = 25°C
1500
1000
500
0
0
25
50
75
100
125
RT/CLK - Resistance - kW
150
175
200
Figure 5. Switching Frequency vs RT/CLK Resistance High
Frequency Range
8
400
300
200
100
0
200
300
400
500 600 700 800 900 1000 1100 1200
RT/CLK Resistance (kW)
C006
Figure 6. Switching Frequency vs RT/CLK Resistance Low
Frequency Range
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Typical Characteristics (continued)
150
40
VI = 12 V
VI = 12 V
130
110
gm - mA/V
gm - mA/V
30
90
20
70
10
-50
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
50
-50
150
-25
0
25
50
75
100
125
150
TJ - Junction Temperature - °C
Figure 7. EA Transconductance During Slow Start vs
Junction Temperature
Figure 8. EA Transconductance vs Junction Temperature
1.40
-3.25
VI = 12 V,
VI(EN) = Threshold +50 mV
VI = 12 V
-3.5
I(EN) - mA
EN - Threshold - V
1.30
-3.75
1.20
-4
1.10
-50
-25
0
25
50
75
100
125
150
TJ - Junction Temperature - °C
-4.25
-50
0
25
50
75
100
125
150
TJ - Junction Temperature - °C
Figure 9. EN Pin Voltage vs Junction Temperature
Figure 10. EN Pin Current vs Junction Temperature
-1
-0.8
VI = 12 V,
VI(EN) = Threshold -50 mV
VI = 12 V
-0.85
-1.5
I(SS/TR) - mA
I(EN) - mA
-25
-0.9
-0.95
-2
-2.5
-1
-50
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
150
Figure 11. EN Pin Current vs Junction Temperature
-3
-50
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
150
Figure 12. SS/TR Charge Current vs Junction Temperature
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Typical Characteristics (continued)
120
100
VI = 12 V
VI = 12 V,
TJ = 25°C
80
% of Nominal fsw
II(SS/TR) - mA
115
110
60
40
105
20
100
-50
0
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
150
0
Figure 13. SS/TR Discharge Current vs Junction
Temperature
0.8
TJ = 25°C
1.5
1.5
I(VIN) - mA
I(VIN) - mA
0.6
2
VI = 12 V
1
0.5
1
0.5
0
-50
0
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
150
Figure 15. Shutdown Supply Current vs Junction
Temperature
0
20
VI - Input Voltage - V
30
40
140
o
TJ = 25 C,
VI(VSENSE) = 0.83 V
VI = 12 V,
VI(VSENSE) = 0.83 V
130
120
120
I(VIN) - mA
130
110
100
90
-50
10
Figure 16. Shutdown Supply Current vs Input Voltage (Vin)
140
I(VIN) - mA
0.4
VSENSE - V
Figure 14. Switching Frequency vs VSENSE
2
110
100
90
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
150
Figure 17. VIN Supply Current vs Junction Temperature
10
0.2
0
20
VI - Input Voltage - V
40
Figure 18. VIN Supply Current vs Input Voltage
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Typical Characteristics (continued)
115
100
VI = 12 V
VI = 12 V
PWRGD Threshold - % of Vref
RDSON - W
80
60
40
20
VSENSE Rising
110
VSENSE Falling
105
100
VSENSE Rising
95
VSENSE Falling
90
0
-50
-25
0
25
50
75
100
125
85
-50
150
-25
0
TJ - Junction Temperature - °C
3
2.3
2.75
2
1.8
1.5
-50
125
150
Figure 20. PWRGD Threshold vs Junction Temperature
2.5
VI(VIN) - V
VI(BOOT-PH) - V
Figure 19. PWRGD ON Resistance vs Junction Temperature
25
50
75
100
TJ - Junction Temperature - °C
2.50
2.25
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
2
-50
150
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
150
Figure 22. Input Voltage (UVLO) vs Junction Temperature
Figure 21. BOOT-PH UVLO vs Junction Temperature
60
500
V(SS/TR) = 0.2 V
VI = 12 V
VI = 12 V,
o
TJ = 25 C
55
400
Offset - mV
Offset - mV
50
300
200
45
40
100
0
0
35
30
-50
100
200
300
400
500
600
700
-25
800
25
50
75
100
125
150
TJ - Junction Temperature - °C
VSENSE - mV
Figure 23. SS/TR to VSENSE Offset vs VSENSE
0
Figure 24. SS/TR to VSENSE Offset vs Temperature
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7 Detailed Description
7.1 Overview
The TPS54140A device is a 42-V, 1.5-A, step-down (buck) regulator with an integrated high side n-channel
MOSFET. To improve performance during line and load transients the device implements a constant frequency,
current mode control which reduces output capacitance and simplifies external frequency compensation design.
The wide switching frequency of 100 kHz to 2500 kHz allows for efficiency and size optimization when selecting
the output filter components. The switching frequency is adjusted using a resistor to ground on the RT/CLK pin.
The device has an internal phase lock loop (PLL) on the RT/CLK pin that is used to synchronize the power
switch turn on to a falling edge of an external system clock.
The TPS54140A has a default start up voltage of approximately 2.5 V. The EN pin has an internal pull-up current
source that can be used to adjust the input voltage under voltage lockout (UVLO) threshold with two external
resistors. In addition, the pull up current provides a default condition. When the EN pin is floating the device will
operate. The operating current is 116 μA when not switching and under no load. When the device is disabled,
the supply current is 1.3 μA.
The integrated 200 mΩ high side MOSFET allows for high efficiency power supply designs capable of delivering
1.5 amperes of continuous current to a load. The TPS54140A reduces the external component count by
integrating the boot recharge diode. The bias voltage for the integrated high side MOSFET is supplied by a
capacitor on the BOOT to PH pin. The boot capacitor voltage is monitored by an UVLO circuit and will turn the
high side MOSFET off when the boot voltage falls below a preset threshold. The TPS54140A can operate at high
duty cycles because of the boot UVLO. The output voltage can be stepped down to as low as the 0.8 V
reference.
The TPS54140A has a power good comparator (PWRGD) which asserts when the regulated output voltage is
less than 92% or greater than 109% of the nominal output voltage. The PWRGD pin is an open drain output
which deasserts when the VSENSE pin voltage is between 94% and 107% of the nominal output voltage
allowing the pin to transition high when a pull-up resistor is used.
The TPS54140A minimizes excessive output overvoltage (OV) transients by taking advantage of the OV power
good comparator. When the OV comparator is activated, the high side MOSFET is turned off and masked from
turning on until the output voltage is lower than 107%.
The SS/TR (slow start and tracking) pin is used to minimize inrush currents or provide power supply sequencing
during power up. A small value capacitor should be coupled to the pin to adjust the slow start time. A resistor
divider can be coupled to the pin for critical power supply sequencing requirements. The SS/TR pin is discharged
before the output powers up. This discharging ensures a repeatable restart after an over-temperature fault,
UVLO fault or a disabled condition.
The TPS54140A, also, discharges the slow start capacitor during overload conditions with an overload recovery
circuit. The overload recovery circuit will slow start the output from the fault voltage to the nominal regulation
voltage once a fault condition is removed. A frequency foldback circuit reduces the switching frequency during
startup and overcurrent fault conditions to help control the inductor current.
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7.2 Functional Block Diagram
PWRGD
6
EN
3
VIN
2
Shutdown
UO
Thermal
Shutdown
Enable
Comparator
Logic
UVLO
Shutdown
Shutdown
Logic
OV
Enable
Threshold
Boot
Charge
Voltage
Reference
Boot
UVLO
Minimum
Clamp
Pulse
Skip
ERROR
AMPLIFIER
Current
Sense
PWM
Comparator
VSENSE 7
1 BOOT
Logic
And
PWM Latch
SS/TR 4
Shutdown
Slope
Compensation
10 PH
COMP 8
Overload
Recovery
Maximum
Clamp
Frequency
Shift
11 POWERPAD
Oscillator
with PLL
9 GND
TPS54140A Block Diagram
5
RT/CLK
7.3 Feature Description
7.3.1 Fixed Frequency PWM Control
The TPS54140A uses an adjustable fixed frequency, peak current mode control. The output voltage is compared
through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives
the COMP pin. An internal oscillator initiates the turn on of the high side power switch. The error amplifier output
is compared to the high side power switch current. When the power switch current reaches the COMP voltage
level the power switch is turned off. The COMP pin voltage will increase and decrease as the output current
increases and decreases. The device implements a current limit by clamping the COMP pin voltage to a
maximum level. The Eco-mode™ is implemented with a minimum clamp on the COMP pin.
7.3.2 Slope Compensation Output Current
The TPS54140A adds a compensating ramp to the switch current signal. This slope compensation prevents subharmonic oscillations. The available peak inductor current remains constant over the full duty cycle range.
7.3.3 Pulse Skip Eco-mode
The TPS54140A enters the pulse skip mode when the voltage on the COMP pin is the minimum clamp value.
The TPS54140A operates in a pulse skip mode at light load currents to improve efficiency. The peak switch
current during the pulse skip mode will be the greater value of 50mA or the peak inductor current that is a
function of the minimum on time, input voltage, output voltage and inductance value. When the load current is
low and the output voltage is within regulation the device will enter a sleep mode and draw only 116 μA input
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Feature Description (continued)
quiescent current. While the device is in sleep mode the output power is delivered by the output capacitor. As the
load current decreases, the time the output capacitor supplies the load current increases and the switching
frequency decreases reducing gate drive and switching losses. As the output voltage drops, the TPS54140A
wakes up from the sleep mode and the power switch turns on to recharge the output capacitor, see Figure 25.
The internal PLL remains operating when in sleep mode. When operating at light load currents in the pulse skip
mode the switching transitions occur synchronously with the external clock signal.
VOUT(ac)
IL
PH
Figure 25. Pulse Skip Mode Operation
7.3.4 Bootstrap Voltage (BOOT)
The TPS54140A has an integrated boot regulator and requires a small ceramic capacitor between the BOOT and
PH pin to provide the gate drive voltage for the high side MOSFET. The value of the ceramic capacitor should be
0.1 μF. A ceramic capacitor with an X7R or X5R grade dielectric is recommended because of the stable
characteristics over temperature and voltage. To improve drop out, the TPS54140A is designed to operate at
100% duty cycle as long as the BOOT to PH pin voltage is greater than 2.1 V. When the voltage from BOOT to
PH drops below 2.1 V, the high side MOSFET is turned off using an UVLO circuit allowing for the low side diode
to conduct which allows refreshing of the BOOT capacitor. Since the supply current sourced from the BOOT
capacitor is low, the high side MOSFET can remain on for more switching cycles than it refreshes, thus, the
effective duty cycle limitation that is attributed to the boot regulator system is high.
7.3.5 Low Dropout Operation
The duty cycle during dropout of the regulator will be mainly determined by the voltage drops across the power
MOSFET, inductor, low side diode and printed circuit board resistance. During operating conditions in which the
input voltage drops, the high side MOSFET can remain on for 100% of the duty cycle to maintain output
regulation or until the BOOT to PH voltage falls below 2.1 V.
Once the high side is off, the low side diode will conduct and the BOOT capacitor will be recharged. During this
boot capacitor recharge time, the inductor current will ramp down until the high side MOSFET turns on. The
recharge time is longer than the typical high side off time of previous switching cycles, and thus, the inductor
current ripple is larger resulting in more ripple voltage on the output. The recharge time is a function of the input
voltage, boot capacitor value, and the impedance of the internal boot recharge diode.
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Feature Description (continued)
Attention needs to be taken in maximum duty cycle applications which experience extended time periods without
a load current. When the voltage across the BOOT capacitors falls below the 2.1-V threshold in applications that
have a difference in the input voltage and output voltage that is less than 3 V, the high side MOSFET will be
turned off but there is not enough current in the inductor to pull the PH pin down to recharge the boot capacitor.
The regulator will not switch because the boot capacitor is less than 2.1 V and the output capacitor will decay
until the difference in the input voltage and output voltage is 2.1 V. At this time the boot under voltage lockout is
exceeded and the device will switch until the desired output voltage is reached.
The start and stop voltages are shown in Figure 26 and Figure 27 for 3.3-V and 5-V applications. The voltages
are plotted versus the load current. The start voltage is defined as the input voltage needed to regulate within
1%. The stop voltage is defined as the input voltage at which the output drops by 5% or stops switching.
4
5.6
VO = 3.3 V
VO = 5 V
5.4
VI - Input Voltage - V
VI - Input Voltage - V
3.8
3.6
Start
3.4
Stop
3.2
5.2
Start
5
Stop
4.8
3
4.6
0
0.05
0.10
IO - Output Current - A
0.15
0.20
0
Figure 26. 3.3-V Start/Stop Voltage
0.05
0.10
IO - Output Current - A
0.15
0.20
Figure 27. 5.0-V Start/Stop Voltage
7.3.6 Error Amplifier
The TPS54140A has a transconductance amplifier for the error amplifier. The error amplifier compares the
VSENSE voltage to the lower of the SS/TR pin voltage or the internal 0.8 V voltage reference. The
transconductance (gm) of the error amplifier is 97 μA/V during normal operation. During the slow start operation,
the transconductance is a fraction of the normal operating gm. When the voltage of the VSENSE pin is below 0.8
V and the device is regulating using the SS/TR voltage, the gm is 25 μA/V.
The frequency compensation components (capacitor, series resistor and capacitor) are added to the COMP pin
to ground.
7.3.7 Voltage Reference
The voltage reference system produces a precise ±2% voltage reference over temperature by scaling the output
of a temperature stable bandgap circuit.
7.3.8 Overload Recovery Circuit
The TPS54140A has an overload recovery (OLR) circuit. The OLR circuit will slow start the output from the
overload voltage to the nominal regulation voltage once the fault condition is removed. The OLR circuit will
discharge the SS/TR pin to a voltage slightly greater than the VSENSE pin voltage using an internal pull down of
100 μA when the error amplifier is changed to a high voltage from a fault condition. When the fault condition is
removed, the output will slow start from the fault voltage to nominal output voltage.
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Feature Description (continued)
7.3.9 Overcurrent Protection and Frequency Shift
The TPS54140A implements current mode control which uses the COMP pin voltage to turn off the high side
MOSFET on a cycle by cycle basis. Each cycle the switch current and COMP pin voltage are compared, when
the peak switch current intersects the COMP voltage, the high side switch is turned off. During overcurrent
conditions that pull the output voltage low, the error amplifier will respond by driving the COMP pin high,
increasing the switch current. The error amplifier output is clamped internally, which functions as a switch current
limit.
To increase the maximum operating switching frequency at high input voltages the TPS54140A implements a
frequency shift. The switching frequency is divided by 8, 4, 2, and 1 as the voltage ramps from 0 to 0.8 volts on
VSENSE pin.
The device implements a digital frequency shift to enable synchronizing to an external clock during normal
startup and fault conditions. Since the device can only divide the switching frequency by 8, there is a maximum
input voltage limit in which the device operates and still have frequency shift protection.
During short-circuit events (particularly with high input voltage applications), the control loop has a finite minimum
controllable on time and the output has a very low voltage. During the switch on time, the inductor current ramps
to the peak current limit because of the high input voltage and minimum on time. During the switch off time, the
inductor would normally not have enough off time and output voltage for the inductor to ramp down by the ramp
up amount. The frequency shift effectively increases the off time allowing the current to ramp down.
7.3.10 Power Good (PWRGD Pin)
The PWRGD pin is an open drain output. Once the VSENSE pin is between 94% and 107% of the internal
voltage reference the PWRGD pin is de-asserted and the pin floats. It is recommended to use a pullup resistor
between the values of 10 and 100kΩ to a voltage source that is 5.5 V or less. The PWRGD is in a defined state
once the VIN input voltage is greater than 1.5 V but with reduced current sinking capability. The PWRGD will
achieve full current sinking capability as VIN input voltage approaches 3 V.
The PWRGD pin is pulled low when the VSENSE is lower than 92% or greater than 109% of the nominal internal
reference voltage. Also, the PWRGD is pulled low, if the UVLO or thermal shutdown are asserted or the EN pin
pulled low.
7.3.11 Overvoltage Transient Protection
The TPS54140A incorporates an overvoltage transient protection (OVTP) circuit to minimize voltage overshoot
when recovering from output fault conditions or strong unload transients on power supply designs with low value
output capacitance. For example, when the power supply output is overloaded the error amplifier compares the
actual output voltage to the internal reference voltage. If the VSENSE pin voltage is lower than the internal
reference voltage for a considerable time, the output of the error amplifier will respond by clamping the error
amplifier output to a high voltage. Thus, requesting the maximum output current. Once the condition is removed,
the regulator output rises and the error amplifier output transitions to the steady state duty cycle. In some
applications, the power supply output voltage can respond faster than the error amplifier output can respond, this
actuality leads to the possibility of an output overshoot. The OVTP feature minimizes the output overshoot, when
using a low value output capacitor, by implementing a circuit to compare the VSENSE pin voltage to OVTP
threshold which is 109% of the internal voltage reference. If the VSENSE pin voltage is greater than the OVTP
threshold, the high side MOSFET is disabled preventing current from flowing to the output and minimizing output
overshoot. When the VSENSE voltage drops lower than the OVTP threshold, the high side MOSFET is allowed
to turn on at the next clock cycle.
7.3.12 Thermal Shutdown
The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 182°C.
The thermal shutdown forces the device to stop switching when the junction temperature exceeds the thermal
trip threshold. Once the die temperature decreases below 182°C, the device reinitiates the power up sequence
by discharging the SS/TR pin.
16
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7.4 Device Functional Modes
7.4.1 Operation with VIN < 3.5 V (Minimum VIN)
The device is recommended to operate with input voltages above 3.5 V. The typical VIN UVLO threshold is 2.5 V
and the device may operate at input voltages down to the UVLO voltage. At input voltages below the actual
UVLO voltage, the device will not switch. The PWRGD output will be controlled once VIN is above 1.5 V
maximum. If EN is externally pulled up to VIN or left floating, when VIN passes the UVLO threshold the device
will become active. Switching is enabled the soft start sequence is initiated. The TPS54140 will start at the soft
start time determined by the external soft start capacitor at the SS/TR pin.
7.4.2 Operation with EN Control
The enable threshold voltage is 1.25 V typical. With EN held below that voltage the device is disabled and
switching is inhibited even if VIN is above its UVLO threshold. The IC quiescent current is reduced in this state. If
the EN voltage is increased above the threshold while VIN is above its UVLO threshold, the device becomes
active. Switching is enabled, and the soft start sequence is initiated. The TPS54140 will start at the soft start time
determined by the external slow start capacitor at the SS/TR pin.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS54140A is a 42-V, 1.5-A, step-down regulator with an integrated high-side MOSFET. This device is
typically used to convert a higher DC voltage to a lower DC voltage with a maximum available output current of
1.5 A. Example applications are 12-V, 24-V and 48-V Industrial, Automotive and Commercial power systems.
Use the following design procedure to select component values for the TPS54140A. This procedure illustrates
the design of a high-frequency switching regulator. The Excel® spreadsheet (SLVC432) located on the product
page can help on all calculations. Alternatively, use the WEBENCH software to generate a complete design. The
WEBENCH software uses an iterative design procedure and accesses a comprehensive database of
components when generating a design.
8.1.1 Adjusting the Output Voltage
The output voltage is set with a resistor divider from the output node to the VSENSE pin. It is recommended to
use 1% tolerance or better divider resistors. Start with a 10 kΩ for the R2 resistor and use the Equation 1 to
calculate R1. To improve efficiency at light loads consider using larger value resistors. If the values are too high
the regulator will be more susceptible to noise and voltage errors from the VSENSE input current will be
noticeable
æ (VOUT - 0.8 V ) ö
R1 = R2 ´ ç
÷
ç
÷
0.8 V
è
ø
(1)
8.1.2 Enable and Adjusting Undervoltage Lockout
The TPS54140A is disabled when the VIN pin voltage falls below 2.5 V. If an application requires a higher
undervoltage lockout (UVLO), use the EN pin as shown in Figure 28 to adjust the input voltage UVLO by using
the two external resistors. Though it is not necessary to use the UVLO adjust registers, for operation providing a
consistent power up behavior is recommended. The EN pin has an internal pull-up current source, I1, of 0.9 μA
that provides the default condition of the TPS54140A operating when the EN pin floats. Once the EN pin voltage
exceeds 1.25 V, an additional 2.9 μA of hysteresis, Ihys, is added. This additional current facilitates input voltage
hysteresis. Use Equation 2 to set the external hysteresis for the input voltage. Use Equation 3 to set the input
start voltage.
TPS54140A
VIN
Ihys
I1
0.9 mA
R1
2.9 mA
+
R2
EN
1.25 V
-
Figure 28. Adjustable Undervoltage Lockout (UVLO)
V
- VSTOP
R1 = START
IHYS
18
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Application Information (continued)
R2 =
VENA
VSTART - VENA
+ I1
R1
(3)
Another technique to add input voltage hysteresis is shown in Figure 29. This method may be used, if the
resistance values are high from the previous method and a wider voltage hysteresis is needed. The resistor R3
sources additional hysteresis current into the EN pin.
TPS54140A
VIN
R1
Ihys
I1
0.9 mA
2.9 mA
+
R2
EN
1.25 V
R3
-
VOUT
Figure 29. Adding Additional Hysteresis
R1 =
R2 =
VSTART - VSTOP
V
IHYS + OUT
R3
(4)
VENA
VSTART - VENA
V
+ I1 - ENA
R1
R3
(5)
Do not place a low-impedance voltage source with greater than 5 V directly on the EN pin. Do not place a
capacitor directly on the EN pin if VEN > 5 V when using a voltage divider to adjust the start and stop voltage.
The node voltage, (see Figure 30) must remain equal to or less than 5.8 V. The zener diode can sink up to 100
µA. The EN pin voltage can be greater than 5 V if the VIN voltage source has a high impedance and does not
source more than 100 µA into the EN pin.
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Application Information (continued)
VIN
R1
Node
ENA
10kohm
R2
5.8V
Figure 30. Node Voltage
8.1.3 Slow Start/Tracking Pin (SS/TR)
The TPS54140A effectively uses the lower voltage of the internal voltage reference or the SS/TR pin voltage as
the power-supply's reference voltage and regulates the output accordingly. A capacitor on the SS/TR pin to
ground implements a slow start time. The TPS54140A has an internal pull-up current source of 2 μA that charges
the external slow start capacitor. The calculations for the slow start time (10% to 90%) are shown in Equation 6.
The voltage reference (VREF) is 0.8 V and the slow start current (ISS) is 2 μA. The slow start capacitor should
remain lower than 0.47 μF and greater than 0.4 7nF.
CSS (nF ) =
tSS (ms )´ ISS (mA )
VREF (V )´ 0.8
(6)
At power up, the TPS54140A will not start switching until the slow start pin is discharged to less than 40 mV to
ensure a proper power up, see Figure 31.
Also, during normal operation, the TPS54140A stops switching and the SS/TR must be discharged to 40 mV
when the voltage at the VIN pin is below the VIN UVLO, EN pin pulled below 1.25 V, or a thermal shutdown
event occurs.
The VSENSE voltage will follow the SS/TR pin voltage with a 45-mV offset up to 85% of the internal voltage
reference. When the SS/TR voltage is greater than 85% on the internal reference voltage the offset increases as
the effective system reference transitions from the SS/TR voltage to the internal voltage reference (see
Figure 23). The SS/TR voltage will ramp linearly until clamped at 1.7 V.
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Application Information (continued)
EN
SS/TR
VSENSE
VOUT
Figure 31. Operation of SS/TR Pin when Starting
8.1.4 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
The switching frequency of the TPS54140A is adjustable over a wide range from approximately 100 kHz to 2500
kHz by placing a resistor on the RT/CLK pin. The RT/CLK pin voltage is typically 0.5 V and must have a resistor
to ground to set the switching frequency. To determine the timing resistance for a given switching frequency, use
Equation 7 or the curves in Figure 32 or Figure 33. To reduce the solution size one would typically set the
switching frequency as high as possible, but tradeoffs of the supply efficiency, maximum input voltage and
minimum controllable on time should be considered.
The minimum controllable on time is typically 130 ns and limits the maximum operating input voltage.
The maximum switching frequency is also limited by the frequency shift circuit. More discussion on the details of
the maximum switching frequency is located below.
206033
RRT (kW ) =
1.0888
fSW (kHz )
(7)
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Application Information (continued)
500
2500
2000
Switching Frequency (kHz)
fs - Switching Frequency - kHz
VI = 12 V,
TJ = 25°C
1500
1000
500
0
0
25
50
75
100
125
150
RT/CLK - Clock Resistance - kW
175
200
Figure 32. Switching Frequency vs RT/CLK Resistance
High Frequency Range
400
300
200
100
0
200
300
400
500 600 700 800 900 1000 1100 1200
RT/CLK Resistance (kW)
C006
Figure 33. Switching Frequency vs RT/CLK Resistance
Low Frequency Range
8.1.5 Selecting the Switching Frequency
The switching frequency that is selected should be the lower value of the two equations, Equation 8 and
Equation 9. Equation 8 is the maximum switching frequency limitation set by the minimum controllable on time.
Setting the switching frequency above this value will cause the regulator to skip switching pulses.
Equation 9 is the maximum switching frequency limit set by the frequency shift protection. To have adequate
output short circuit protection at high input voltages, the switching frequency should be set to be less than the
fsw(maxshift) frequency. In Equation 9, to calculate the maximum switching frequency one must take into
account that the output voltage decreases from the nominal voltage to 0 volts, the fdiv integer increases from 1 to
8 corresponding to the frequency shift.
In Figure 34, the solid line illustrates a typical safe operating area regarding frequency shift and assumes the
output voltage is zero volts, and the resistance of the inductor is 0.1 Ω, FET on resistance of 0.2Ω and the diode
voltage drop is 0.5 V. The dashed line is the maximum switching frequency to avoid pulse skipping. Enter these
equations in a spreadsheet or other software or use the SwitcherPro design software to determine the switching
frequency.
fSW (max skip ) =
fSWshift =
1
tON
æ I ´R + V
dc
OUT + Vd
´ç L
ç VIN - IL ´ RDS(on ) + Vd
è
fDIV æç IL ´ Rdc + VOUT(sc ) + Vd
´
tON ç VIN - IL ´ RDS(on ) + Vd
è
ö
÷
÷
ø
ö
÷
÷
ø
IL
inductor current
Rdc
inductor resistance
VIN
maximum input voltage
VOUT
output voltage
VOUTSC
output voltage during short
Vc
diode voltage drop
RDS(on)
switch on resistance
tON(min)
minimum controllable on time
ƒDIV
frequency divide equals (1, 2, 4, or 8)
22
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Application Information (continued)
2500
fs - Switching Frequency - kHz
VO = 3.3 V
2000
Shift
1500
Skip
1000
500
0
20
30
VI - Input Voltage - V
10
40
Figure 34. Maximum Switching Frequency vs. Input Voltage
8.1.6 How to Interface to RT/CLK Pin
The RT/CLK pin can be used to synchronize the regulator to an external system clock. To implement the
synchronization feature connect a square wave to the RT/CLK pin through the circuit network shown in
Figure 35. The square wave amplitude must transition lower than 0.5 V and higher than 2.2 V on the RT/CLK pin
and have an on time greater than 40 ns and an off time greater than 40 ns. The synchronization frequency range
is 300 kHz to 2200 kHz. The rising edge of the PH will be synchronized to the falling edge of RT/CLK pin signal.
The external synchronization circuit should be designed in such a way that the device will have the default
frequency set resistor connected from the RT/CLK pin to ground should the synchronization signal turn off. It is
recommended to use a frequency set resistor connected as shown in Figure 35 through a 50Ω resistor to
ground. The resistor should set the switching frequency close to the external CLK frequency. It is recommended
to ac couple the synchronization signal through a 10 pF ceramic capacitor to RT/CLK pin and a 4kΩ series
resistor. The series resistor reduces PH jitter in heavy load applications when synchronizing to an external clock
and in applications which transition from synchronizing to RT mode. The first time the CLK is pulled above the
CLK threshold the device switches from the RT resistor frequency to PLL mode. The internal 0.5V voltage source
is removed and the CLK pin becomes high impedance as the PLL starts to lock onto the external signal. Since
there is a PLL on the regulator the switching frequency can be higher or lower than the frequency set with the
external resistor. The device transitions from the resistor mode to the PLL mode and then will increase or
decrease the switching frequency until the PLL locks onto the CLK frequency within 100 microseconds.
When the device transitions from the PLL to resistor mode the switching frequency will slow down from the CLK
frequency to 150 kHz, then reapply the 0.5 V voltage and the resistor will then set the switching frequency. The
switching frequency is divided by 8, 4, 2, and 1 as the voltage ramps from 0 to 0.8 volts on VSENSE pin. The
device implements a digital frequency shift to enable synchronizing to an external clock during normal startup
and fault conditions. Figure 36, Figure 37 and Figure 38 show the device synchronized to an external system
clock in continuous conduction mode (ccm) discontinuous conduction (dcm) and pulse skip mode (psm).
TPS54140A
10 pF
4 kW
PLL
Rfset
EXT
Clock
Source
50 W
RT/CLK
Figure 35. Synchronizing to a System Clock
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Application Information (continued)
EXT
EXT
VOUT
IL
PH
PH
IL
Figure 36. Plot of Synchronizing in CCM
Figure 37. Plot of Synchronizing in DCM
EXT
IL
PH
Figure 38. Plot of Synchronizing in PSM
24
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8.2 Typical Application
L1
10 mH
U1
TPS54140ADGQ
BOOT
VIN
C2
C3
C4
R3
2.2 mF 2.2 mF 0.1 mF
EN
SS/TR
RT/CLK
332 kW
CSS
RT
0.01 mF
90.9 kW
R4
61.9 kW
D1
B220A
COMP
VSNS
PWRGD
CF
6.8 pF
COUT
+
47 mF/6.3 V
PH
GND
PwPd
8 - 18 V
3.3 V at 1.5 A
0.1 mF
C1
RC
76.8 kW
CC
2700 pF
R1
31.6 kW
R2
10 kW
Figure 39. High Frequency, 3.3V Output Power Supply Design with Adjusted UVLO
8.2.1 Design Requirements
This example details the design of a high frequency switching regulator design using ceramic output capacitors.
A few parameters must be known in order to start the design process. These parameters are typically determined
at the system level. For this example, we will start with the following known parameters:
Table 1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Output Voltage
3.3 V
Transient Response 0 to 1.5-A
load step
ΔVout = 4%
Maximum Output Current
1.5 A
Input Voltage
12 V nom. 8V to 18V
Output Voltage Ripple
< 33 mVpp
Start Input Voltage (rising VIN)
7.7 V
Stop Input Voltage (falling VIN)
6.7 V
8.2.2 Detailed Design Procedure
8.2.2.1 Selecting the Switching Frequency
The first step is to decide on a switching frequency for the regulator. Typically, the user will want to choose the
highest switching frequency possible since this will produce the smallest solution size. The high switching
frequency allows for lower valued inductors and smaller output capacitors compared to a power supply that
switches at a lower frequency. The switching frequency that can be selected is limited by the minimum on-time of
the internal power switch, the input voltage and the output voltage and the frequency shift limitation.
Equation 8 and Equation 9 must be used to find the maximum switching frequency for the regulator, choose the
lower value of the two equations. Switching frequencies higher than these values will result in pulse skipping or
the lack of overcurrent protection during a short circuit.
The typical minimum on time, tonmin, is 130 ns for the TPS54140A. For this example, the output voltage is 3.3 V
and the maximum input voltage is 18 V, which allows for a maximum switch frequency up to 1600 kHz when
including the inductor resistance, on resistance and diode voltage in Equation 8. To ensure overcurrent runaway
is not a concern during short circuits in your design use Equation 9 or the solid curve in Figure 34 to determine
the maximum switching frequency. With an maximum input voltage of 20 V, assuming a diode voltage of 0.5V,
inductor resistance of 100 mΩ, switch resistance of 200 mΩ, an output current of 2.8 A, the maximum switching
frequency is approximately 1600kHz.
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Choosing the lower of the two values and adding some margin a switching frequency of 1200kHz is used. To
determine the timing resistance for a given switching frequency, use Equation 7 or the curve in Figure 32.
The switching frequency is set by resistor Rt shown in Figure 39.
8.2.2.2 Output Inductor Selection (LO)
To calculate the minimum value of the output inductor, use Equation 10.
KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current.
The inductor ripple current will be filtered by the output capacitor. Therefore, choosing high inductor ripple
currents will impact the selection of the output capacitor since the output capacitor must have a ripple current
rating equal to or greater than the inductor ripple current. In general, the inductor ripple value is at the discretion
of the designer; however, the following guidelines may be used.
For designs using low ESR output capacitors such as ceramics, a value as high as KIND = 0.3 may be used.
When using higher ESR output capacitors, KIND = 0.2 yields better results. Since the inductor ripple current is
part of the PWM control system, the inductor ripple current should always be greater than 100 mA for
dependable operation. In a wide input voltage regulator, it is best to choose an inductor ripple current on the
larger side. This allows the inductor to still have a measurable ripple current with the input voltage at its
minimum.
For this design example, use KIND = 0.2 and the minimum inductor value is calculated to be 7.6 μH. For this
design, a nearest standard value was chosen: 10 μH. For the output filter inductor, it is important that the RMS
current and saturation current ratings not be exceeded. The RMS and peak inductor current can be found from
Equation 12 and Equation 13.
For this design, the RMS inductor current is 1.506 A and the peak inductor current is 1.62 A. The chosen
inductor is a MSS6132-103. It has a saturation current rating of 1.64 A and an RMS current rating of 1.9 A.
As the equation set demonstrates, lower ripple currents will reduce the output voltage ripple of the regulator but
will require a larger value of inductance. Selecting higher ripple currents will increase the output voltage ripple of
the regulator but allow for a lower inductance value.
The current flowing through the inductor is the inductor ripple current plus the output current. During power up,
faults or transient load conditions, the inductor current can increase above the calculated peak inductor current
level calculated above. In transient conditions, the inductor current can increase up to the switch current limit of
the device. For this reason, the most conservative approach is to specify an inductor with a saturation current
rating equal to or greater than the switch current limit rather than the peak inductor current.
VIN(max ) - VOUT
VOUT
´
LO(min ) =
IOUT ´ KIND
VIN(max ) ´ fSW
(10)
IRIPPLE =
IL(rms ) =
VOUT ´ (VIN(max ) - VOUT )
VIN(max ) ´ LO ´ fSW
(IOUT )
IL(peak ) = IOUT
2
(11)
(
æ
1 ç VOUT ´ VIN(max ) - VOUT
+
´
12 çç
VIN(max ) ´ LO ´ fSW
è
)ö÷
2
÷
÷
ø
I
+ RIPPLE
2
(12)
(13)
8.2.2.3 Output Capacitor
There are three primary considerations for selecting the value of the output capacitor. The output capacitor will
determine the modulator pole, the output voltage ripple, and how the regulators responds to a large change in
load current. The output capacitance needs to be selected based on the more stringent of these three criteria.
26
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The desired response to a large change in the load current is the first criteria. The output capacitor needs to
supply the load with current when the regulator can not. This situation would occur if there are desired hold-up
times for the regulator where the output capacitor must hold the output voltage above a certain level for a
specified amount of time after the input power is removed. The regulator also will temporarily not be able to
supply sufficient output current if there is a large, fast increase in the current needs of the load such as
transitioning from no load to a full load. The regulator usually needs two or more clock cycles for the control loop
to see the change in load current and output voltage and adjust the duty cycle to react to the change. The output
capacitor must be sized to supply the extra current to the load until the control loop responds to the load change.
The output capacitance must be large enough to supply the difference in current for 2 clock cycles while only
allowing a tolerable amount of droop in the output voltage. Equation 14 shows the minimum output capacitance
necessary to accomplish this.
Where ΔIout is the change in output current, ƒsw is the regulators switching frequency and ΔVout is the
allowable change in the output voltage. For this example, the transient load response is specified as a 4%
change in Vout for a load step from 0A (no load) to 1.5 A (full load). For this example, ΔIout = 1.5-0 = 1.5 A and
ΔVout = 0.04 × 3.3 = 0.132 V. Using these numbers gives a minimum capacitance of 18.9 μF. This value does
not take the ESR of the output capacitor into account in the output voltage change. For ceramic capacitors, the
ESR is usually small enough to ignore in this calculation. Aluminum electrolytic and tantalum capacitors have
higher ESR that should be taken into account.
The catch diode of the regulator can not sink current so any stored energy in the inductor will produce an output
voltage overshoot when the load current rapidly decreases, see Figure 40. The output capacitor must also be
sized to absorb energy stored in the inductor when transitioning from a high load current to a lower load current.
The excess energy that gets stored in the output capacitor will increase the voltage on the capacitor. The
capacitor must be sized to maintain the desired output voltage during these transient periods. Equation 15 is
used to calculate the minimum capacitance to keep the output voltage overshoot to a desired value. Where L is
the value of the inductor, IOH is the output current under heavy load, IOL is the output under light load, Vƒ is the
final peak output voltage, and Vi is the initial capacitor voltage. For this example, the worst case load step will be
from 1.5 A to 0 A. The output voltage will increase during this load transition and the stated maximum in our
specification is 4% of the output voltage. This will make Vƒ = 1.04 × 3.3 = 3.432. Vi is the initial capacitor voltage
which is the nominal output voltage of 3.3 V. Using these numbers in Equation 15 yields a minimum capacitance
of 25.3 μF.
Equation 16 calculates the minimum output capacitance needed to meet the output voltage ripple specification.
Where fsw is the switching frequency, Voripple is the maximum allowable output voltage ripple, and Iripple is the
inductor ripple current. Equation 17 yields 0.7 μF.
Equation 17 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple
specification. Equation 17 indicates the ESR should be less than 144mΩ.
The most stringent criteria for the output capacitor is 25.3 μF of capacitance to keep the output voltage in
regulation during an unload transient.
Additional capacitance de-ratings for aging, temperature and dc bias should be factored in which will increase
this minimum value. For this example, a 47 μF 6.3V X7R ceramic capacitor with 5 mΩ of ESR will be used.
Capacitors generally have limits to the amount of ripple current they can handle without failing or producing
excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor
data sheets specify the Root Mean Square (RMS) value of the maximum ripple current. Equation 18 can be used
to calculate the RMS ripple current the output capacitor needs to support. For this application, Equation 18 yields
66mA.
2 ´ DIOUT
COUT >
fSW ´ DVOUT
(14)
COUT > LO ´
((I )
((V )
OH
f
COUT
2
2
)
- (V ) )
- (IOL )2
i
2
(15)
1
1
>
´
8 ´ fSW æ VOUT(ripple ) ö
ç
÷
ç IRIPPLE ÷
è
ø
(16)
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VOUT(ripple )
RESR =
IRIPPLE
ICOUT(rms) =
(17)
(
VOUT ´ VIN(max ) - VOUT
)
12 ´ VIN(max ) ´ LO ´ fSW
(18)
8.2.2.4 Catch Diode
The TPS54140A requires an external catch diode between the PH pin and GND. The selected diode must have
a reverse voltage rating equal to or greater than Vinmax. The peak current rating of the diode must be greater
than the maximum inductor current. The diode should also have a low forward voltage. Schottky diodes are
typically a good choice for the catch diode due to their low forward voltage. The lower the forward voltage of the
diode, the higher the efficiency of the regulator will be.
Typically, the higher the voltage and current ratings the diode has, the higher the forward voltage will be. Since
the design example has an input voltage up to 18 V, a diode with a minimum of 20 V reverse voltage will be
selected.
For the example design, the B220A Schottky diode is selected for its lower forward voltage and it comes in a
larger package size which has good thermal characteristics over small devices. The typical forward voltage of the
B220A is 0.50 volts.
The diode must also be selected with an appropriate power rating. The diode conducts the output current during
the off-time of the internal power switch. The off-time of the internal switch is a function of the maximum input
voltage, the output voltage, and the switching frequency. The output current during the off-time is multiplied by
the forward voltage of the diode which equals the conduction losses of the diode. At higher switch frequencies,
the ac losses of the diode need to be taken into account. The ac losses of the diode are due to the charging and
discharging of the junction capacitance and reverse recovery. Equation 19 is used to calculate the total power
dissipation, conduction losses plus ac losses, of the diode.
The B220A has a junction capacitance of 120 pF. Using Equation 19, the selected diode will dissipate 0.632
Watts. This power dissipation, depending on mounting techniques, should produce a 16°C temperature rise in
the diode when the input voltage is 18V and the load current is 1.5 A.
If the power supply spends a significant amount of time at light load currents or in sleep mode consider using a
diode which has a low leakage current and slightly higher forward voltage drop.
PD
(V
=
IN(max ) - VOUT
)´ I
OUT
VIN(max )
2
´ Vf d
+
C j ´ fSW ´ (VIN + Vf d)
2
(19)
8.2.2.5 Input Capacitor
The TPS54140A requires a high quality ceramic, type X5R or X7R, input decoupling capacitor of at least 3 μF of
effective capacitance and in some applications a bulk capacitance. The effective capacitance includes any dc
bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The
capacitor must also have a ripple current rating greater than the maximum input current ripple of the TPS54140A.
The input ripple current can be calculated using Equation 20.
The value of a ceramic capacitor varies significantly over temperature and the amount of dc bias applied to the
capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that
is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors
because they have a high capacitance to volume ratio and are fairly stable over temperature. The output
capacitor must also be selected with the dc bias taken into account. The capacitance value of a capacitor
decreases as the dc bias across a capacitor increases.
28
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For this example design, a ceramic capacitor with at least a 20 V voltage rating is required to support the
maximum input voltage. Common standard ceramic capacitor voltage ratings include 4 V, 6.3 V, 10 V, 16V, 25 V,
50 V or 100V so a 25 V capacitor should be selected. For this example, two 2.2 μF, 25 V capacitors in parallel
have been selected. Table 2 shows a selection of high voltage capacitors. The input capacitance value
determines the input ripple voltage of the regulator. The input voltage ripple can be calculated using Equation 21.
Using the design example values, Ioutmax = 1.5 A, Cin = 4.4 μF, ƒsw = 1200 kHz, yields an input voltage ripple
of 71 mV and a rms input ripple current of 0.701 A.
ICI(rms ) = IOUT ´
DVIN =
(
VIN(min ) - VOUT
VOUT
´
VIN(min )
VIN(min )
)
(20)
IOUT(max ) ´ 0.25
CIN ´ fSW
(21)
Table 2. Capacitor Types
VENDOR
VALUE (μF)
1.0 to 2.2
Murata
1.0 to 4.7
1.0
1.0 to 2.2
1.0 10 1.8
Vishay
1.0 to 1.2
1.0 to 3.9
1.0 to 1.8
1.0 to 2.2
TDK
1.5 to 6.8
1.0. to 2.2
1.0 to 3.3
1.0 to 4.7
AVX
1.0
1.0 to 4.7
1.0 to 2.2
EIA Size
1210
1206
2220
2225
1812
1210
1210
1812
VOLTAGE
DIALECTRIC
100 V
COMMENTS
GRM32 series
50 V
100 V
GRM31 series
50 V
50 V
100 V
VJ X7R series
50 V
100 V
100 V
50 V
100 V
50 V
X7R
C series C4532
C series C3225
50 V
100 V
50 V
X7R dielectric series
100 V
8.2.2.6 Slow Start Capacitor
The slow start capacitor determines the minimum amount of time it will take for the output voltage to reach its
nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This
is also used if the output capacitance is very large and would require large amounts of current to charge the
capacitor to the output voltage level. The large currents necessary to charge the capacitor may make the
TPS54140A reach the current limit or excessive current draw from the input power supply may cause the input
voltage rail to sag. Limiting the output voltage slew rate solves both of these problems.
The slow start time must be long enough to allow the regulator to charge the output capacitor up to the output
voltage without drawing excessive current. Equation 22 can be used to find the minimum slow start time, tss,
necessary to charge the output capacitor, Cout, from 10% to 90% of the output voltage, Vout, with an average
slow start current of Issavg. In the example, to charge the 47 μF output capacitor up to 3.3 V while only allowing
the average input current to be 0.125 A would require a 1 ms slow start time.
Once the slow start time is known, the slow start capacitor value can be calculated using Equation 6. For the
example circuit, the slow start time is not too critical since the output capacitor value is 47 μF which does not
require much current to charge to 3.3 V. The example circuit has the slow start time set to an arbitrary value of
1ms which requires a 3.3 nF capacitor.
´ VOUT ´ 0.8
C
tSS > OUT
ISS(avg)
(22)
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8.2.2.7 Bootstrap Capacitor Selection
A 0.1-μF ceramic capacitor must be connected between the BOOT and PH pins for proper operation. It is
recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have a 10-V
or higher voltage rating.
8.2.2.8 Undervoltage Lock Out Set Point
The Under Voltage Lock Out (UVLO) can be adjusted using an external voltage divider on the EN pin of the
TPS54140A. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power
down or brown outs when the input voltage is falling. For the example design, the supply should turn on and start
switching once the input voltage increases above 7.7 V (enabled). After the regulator starts switching, it should
continue to do so until the input voltage falls below 6.7 V (UVLO stop).
The programmable UVLO and enable voltages are set using a resistor divider between Vin and ground to the EN
pin. Equation 2 through Equation 3 can be used to calculate the resistance values necessary. For the example
application, a 332 kΩ between Vin and EN and a 61.9 kΩ between EN and ground are required to produce the
7.7 and 6.7 volt start and stop voltages.
8.2.2.9 Output Voltage and Feedback Resistors Selection
For the example design, 10.0 kΩ was selected for R2. Using Equation 1, R1 is calculated as 31.25 kΩ. The
nearest standard 1% resistor is 31.6 kΩ. Due to current leakage of the VSENSE pin, the current flowing through
the feedback network should be greater than 1 μA in order to maintain the output voltage accuracy. This
requirement makes the maximum value of R2 equal to 800 kΩ. Choosing higher resistor values will decrease
quiescent current and improve efficiency at low output currents but may introduce noise immunity problems.
8.2.2.10 Compensation
There are several industry techniques used to compensate DC/DC regulators. The method presented here yields
high phase margins. For most conditions, the regulator will have a phase margin between 60 and 90 degrees.
The method presented here ignores the effects of the slope compensation that is internal to the TPS54140A.
Since the slope compensation is ignored, the actual cross over frequency is usually lower than the cross over
frequency used in the calculations.
Use SwitcherPro software for a more accurate design.
The uncompensated regulator will have a dominant pole, typically located between 300 Hz and 3 kHz, due to the
output capacitor and load resistance and a pole due to the error amplifier. One zero exists due to the output
capacitor and the ESR. The zero frequency is higher than either of the two poles.
If left uncompensated, the double pole created by the error amplifier and the modulator would lead to an unstable
regulator. To stabilize the regulator, one pole must be canceled out. One design approach is to locate a
compensating zero at the modulator pole. Then select a cross over frequency that is higher than the modulator
pole. The gain of the error amplifier can be calculated to achieve the desired cross over frequency. The capacitor
used to create the compensation zero along with the output impedance of the error amplifier form a low
frequency pole to provide a minus one slope through the cross over frequency. Then a compensating pole is
added to cancel the zero due to the output capacitors ESR. If the ESR zero resides at a frequency higher than
the switching frequency then it can be ignored.
To compensate the TPS54140A using this method, first calculate the modulator pole and zero using the following
equations:
IOUT(max )
fP(mod) =
2 ´ p ´ VOUT ´ COUT
where
•
•
•
IOUT(max) is the maximum output current
COUT is the output capacitance
VOUT is the nominal output voltage
f Z(mod) =
30
1
2 ´ p ´ RESR ´ COUT
(23)
(24)
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For the example design, the modulator pole is located at 1.5 kHz and the ESR zero is located at 338 kHz.
Next, the designer needs to select a crossover frequency which will determine the bandwidth of the control loop.
The cross over frequency must be located at a frequency at least five times higher than the modulator pole. The
cross over frequency must also be selected so that the available gain of the error amplifier at the cross over
frequency is high enough to allow for proper compensation.
Equation 29 is used to calculate the maximum cross over frequency when the ESR zero is located at a frequency
that is higher than the desired cross over frequency. This will usually be the case for ceramic or low ESR
tantalum capacitors. Aluminum Electrolytic and Tantalum capacitors will typically produce a modulator zero at a
low frequency due to their high ESR.
The example application is using a low ESR ceramic capacitor with 10 mΩ of ESR making the zero at 338 kHz.
This value is much higher than typical crossover frequencies so the maximum crossover frequency is calculated
using both Equation 25 and Equation 28.
Using Equation 28 gives a minimum crossover frequency of 7.6 kHz and Equation 25 gives a maximum
crossover frequency of 45.3 kHz.
A crossover frequency of 45 kHz is arbitrarily selected from this range.
For ceramic capacitors use Equation 25:
fC(max ) £ 2100
fP(mod)
VOUT
(25)
For tantalum or aluminum capacitors use Equation 26:
51442
fC(max ) £
VOUT
(26)
For all cases use Equation 27 and Equation 28:
f
fC(max ) £ SW
5
fC(min ) ³ 5 ´ fP(mod)
(27)
(28)
Once a cross over frequency, ƒc, has been selected, the gain of the modulator at the cross over frequency is
calculated. The gain of the modulator at the cross over frequency is calculated using Equation 29 .
GMOD( f c ) =
gm(PS ) ´ RLOAD ´ (2p ´ fC ´ COUT ´ RESR + 1)
2p ´ fC ´ COUT ´ (RLOAD + RESR ) + 1
(29)
For the example problem, the gain of the modulator at the cross over frequency is 0.542. Next, the compensation
components are calculated. A resistor in series with a capacitor is used to create a compensating zero. A
capacitor in parallel to these two components forms the compensating pole. However, calculating the values of
these components varies depending on if the ESR zero is located above or below the cross over frequency. For
ceramic or low ESR tantalum output capacitors, the zero will usually be located above the cross over frequency.
For aluminum electrolytic and tantalum capacitors, the modulator zero is usually located lower in frequency than
the cross over frequency. For cases where the modulator zero is higher than the cross over frequency (ceramic
capacitors).
RC =
VOUT
GMOD( f c ) ´ gm(EA ) ´ VREF
(30)
1
CC =
2p ´ RC ´ fP(mod)
(31)
C
´ RESR
Cf = OUT
RC
(32)
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For cases where the modulator zero is less than the cross over frequency (Aluminum or Tantalum capacitors),
the equations are:
RC =
VOUT
GMOD( f c ) ´ f Z(mod) ´ gm(EA ) ´ VREF
(33)
1
CC =
2p ´ RC ´ fP(mod)
(34)
1
Cf =
2p ´ RC ´ f Z(mod)
(35)
For the example problem, the ESR zero is located at a higher frequency compared to the cross over frequency
so Equation 32 through Equation 35 are used to calculate the compensation components. For the example
problem, the components are calculated to be: RC = 76.2 kΩ, CC = 2710 pF, and Cƒ = 6.17 pF.
The calculated value of the Cƒ capacitor is not a standard value so a value of 2700 pF will be used. 6.8 pF is
used for CC. Rc resistor sets the gain of the error amplifier which determines the cross over frequency. The
calculated RC resistor is not a standard value, so 76.8kΩ will be used.
8.2.3 Application Curves
VIN
VO
VOUT
EN
IO
IL
Figure 40. Load Transmit
Figure 41. Startup With EN
VOUT
VOUT
IL
PH
VIN
IL
Figure 42. VIN Power Up
32
Figure 43. Output Ripple CCM
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VOUT
VOUT
IL
IL
PH
PH
Figure 44. Output Ripple, DCM
Figure 45. Output Ripple, PSM
VIN
VIN
IL
IL
PH
PH
Figure 47. Input Ripple DCM
Figure 46. Input Ripple CCM
95
VI = 8 V
90
VO = 3.3 V,
fsw = 1200 kHz
85
VIN
Efficiency - %
80
IL
VI = 12 V
75
VI = 16 V
70
65
PH
60
55
50
0
0.25
0.50
0.75
1
1.25
IL - Load Current - A
1.5
1.75
2
Figure 49. Efficiency vs Load Current
Figure 48. Input Ripple PSM
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1.015
60
150
VI = 12 V
1.010
40
100
Phase
Phase - o
Gain - dB
0
Gain
0
-50
-100
-20
Regulation (%)
1.005
50
20
1.000
0.995
0.990
-150
-40
100
1-103
1-104
f - Frequency - Hz
1-105
0.985
0.00
1-106
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
Load Current - A
Figure 50. Overall Loop Frequency Response
Figure 51. Regulation vs Load Current
1.015
IO = 0.5 A
1.010
Regulation (%)
1.005
1.000
0.995
0.990
0.985
5
10
15
20
VI - Input Voltage - V
Figure 52. Regulation vs Input Voltage
34
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8.3 System Examples
8.3.1 Simple Small Signal Model for Peak Current Mode Control
Figure 53 describes a simple small signal model that can be used to understand how to design the frequency
compensation. The TPS54140A power stage can be approximated to a voltage-controlled current source (duty
cycle modulator) supplying current to the output capacitor and load resistor. The control to output transfer
function is shown in Equation 36 and consists of a dc gain, one dominant pole, and one ESR zero. The quotient
of the change in switch current and the change in COMP pin voltage (node c in Figure 56) is the power stage
transconductance. The gmPS for the TPS54140A is 6 A/V. The low-frequency gain of the power stage frequency
response is the product of the transconductance and the load resistance as shown in Equation 37.
As the load current increases and decreases, the low-frequency gain decreases and increases, respectively. This
variation with the load may seem problematic at first glance, but fortunately the dominant pole moves with the
load current (see Equation 38). The combined effect is highlighted by the dashed line in the right half of
Figure 53. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB
crossover frequency the same for the varying load conditions which makes it easier to design the frequency
compensation. The type of output capacitor chosen determines whether the ESR zero has a profound effect on
the frequency compensation design. Using high ESR aluminum electrolytic capacitors may reduce the number
frequency compensation components needed to stabilize the overall loop because the phase margin increases
from the ESR zero at the lower frequencies (see Equation 39).
VO
Adc
VC
RESR
fp
RL
gmps
COUT
fz
Figure 53. Simple Small Signal Model and Frequency Response for Peak Current Mode Control
æ
s
ç1 +
2p ´ f Z
VOUT
= Adc ´ è
VC
æ
s
ç1 +
2p ´ fP
è
Adc = gmps ´ RL
fP =
ö
÷
ø
ö
÷
ø
(36)
(37)
1
COUT ´ RL ´ 2p
(38)
1
fZ =
COUT ´ RESR ´ 2p
(39)
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System Examples (continued)
8.3.2 Small Signal Model for Frequency Compensation
The TPS54140A uses a transconductance amplifier for the error amplifier and readily supports three of the
commonly-used frequency compensation circuits. Compensation circuits Type 2A, Type 2B, and Type 1 are
shown in Figure 54. Type 2 circuits most likely implemented in high bandwidth power-supply designs using low
ESR output capacitors. The Type 1 circuit is used with power-supply designs with high-ESR aluminum
electrolytic or tantalum capacitors.. Equation 40 and Equation 41 show how to relate the frequency response of
the amplifier to the small signal model in Figure 54. The open-loop gain and bandwidth are modeled using the RO
and CO shown in Figure 54. See Figure 39 for a design example using a Type 2A network with a low ESR output
capacitor.
Equation 40 through Equation 49 are provided as a reference for those who prefer to compensate using the
preferred methods. Those who prefer to use prescribed method use the method outlined in the application
section or use switched information.
VO
R1
VSENSE
gmea
Type 2A
COMP
Type 2B
Type 1
Vref
R2
RO
R3
CO
C2
C1
R3
C2
C1
Figure 54. Types of Frequency Compensation
Aol
A0
P1
Z1
P2
A1
BW
Figure 55. Frequency Response of the Type 2A and Type 2B Frequency Compensation
36
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System Examples (continued)
Ro =
COUT
Aol(V/V)
gmea
gmea
=
2p ´ BW (Hz)
(40)
(41)
æ
ö
s
ç1 +
÷
2
p
´
f
Z1 ø
è
EA = A0 ´
æ
ö æ
ö
s
s
ç1 +
÷ ´ ç1 +
÷
2p ´ fP1 ø è
2p ´ fP2 ø
è
A0 = gmea
A1 = gmea
P1 =
Z1 =
(42)
R2
´ Ro ´
R1 + R2
R2
´ Ro| | R3 ´
R1 + R2
(43)
(44)
1
2p ´ Ro ´ C1
(45)
1
2p ´ R3 ´ C1
(46)
1
P2 =
type 2a
2p ´ R3 | | R ´ (C2 + COUT )
(47)
1
type 2b
2p ´ R3 | | R ´ COUT
(48)
P2 =
1
P2 =
type 1
2p ´ R ´ (C2 + COUT )
(49)
8.3.3 Small Signal Model for Loop Response
Figure 56 shows an equivalent model for the TPS54140A control loop which can be modeled in a circuit
simulation program to check frequency response and dynamic load response. The error amplifier is a
transconductance amplifier with a gmEA of 97 μA/V. The error amplifier can be modeled using an ideal voltage
controlled current source. The resistor Ro and capacitor Co model the open loop gain and frequency response of
the amplifier. The 1mV ac voltage source between the nodes a and b effectively breaks the control loop for the
frequency response measurements. Plotting c/a shows the small signal response of the frequency compensation.
Plotting a/b shows the small signal response of the overall loop. The dynamic loop response can be checked by
replacing RL with a current source with the appropriate load step amplitude and step rate in a time domain
analysis. This equivalent model is only valid for continuous conduction mode designs.
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System Examples (continued)
PH
VO
Power Stage
gmps 6 A/V
a
b
R1
RESR
RL
COMP
c
0.8 V
R3
C2
CO
RO
VSENSE
COUT
gmea
97 mA/V
R2
C1
Figure 56. Small Signal Model for Loop Response
38
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9 Power Supply Recommendations
The devices are designed to operate from an input voltage supply range between 3.5 V and 60 V. This input
supply should be well regulated. If the input supply is located more than a few inches from the TPS54160
converter additional bulk capacitance may be required in addition to the ceramic bypass capacitors. An
electrolytic capacitor with a value of 100 μF is a typical choice
9.1 Sequencing
Many of the common power supply sequencing methods can be implemented using the SS/TR, EN, and
PWRGD pins. The sequential method can be implemented using an open drain output of a power on reset pin of
another device. The sequential method is illustrated in Figure 57 using two TPS54140A devices. The power good
is coupled to the EN pin on the TPS54140A which will enable the second power supply once the primary supply
reaches regulation. If needed, a 1nF ceramic capacitor on the EN pin of the second power supply will provide a
1ms start up delay. Figure 58 shows the results of Figure 57.
SPACE
TPS54140A
EN
PWRGD
EN
EN1
SS /TR
SS /TR
PWRGD1
PWRGD
VOUT1
VOUT2
Figure 57. Schematic for Sequential Start-Up
Sequence
Figure 58. Sequential Startup using EN and
PWRGD
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Sequencing (continued)
TPS54140A
3
EN
EN1, EN2
4
SS/TR
6
PWRGD
VOUT1
VOUT2
TPS54140A
3
EN
4
SS/TR
6
PWRGD
Figure 59. Schematic for Ratiometric Start-Up
Sequence
Figure 60. Ratio-Metric Startup using Coupled
SS/TR pins
Figure 59 shows a method for ratio-metric start up sequence by connecting the SS/TR pins together. The
regulator outputs will ramp up and reach regulation at the same time. When calculating the slow start time the
pullup current source must be doubled in Equation 6. Figure 60 shows the results of Figure 59.
40
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Sequencing (continued)
TPS54140A
EN
VOUT 1
SS/TR
PWRGD
TPS54140A
VOUT 2
EN
R1
SS/ TR
R2
PWRGD
R3
R4
Figure 61. Schematic for Ratiometric and Simultaneous Start-Up Sequence
Ratio-metric and simultaneous power supply sequencing can be implemented by connecting the resistor network
of R1 and R2 shown in Figure 61 to the output of the power supply that needs to be tracked or another voltage
reference source. Using Equation 50 and Equation 51, the tracking resistors can be calculated to initiate the
Vout2 slightly before, after or at the same time as Vout1. Equation 52 is the voltage difference between Vout1
and Vout2 at the 95% of nominal output regulation.
The deltaV variable is zero volts for simultaneous sequencing. To minimize the effect of the inherent SS/TR to
VSENSE offset (Vssoffset) in the slow start circuit and the offset created by the pullup current source (Iss) and
tracking resistors, the Vssoffset and Iss are included as variables in the equations.
To design a ratio-metric start up in which the Vout2 voltage is slightly greater than the Vout1 voltage when Vout2
reaches regulation, use a negative number in Equation 50 through Equation 52 for deltaV. Equation 52 will result
in a positive number for applications which the Vout2 is slightly lower than Vout1 when Vout2 regulation is
achieved.
Since the SS/TR pin must be pulled below 40 mV before starting after an EN, UVLO or thermal shutdown fault,
careful selection of the tracking resistors is needed to ensure the device will restart after a fault. Make sure the
calculated R1 value from Equation 50 is greater than the value calculated in Equation 53 to ensure the device
can recover from a fault.
As the SS/TR voltage becomes more than 85% of the nominal reference voltage the Vssoffset becomes larger
as the slow start circuits gradually handoff the regulation reference to the internal voltage reference. The SS/TR
pin voltage needs to be greater than 1.3 V for a complete handoff to the internal voltage reference as shown in
Figure 23.
V
+ DV VSS(offset )
R1 = OUT2
+
VREF
ISS
(50)
R2 =
VREF ´ R1
VOUT2 + DV - VREF
(51)
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Sequencing (continued)
DV = VOUT1 - VOUT2
R1 > 2800 ´ VOUT1 - 180 ´ DV
(52)
(53)
EN
EN
VOUT1
VOUT1
VOUT2
Figure 62. Ratio-metric Startup with Tracking Resistors
VOUT2
Figure 63. Ratiometric Startup with Tracking Resistors
EN
VOUT1
VOUT2
Figure 64. Simultaneous Startup With Tracking Resistor
42
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10 Layout
10.1 Layout Guidelines
Layout is a critical portion of good power supply design. There are several signals paths that conduct fast
changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise
or degrade the power supplies performance. To help eliminate these problems, the VIN pin should be bypassed
to ground with a low ESR ceramic bypass capacitor with X5R or X7R dielectric. Care should be taken to
minimize the loop area formed by the bypass capacitor connections, the VIN pin, and the anode of the catch
diode. See Figure 65 for a PCB layout example. The GND pin should be tied directly to the power pad under the
IC and the power pad.
The power pad should be connected to any internal PCB ground planes using multiple vias directly under the IC.
The PH pin should be routed to the cathode of the catch diode and to the output inductor. Since the PH
connection is the switching node, the catch diode and output inductor should be located very close to the PH
pins, and the area of the PCB conductor minimized to prevent excessive capacitive coupling. For operation at full
rated load, the top side ground area must provide adequate heat dissipating area. The RT/CLK pin is sensitive to
noise so the RT resistor should be located as close as possible to the IC and routed with minimal lengths of
trace. The additional external components can be placed approximately as shown. It may be possible to obtain
acceptable performance with alternate PCB layouts, however this layout has been shown to produce good
results and is meant as a guideline.
10.2 Layout Example
Vout
Output
Capacitor
Topside
Ground
Area
Route Boot Capacitor
Trace on another layer to
provide wide path for
topside ground
Input
Bypass
Capacitor
BOOT
Vin
UVLO
Adjust
Resistors
Slow Start
Capacitor
Output
Inductor
Catch
Diode
PH
VIN
GND
EN
COMP
SS/TR
VSENSE
RT/CLK
PWRGD
Frequency
Set Resistor
Compensation
Network
Resistor
Divider
Thermal VIA
Signal VIA
Figure 65. PCB Layout Example
10.3 Power Dissipation Estimate
The following formulas show how to estimate the device power dissipation under continuous conduction mode
(CCM) operation. These equations should not be used if the device is working in discontinuous conduction mode
(DCM).
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Power Dissipation Estimate (continued)
The power dissipation of the device includes conduction loss (Pcon), switching loss (Psw), gate drive loss (Pgd)
and supply current (Pq).
æV
ö
2
PCOND = (IOUT ) ´ RDS(on ) ´ ç OUT ÷
è VIN ø
(54)
2
PSW = (VIN ) ´ fSW ´ IOUT ´ 0.25 ´ 10-9
PGD = VIN ´ 3 ´ 10
PQ = 116 ´ 10
-6
-9
´ fSW
(55)
(56)
´ VIN
where
•
•
•
•
•
IOUT is the output current (A)
RDS(on) is the on-resistance of the high-side MOSFET (Ω)
VOUT is the output voltage (V)
VIN is the input voltage (V)
ƒSW is the switching frequency (Hz)
PTOT = PCOND ´ PSW ´ PGD ´ PQ
(57)
(58)
For given TA,
TJ = TA + RTH ´ PTOT
(59)
For given TJMAX = 150°C
TA (max ) = TJ(max ) - RTH ´ PTOT
where
•
•
•
•
•
•
PTOT s the total device power dissipation (W)
TA is the ambient temperature (°C)
TJ is the junction temperature (°C)
RTH is the thermal resistance of the package (°C/W)
TJ(max) is maximum junction temperature (°C)
TA(max) is maximum ambient temperature (°C).
(60)
There are additional power losses in the regulator circuit due to the inductor ac and dc losses, the catch diode
and trace resistance that will impact the overall efficiency of the regulator.
44
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
Eco-mode, PowerPAD, SwitcherPro, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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3-Sep-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS54140ADGQ
ACTIVE
MSOPPowerPAD
DGQ
10
80
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
5414A
TPS54140ADGQR
ACTIVE
MSOPPowerPAD
DGQ
10
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
5414A
TPS54140ADRCR
ACTIVE
VSON
DRC
10
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
5414A
TPS54140ADRCT
ACTIVE
VSON
DRC
10
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
5414A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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3-Sep-2016
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jul-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPS54140ADGQR
MSOPPower
PAD
DGQ
10
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
TPS54140ADGQR
MSOPPower
PAD
DGQ
10
2500
330.0
12.4
5.3
3.3
1.3
8.0
12.0
Q1
TPS54140ADRCR
VSON
DRC
10
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPS54140ADRCR
VSON
DRC
10
3000
330.0
12.4
3.3
3.3
1.0
8.0
12.0
Q2
TPS54140ADRCT
VSON
DRC
10
250
180.0
12.4
3.3
3.3
1.0
8.0
12.0
Q2
TPS54140ADRCT
VSON
DRC
10
250
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jul-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS54140ADGQR
MSOP-PowerPAD
DGQ
10
2500
364.0
364.0
27.0
TPS54140ADGQR
MSOP-PowerPAD
DGQ
10
2500
346.0
346.0
35.0
TPS54140ADRCR
VSON
DRC
10
3000
338.0
355.0
50.0
TPS54140ADRCR
VSON
DRC
10
3000
346.0
346.0
35.0
TPS54140ADRCT
VSON
DRC
10
250
203.0
203.0
35.0
TPS54140ADRCT
VSON
DRC
10
250
338.0
355.0
50.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DRC 10
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4204102-3/M
PACKAGE OUTLINE
DRC0010J
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
A
B
PIN 1 INDEX AREA
3.1
2.9
1.0
0.8
C
SEATING PLANE
0.05
0.00
0.08 C
1.65 0.1
2X (0.5)
EXPOSED
THERMAL PAD
(0.2) TYP
4X (0.25)
5
2X
2
6
11
SYMM
2.4 0.1
10
1
8X 0.5
PIN 1 ID
(OPTIONAL)
10X
SYMM
0.5
10X
0.3
0.30
0.18
0.1
0.05
C A B
C
4218878/B 07/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
DRC0010J
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.65)
(0.5)
10X (0.6)
1
10
10X (0.24)
11
(2.4)
SYMM
(3.4)
(0.95)
8X (0.5)
6
5
(R0.05) TYP
( 0.2) VIA
TYP
(0.25)
(0.575)
SYMM
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218878/B 07/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
DRC0010J
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2X (1.5)
(0.5)
SYMM
EXPOSED METAL
TYP
11
10X (0.6)
1
10
(1.53)
10X (0.24)
2X
(1.06)
SYMM
(0.63)
8X (0.5)
6
5
(R0.05) TYP
4X (0.34)
4X (0.25)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11:
80% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218878/B 07/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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