TPS54319
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SLVSA83 – JUNE 2010
2.95-V to 6-V Input, 3-A Output, 2-MHz, Synchronous Step-Down
Switcher With Integrated FETs ( SWIFT™)
Check for Samples: TPS54319
FEATURES
DESCRIPTION
•
The TPS54319 device is a full featured 6 V, 3 A,
synchronous step down current mode converter with
two integrated MOSFETs.
1
2
•
•
•
•
•
•
•
•
Two 45-mΩ (typical) MOSFETs for High
Efficiency at 3-A Loads
300kHz to 2MHz Switching Frequency
0.8 V ± 3.0% Voltage Reference Over
Temperature (0°C to 85°C)
Synchronizes to External Clock
Adjustable Slow Start/Sequencing
UV and OV Power Good Output
–40°C to 150°C Operating Junction
Temperature Range
Thermally Enhanced 3mm × 3mm 16-pin QFN
Pin Compatible to TPS54318
APPLICATIONS
•
•
Low-Voltage, High-Density Power Systems
Point-of-Load Regulation for Consumer
Applications such as Set Top Boxes, LCD
Displays, CPE Equipment
SIMPLIFIED SCHEMATIC
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The TPS54319 enables small designs by integrating
the MOSFETs, implementing current mode control to
reduce external component count, reducing inductor
size by enabling up to 2 MHz switching frequency,
and minimizing the IC footprint with a small 3mm x
3mm thermally enhanced QFN package.
The TPS54319 provides accurate regulation for a
variety of loads with an accurate ±3.0% Voltage
Reference (VREF) over temperature.
Efficiency is maximized through the integrated 45mΩ
MOSFETs and 360mA typical supply current. Using
the enable pin, shutdown supply current is reduced to
2 µA by entering a shutdown mode.
Under voltage lockout is internally set at 2.6 V, but
can be increased by programming the threshold with
a resistor network on the enable pin. The output
voltage startup ramp is controlled by the slow start
pin. An open drain power good signal indicates the
output is within 93% to 107% of its nominal voltage.
Frequency fold back and thermal shutdown protects
the device during an over-current condition.
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VIN
The TPS54319 is supported in the SwitcherPro™
Software Tool at www.ti.com/switcherpro.
CBOOT
VIN
BOOT
CI
TPS54319
EN
LO
VOUT
PH
CO
For more SWIFTTM documentation, see the TI
website at www.ti.com/swift.
R1
PWRGD
100
GND
AGND
POWERPAD
C ss
RT
R3
C1
R2
80
5 Vin, 1.8 Vout
70
Efficiency - %
SS/TR
RT /CLK
COMP
3.3 Vin,1.8 Vout
90
VSENSE
60
50
40
30
20
10
0
0
0.5
1
1.5
2
2.5
3
Output Current - A
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SWIFT, SwitcherPro are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
TPS54319
SLVSA83 – JUNE 2010
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION (1)
(1)
TJ
PACKAGE
PART NUMBER
–40°C to 150°C
3 × 3 mm QFN
TPS54319RTE
For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI website at www.ti.com
ABSOLUTE MAXIMUM RATINGS (1)
VALUE
Input voltage
MIN
MAX
VIN
–0.3
7
EN
–0.3
7
BOOT
Output voltage
PH + 7
VSENSE
–0.3
3
COMP
–0.3
3
PWRGD
–0.3
7
SS/TR
–0.3
3
RT/CLK
–0.3
6
BOOT-PH
PH 10 ns Transient
Sink current
–0.6
7
–2
10
100
µA
RT/CLK
100
µA
COMP
100
µA
PWRGD
10
mA
100
µA
1
kV
Electrostatic discharge (HBM) QSS 009-105 (JESD22-A114A)
(2)
Electrostatic discharge (CDM) QSS 009-147 (JESD22-C101B.01)
(1)
(2)
2
V
EN
SS/TR
Temperature
V
7
PH
Source current
UNIT
500
V
Tj
–40
150
°C
Tstg
–65
150
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under ELECTRICAL
SPECIFICATIONS is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin. The machine model is a 200-pF
capacitor discharged directly into each pin.
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SLVSA83 – JUNE 2010
THERMAL INFORMATION
TPS54319
THERMAL METRIC (1) (2)
qJA
Junction-to-ambient thermal resistance (standard board)
qJA
Junction-to-ambient thermal resistance (custom board)
yJT
Junction-to-top characterization parameter
0.8
yJB
Junction-to-board characterization parameter
19.2
qJC(top)
Junction-to-case(top) thermal resistance
69.3
qJC(bottom)
Junction-to-case(bottom) thermal resistance
6.2
qJB
Junction-to-board thermal resistance
22
(1)
(2)
(3)
UNITS
RTE (16-PINS)
(3)
51.7
37.0
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Power rating at a specific ambient temperature TA should be determined with a junction temperature of 150°C. This is the point where
distortion starts to substantially increase. See power dissipation estimate in application section of this data sheet for more information.
Test boards conditions:
(a) 2 inches x 2 inches, 4 layers, thickness: 0.062 inch
(b) 2 oz. copper traces located on the top of the PCB
(c) 2 oz. copper ground planes on the 2 internal layers and bottom layer
(d) 4 thermal vias (10mil) located under the device package
ELECTRICAL CHARACTERISTICS
TJ = –40°C to 150°C, VIN = 2.95 to 6 V (unless otherwise noted)
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
6
V
2.6
2.8
V
SUPPLY VOLTAGE (VIN PIN)
Operating input voltage
2.95
Internal under voltage lockout threshold
Shutdown supply current
EN = 0 V, 25°C, 2.95 V ≤ VIN ≤ 6 V
2
5
mA
Quiescent Current - Iq
VSENSE = 0.9 V, VIN = 5 V, 25°C, RT = 400 kΩ
360
575
mA
Rising
1.25
Falling
1.18
Enable threshold + 50 mV
–4.6
Enable threshold – 50 mV
–1.2
ENABLE AND UVLO (EN PIN)
Enable threshold
Input current
V
mA
VOLTAGE REFERENCE (VSENSE PIN)
Voltage Reference
2.95 V ≤ VIN ≤ 6 V, 0°C 2930 ´ Vout1- 145 ´ DV
(8)
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SLVSA83 – JUNE 2010
TPS54319
EN1
VOUT1
EN1
SS/TR1
PWRGD1
SS2
Vout1
TPS54319
EN2
Vout2
VOUT 2
R1
SS/TR2
R2
PWRGD2
Figure 28. Ratio-metric and Simultaneous Startup
Sequence
Figure 29. Ratio-metric Start-Up using Coupled
SS/TR Pins
CONSTANT SWITCHING FREQUENCY and TIMING RESISTOR (RT/CLK Pin)
The switching frequency of the TPS54319 is adjustable over a wide range from 300 kHz to 2000 kHz by placing
a maximum of 700 kΩ and minimum of 85 kΩ, respectively, on the RT/CLK pin. An internal amplifier holds this
pin at a fixed voltage when using an external resistor to ground to set the switching frequency. The RT/CLK is
typically 0.5 V. To determine the timing resistance for a given switching frequency, use the curve in Figure 5 and
Figure 6, or Equation 9.
311890
RT (kW) =
Fsw(kHz)1.0793
(9)
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Fsw(kHz) =
133870
RT(kW)0.9393
(10)
To reduce the solution size one would typically set the switching frequency as high as possible, but tradeoffs of
the efficiency, maximum input voltage and minimum controllable on time should be considered.
The minimum controllable on time is typically 65 ns at full current load and 120 ns at no load, and limits the
maximum operating input voltage or output voltage.
OVERCURRENT PROTECTION
The TPS54319 implements a cycle by cycle current limit. During each switching cycle the high side switch
current is compared to the voltage on the COMP pin. When the instantaneous switch current intersects the
COMP voltage, the high side switch is turned off. During overcurrent conditions that pull the output voltage low,
the error amplifier responds by driving the COMP pin high, increasing the switch current. The error amplifier
output is clamped internally. This clamp functions as a switch current limit.
FREQUENCY SHIFT
To operate at high switching frequencies and provide protection during overcurrent conditions, the TPS54319
implements a frequency shift. If frequency shift was not implemented, during an overcurrent condition the low
side MOSFET may not be turned off long enough to reduce the current in the inductor, causing a current
runaway. With frequency shift, during an overcurrent condition the switching frequency is reduced from 100%,
then 50%, then 25%, then 12.5% as the voltage decreases from 0.827 to 0 volts on VSENSE pin to allow the low
side MOSFET to be off long enough to decrease the current in the inductor. During start-up, the switching
frequency increases as the voltage on VSENSE increases from 0 to 0.827 volts. See Figure 7 for details.
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REVERSE OVERCURRENT PROTECTION
The TPS54319 implements low side current protection by detecting the voltage across the low side MOSFET.
When the converter sinks current through its low side FET, the control circuit turns off the low side MOSFET if
the reverse current is typically more than 2 A. By implementing this additional protection scheme, the converter is
able to protect itself from excessive current during power cycling and start-up into pre-biased outputs.
SYNCHRONIZE USING THE RT/CLK PIN
The RT/CLK pin is used to synchronize the converter to an external system clock. See Figure 30. To implement
the synchronization feature in a system, connect a square wave to the RT/CLK pin with an on time of at least
75ns. If the pin is pulled above the PLL upper threshold, a mode change occurs and the pin becomes a
synchronization input. The internal amplifier is disabled and the pin is a high impedance clock input to the
internal PLL. If clocking edges stop, the internal amplifier is re-enabled and the mode returns to the frequency set
by the resistor. The square wave amplitude at this pin must transition lower than 0.6 V and higher than 1.6 V
typically. The synchronization frequency range is 300 kHz to 2000 kHz. The rising edge of the PH is
synchronized to the falling edge of RT/CLK pin.
TPS54319
SYNC Clock = 2 V / div
PLL
PH = 2 V / div
RT/CLK
Clock
Source
RT
Time = 500 nsec / div
Figure 30. Synchronizing to a System Clock
Figure 31. Plot of Synchronizing to System Clock
POWER GOOD (PWRGD PIN)
The PWRGD pin output is an open drain MOSFET. The output is pulled low when the VSENSE voltage enters
the fault condition by falling below 91% or rising above 107% of the nominal internal reference voltage. There is
a 2% hysteresis on the threshold voltage, so when the VSENSE voltage rises to the good condition above 93%
or falls below 105% of the internal voltage reference the PWRGD output MOSFET is turned off. It is
recommended to use a pull-up resistor between the values of 1kΩ and 100kΩ to a voltage source that is 6 V or
less. The PWRGD is in a valid state once the VIN input voltage is greater than 1.2 V.
OVERVOLTAGE TRANSIENT PROTECTION
The TPS54319 incorporates an overvoltage transient protection (OVTP) circuit to minimize voltage overshoot
when recovering from output fault conditions or strong unload transients. The OVTP feature minimizes the output
overshoot by implementing a circuit to compare the VSENSE pin voltage to the OVTP threshold which is 107%
of the internal voltage reference. If the VSENSE pin voltage is greater than the OVTP threshold, the high side
MOSFET is disabled preventing current from flowing to the output and minimizing output overshoot. When the
VSENSE voltage drops lower than the OVTP threshold the high side MOSFET is allowed to turn on the next
clock cycle.
THERMAL SHUTDOWN
The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 165°C.
The thermal shutdown forces the device to stop switching when the junction temperature exceeds the thermal
trip threshold. Once the die temperature decreases below 150°C, the device reinitiates the power up sequence
by discharging the SS pin to below 40 mV. The thermal shutdown hysteresis is 15°C.
16
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SMALL SIGNAL MODEL FOR LOOP RESPONSE
Figure 32 shows an equivalent model for the TPS54319 control loop which can be modeled in a circuit simulation
program to check frequency response and dynamic load response. The error amplifier is a transconductance
amplifier with a gm of 245 mA/V. The error amplifier can be modeled using an ideal voltage controlled current
source. The resistor Ro and capacitor Co model the open loop gain and frequency response of the amplifier. The
1-mV AC voltage source between the nodes a and b effectively breaks the control loop for the frequency
response measurements. Plotting a/c shows the small signal response of the frequency compensation. Plotting
a/b shows the small signal response of the overall loop. The dynamic loop response can be checked by
replacing the RL with a current source with the appropriate load step amplitude and step rate in a time domain
analysis.
PH
VO
Power Stage
18.0 A/V
a
b
R1
RESR
RL
COMP
c
R3
C2
C1
CO RO
0.827 V
VSENSE
gm
245 µA/V
COUT
R2
Figure 32. Small Signal Model for Loop Response
SIMPLE SMALL SIGNAL MODEL FOR PEAK CURRENT MODE CONTROL
Figure 32 is a simple small signal model that can be used to understand how to design the frequency
compensation. The TPS54319 power stage can be approximated to a voltage controlled current source (duty
cycle modulator) supplying current to the output capacitor and load resistor. The control to output transfer
function is shown in Equation 11 and consists of a dc gain, one dominant pole and one ESR zero. The quotient
of the change in switch current and the change in COMP pin voltage (node c in Figure 32) is the power stage
transconductance. The gm for the TPS54319 is 18.0 A/V. The low frequency gain of the power stage frequency
response is the product of the transconductance and the load resistance as shown in Equation 12. As the load
current increases and decreases, the low frequency gain decreases and increases, respectively. This variation
with load may seem problematic at first glance, but the dominant pole moves with load current [see Equation 13].
The combined effect is highlighted by the dashed line in the right half of Figure 33. As the load current
decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover frequency the same
for the varying load conditions which makes it easier to design the frequency compensation.
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VO
Adc
VC
RESR
fp
RL
gmps
COUT
fz
Figure 33. Simple Small Signal Model and Frequency Response for Peak Current Mode Control
æ
ç 1+
vo
è 2p
= Adc ´
vc
æ
ç 1+
è 2p
ö
s
÷
× ¦z ø
ö
s
÷
× ¦p ø
(11)
Adc = gmps ´ RL
¦p =
C OUT
(12)
1
´ RL ´ 2p
(13)
1
´ RESR ´ 2p
(14)
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¦z =
COUT
SMALL SIGNAL MODEL FOR FREQUENCY COMPENSATION
The TPS54319 uses a transconductance amplifier for the error amplifier and readily supports two of the
commonly used frequency compensation circuits. The compensation circuits are shown in Figure 34. The Type 2
circuits are most likely implemented in high bandwidth power supply designs using low ESR output capacitors. In
Type 2A, one additional high frequency pole is added to attenuate high frequency noise.
VO
R1
VSENSE
COMP
gmea
R2
Vref
RO
CO
5pF
Type 2A
R3
C2
Type 2B
R3
C1
C1
Figure 34. Types of Frequency Compensation
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The design guidelines for TPS54319 loop compensation are as follows:
1. The modulator pole, fpmod, and the esr zero, fz1 must be calculated using Equation 15 and Equation 16.
Derating the output capacitor (COUT) may be needed if the output voltage is a high percentage of the
capacitor rating. Use the capacitor manufacturer information to derate the capacitor value. Use Equation 17
and Equation 18 to estimate a starting point for the crossover frequency, fc. Equation 17 is the geometric
mean of the modulator pole and the esr zero and Equation 18 is the mean of modulator pole and the
switching frequency. Use the lower value of Equation 17 or Equation 18 as the maximum crossover
frequency.
¦ p m od =
Iout m ax
2 p ´ Vout ´ Cout
(15)
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¦ z m od =
1
2 p ´ Resr ´ Cout
(16)
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¦C =
¦p mod ´ ¦ z mod
(17)
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¦C =
¦p mod ´
¦ sw
2
(18)
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2. R3 can be determined by
2p × ¦ c ´ Vo ´ COUT
R3 =
gmea ´ Vref ´ gmps
(19)
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Where is the gmea amplifier gain (245 mA/V), gmps is the power stage gain (18 A/V).
¦p =
3. Place a compensation zero at the dominant pole
R ´ COUT
C1 = L
R3
1
C OUT ´ R L ´ 2 p . C1 can be determined by
(20)
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4. C2 is optional. It can be used to cancel the zero from Co’s ESR.
Resr ´ COUT
C2 =
R3
(21)
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APPLICATION INFORMATION
DESIGN GUIDE – STEP-BY-STEP DESIGN PROCEDURE
This example details the design of a high frequency switching regulator design using ceramic output capacitors.
This design is available as the HPA375 evaluation module (EVM). A few parameters must be known in order to
start the design process. These parameters are typically determined on the system level. For this example, we
start with the following known parameters:
Output Voltage
1.8 V
Transient Response 1 to 2A load step
ΔVout = 5%
Maximum Output Current
3A
Input Voltage
5 V nom. 3 V to 5 V
Output Voltage Ripple
< 30 mV p-p
Switching Frequency (Fsw)
1000 kHz
SELECTING THE SWITCHING FREQUENCY
The first step is to decide on a switching frequency for the regulator. Typically, you want to choose the highest
switching frequency possible since this produces the smallest solution size. The high switching frequency allows
for lower valued inductors and smaller output capacitors compared to a power supply that switches at a lower
frequency. However, the highest switching frequency causes extra switching losses, which hurt the converter’s
performance. The converter is capable of running from 300 kHz to 2 MHz. Unless a small solution size is an
ultimate goal, a moderate switching frequency of 1MHz is selected to achieve both a small solution size and a
high efficiency operation. Using Equation 9, R5 is calculated to be 180 kΩ. A standard 1% 182 kΩ value was
chosen in the design.
Figure 35. High Frequency, 1.8 V Output Power Supply Design with Adjusted UVLO
OUTPUT INDUCTOR SELECTION
The inductor selected works for the entire TPS54319 input voltage range. To calculate the value of the output
inductor, use Equation 22. KIND is a coefficient that represents the amount of inductor ripple current relative to the
maximum output current. The inductor ripple current is filtered by the output capacitor. Therefore, choosing high
inductor ripple currents impacts the selection of the output capacitor since the output capacitor must have a
ripple current rating equal to or greater than the inductor ripple current. In general, the inductor ripple value is at
the discretion of the designer; however, KIND is normally from 0.1 to 0.3 for the majority of applications.
20
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For this design example, use KIND = 0.3 and the inductor value is calculated to be 1.36 mH. For this design, a
nearest standard value was chosen: 1.5 mH. For the output filter inductor, it is important that the RMS current
and saturation current ratings not be exceeded. The RMS and peak inductor current can be found from
Equation 24 and Equation 25.
For this design, the RMS inductor current is 3.01 A and the peak inductor current is 3.72 A. The chosen inductor
is a Coilcraft XLA4020-152ME_. It has a saturation current rating 0f 9.6 A and a RMS current rating of 7.5 A.
The current flowing through the inductor is the inductor ripple current plus the output current. During power up,
faults or transient load conditions, the inductor current can increase above the calculated peak inductor current
level calculated above. In transient conditions, the inductor current can increase up to the switch current limit of
the device. For this reason, the most conservative approach is to specify an inductor with a saturation current
rating equal to or greater than the switch current limit rather than the peak inductor current.
Vinmax - Vout
Vout
´
L1 =
Io ´ Kind
Vinmax ´ ¦ sw
(22)
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Iripple =
Vinmax - Vout
Vout
´
L1
Vinmax ´ ¦ sw
(23)
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ILrms =
Io 2 +
æ Vo ´ (Vinmax - Vo) ö
1
´ ç
÷
12
è Vinmax ´ L1 ´ ¦ sw ø
2
(24)
vertical spacer
ILpeak = Iout +
Iripple
2
(25)
OUTPUT CAPACITOR
There are three primary considerations for selecting the value of the output capacitor. The output capacitor
determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in
load current. The output capacitance needs to be selected based on the more stringent of these three criteria.
The desired response to a large change in the load current is the first criteria. The output capacitor needs to
supply the load with current when the regulator can not. This situation would occur if there are desired hold-up
times for the regulator where the output capacitor must hold the output voltage above a certain level for a
specified amount of time after the input power is removed. The regulator is temporarily not able to supply
sufficient output current if there is a large, fast increase in the current needs of the load such as transitioning
from no load to a full load. The regulator usually needs two or more clock cycles for the control loop to see the
change in load current and output voltage and adjust the duty cycle to react to the change. The output capacitor
must be sized to supply the extra current to the load until the control loop responds to the load change. The
output capacitance must be large enough to supply the difference in current for 2 clock cycles while only allowing
a tolerable amount of droop in the output voltage. Equation 26 shows the minimum output capacitance necessary
to accomplish this.
For this example, the transient load response is specified as a 5 % change in Vout for a load step from 0 A (no
load) to 1.5 A (50% load). For this example, ΔIout = 1.5-0 = 1.5 A and ΔVout= 0.05 × 1.8 = 0.090 V. Using these
numbers gives a minimum capacitance of 33 mF. This value does not take the ESR of the output capacitor into
account in the output voltage change. For ceramic capacitors, the ESR is usually small enough to ignore in this
calculation.
Equation 27 calculates the minimum output capacitance needed to meet the output voltage ripple specification.
Where fsw is the switching frequency, Vripple is the maximum allowable output voltage ripple, and Iripple is the
inductor ripple current. In this case, the maximum output voltage ripple is 30 mV. Under this requirement,
Equation 27 yields 2.3 uF.
vertical spacer
2 ´ DIout
Co >
¦ sw ´ DVout
(26)
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vertical spacer
Co >
1
´
8 ´ ¦ sw
1
Voripple
Iripple
Where ΔIout is the change in output current, Fsw is the regulators switching frequency and ΔVout is the
allowable change in the output voltage.
(27)
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Equation 28 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple
specification. Equation 28 indicates the ESR should be less than 55 mΩ. In this case, the ESR of the ceramic
capacitor is much less than 55 mΩ.
Additional capacitance de-ratings for aging, temperature and DC bias should be factored in which increases this
minimum value. For this example, two 22 mF 10 V X5R ceramic capacitors with 3 mΩ of ESR are used.
Capacitors generally have limits to the amount of ripple current they can handle without failing or producing
excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor
data sheets specify the RMS (Root Mean Square) value of the maximum ripple current. Equation 29 can be used
to calculate the RMS ripple current the output capacitor needs to support. For this application, Equation 29 yields
333 mA.
Voripple
Resr <
Iripple
(28)
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Icorm s =
Vout ´ (Vinm ax - Vout)
12 ´ Vinm ax ´ L1 ´ ¦ sw
(29)
INPUT CAPACITOR
The TPS54319 requires a high quality ceramic, type X5R or X7R, input decoupling capacitor of at least 4.7 mF of
effective capacitance and in some applications a bulk capacitance. The effective capacitance includes any DC
bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The
capacitor must also have a ripple current rating greater than the maximum input current ripple of the TPS54319.
The input ripple current can be calculated using Equation 30.
The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the
capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that
is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors
because they have a high capacitance to volume ratio and are fairly stable over temperature. The output
capacitor must also be selected with the DC bias taken into account. The capacitance value of a capacitor
decreases as the DC bias across a capacitor increases.
For this example design, a ceramic capacitor with at least a 10 V voltage rating is required to support the
maximum input voltage. For this example, one 10 mF and one 0.1 mF 10 V capacitors in parallel have been
selected. The input capacitance value determines the input ripple voltage of the regulator. The input voltage
ripple can be calculated using Equation 31. Using the design example values, Ioutmax=3 A, Cin=10 mF, Fsw=1
MHz, yields an input voltage ripple of 76 mV and a rms input ripple current of 1.47 A.
Icirms = Iout ´
Vout
´
Vinmin
(Vinmin
- Vout )
Vinmin
vertical spacer
Ioutmax ´ 0.25
DVin =
Cin ´ ¦ sw
(30)
(31)
SLOW START CAPACITOR
The slow start capacitor determines the minimum amount of time it takes for the output voltage to reach its
22
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nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This
is also used if the output capacitance is very large and would require large amounts of current to quickly charge
the capacitor to the output voltage level. The large currents necessary to charge the capacitor may make the
TPS54319 reach the current limit or excessive current draw from the input power supply may cause the input
voltage rail to sag. Limiting the output voltage slew rate solves both of these problems.
The slow start capacitor value can be calculated using Equation 32. For the example circuit, the slow start time is
not too critical since the output capacitor value is 44 mF which does not require much current to charge to 1.8 V.
The example circuit has the slow start time set to an arbitrary value of 4ms which requires a 10 nF capacitor. In
TPS54319, Iss is 2.2 mA and Vref is 0.827 V.
Tss(ms) ´ Iss(mA)
Css(nF) =
Vref(V)
(32)
BOOTSTRAP CAPACITOR SELECTION
A 0.1 mF ceramic capacitor must be connected between the BOOT to PH pin for proper operation. It is
recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have 10 V or
higher voltage rating.
OUTPUT VOLTAGE AND FEEDBACK RESISTORS SELECTION
For the example design, 100 kΩ was selected for R6. Using Equation 33, R7 is calculated as 80 kΩ. The nearest
standard 1% resistor is 80.5 kΩ.
Vref
R7 =
R6
Vo - Vref
(33)
Due to the internal design of the TPS54319, there is a minimum output voltage limit for any given input voltage.
The output voltage can never be lower than the internal voltage reference of 0.827 V. Above 0.827 V, the output
voltage may be limited by the minimum controllable on time. The minimum output voltage in this case is given by
Equation 34
Voutmin = Ontimemin ´ Fsmax ´ (Vinmax - Ioutmin ´ 2 ´ RDS ) - Ioutmin ´ (RL + RDS )
Where:
Voutmin = minimum achievable output voltage
Ontimemin = minimum controllable on-time (65 ns typical. 120 nsec no load)
Fsmax = maximum switching frequency including tolerance
Vinmax = maximum input voltage
Ioutmin = minimum load current
RDS = minimum high side MOSFET on resistance (45 - 64 mΩ)
RL = series resistance of output inductor
(34)
There is also a maximum achievable output voltage which is limited by the minimum off time. The maximum
output voltage is given by Equation 35
Voutmax = (1 - Offtimemax ´ Fsmax )´ (Vinmin - Ioutmax ´ 2 ´ RDS ) - Ioutmax ´ (RL + RDS )
Where:
Voutmax = maximum achievable output voltage
Offtimeman = maximum off time (60 nsec typical)
Fsmax = maximum switching frequency including tolerance
Vinmin = minimum input voltage
Ioutmax = maximum load current
RDS = maximum high side MOSFET on resistance (81 - 110 mΩ)
RL = series resistance of output inductor
(35)
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COMPENSATION
There are several industry techniques used to compensate DC/DC regulators. The method presented here is
easy to calculate and yields high phase margins. For most conditions, the regulator has a phase margin between
60 and 90 degrees. The method presented here ignores the effects of the slope compensation that is internal to
the TPS54319. Since the slope compensation is ignored, the actual cross over frequency is usually lower than
the cross over frequency used in the calculations. Use SwitcherPro software for a more accurate design.
To get started, the modulator pole, fpmod, and the esr zero, fz1 must be calculated using Equation 36 and
Equation 37. For Cout, derating the capacitor is not needed as the 1.8 V output is a small percentage of the 10 V
capacitor rating. If the output is a high percentage of the capacitor rating, use the capacitor manufacturer
information to derate the capacitor value. Use Equation 38 and Equation 39 to estimate a starting point for the
crossover frequency, fc. For the example design, fpmod is 6.03 kHz and fzmod is 1210 kHz. Equation 38 is the
geometric mean of the modulator pole and the esr zero and Equation 39 is the mean of modulator pole and the
switching frequency. Equation 38 yields 85.3 kHz and Equation 39 gives 54.9 kHz. Use the lower value of
Equation 38 or Equation 39 as the approximate crossover frequency. For this example, fc is 56 kHz. Next, the
compensation components are calculated. A resistor in series with a capacitor is used to create a compensating
zero. A capacitor in parallel to these two components forms the compensating pole (if needed).
¦ p m od =
Iout m ax
2 p ´ Vout ´ Cout
(36)
1
2 p ´ Resr ´ Cout
(37)
vertical spacer
¦ z m od =
vertical spacer
¦C =
¦p mod ´ ¦ z mod
(38)
vertical spacer
¦C =
¦p mod ´
¦ sw
2
(39)
vertical spacer
The compensation design takes the following steps:
1. Set up the anticipated cross-over frequency. Use Equation 40 to calculate the compensation network’s
resistor value. In this example, the anticipated cross-over frequency (fc) is 56 kHz. The power stage gain
(gmps) is 18 A/V and the error amplifier gain (gmea) is 245 mA/V.
2p × ¦ c ´ Vo ´ Co
R3 =
Gm ´ Vref ´ VIgm
(40)
2. Place compensation zero at the pole formed by the load resistor and the output capacitor. The compensation
network’s capacitor can be calculated from Equation 41.
Ro ´ Co
C3 =
R3
(41)
3. An additional pole can be added to attenuate high frequency noise. In this application, it is not necessary to
add it.
From the procedures above, the compensation network includes a 7.68 kΩ resistor and a 3300 pF capacitor.
24
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APPLICATION CURVES
EFFICIENCY
vs
LOAD CURRENT
100
EFFICIENCY
vs
LOAD CURRENT
100
3.3 Vin,1.8 Vout
90
90
80
80
5 Vin, 1.8 Vout
70
Efficiency - %
Efficiency - %
70
60
50
40
5 Vin, 1.8 Vout
3.3 Vin,1.8 Vout
60
50
40
30
30
20
20
10
10
0
0
0.5
1
1.5
2
2.5
0
0.001
3
0.01
0.1
Output Current - A
1
10
Output Current - A
Figure 36.
Figure 37.
EFFICIENCY
vs
LOAD CURRENT
1 MHz, 3.3 VIN, TA = 25°C
EFFICIENCY
vs
LOAD CURRENT
1 MHz, 5 VIN, TA = 25°C
100
100
95
90
90
85
85
80
1.05 V
1.2 V
Efficience - %
Efficience - %
2.5 V
1.8 V
95
1.5 V
75
70
2.5 V
1.8 V
1.5 V
1.2 V
3.3 V
80
1.05V
75
70
65
65
60
60
55
55
50
50
0
0.5
1
1.5
2
IO - Output Current - A
2.5
3
0
0.5
Figure 38.
1
1.5
2
IO - Output Current - A
2.5
3
Figure 39.
TRANSIENT RESPONSE, 1.5 A STEP
POWER UP VOUT, VIN
Vin = 5 V / div
Vout = 100 mV / div (ac coupled)
Vout = 2 V / div
Iout = 1 A / div (0 A to 1.5 A load step)
EN = 2 V / div
PWRGD = 5 V / div
Time = 5 msec / div
Time = 200 usec / div
Figure 40.
Figure 41.
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POWER UP VOUT, EN
OUTPUT RIPPLE, 3 A
Vin = 5 V / div
Vout = 20 mV / div (ac coupled)
Vout = 2 V / div
PH = 2 V / div
EN = 2 V / div
PWRGD = 5 V / div
Time = 500 nsec / div
Time = 5 msec / div
Figure 42.
Figure 43.
CLOSED LOOP RESPONSE, VIN (5 V), 3 A
Gain - dB
Vin = 100 mV / div (ac coupled)
PH = 2 V / div
60
180
50
150
40
120
30
90
20
60
10
30
0
0
–10
–30
–20
–60
–30
–90
–40
–120
Gain
Phase
–50
–60
10
Time = 500 nsec / div
100
Figure 44.
1000
10k
Frequency - Hz
–180
1M
100k
REGULATION
vs
INPUT VOLTAGE
0.4
0.4
0.3
Output Voltage Deviation - %
0.3
Output Voltage Deviation - %
–150
Figure 45.
LOAD REGULATION
vs
LOAD CURRENT
0.2
Vin = 5 V
0.1
0
Vin = 3.3 V
-0.1
-0.2
Iout = 2 A
0.2
0.1
0
-0.1
-0.2
-0.3
-0.3
-0.4
-0.4
0
0.5
1
1.5
2
2.5
3
3
3.5
4
4.5
5
5.5
6
Input Voltage-V
Output Current - A
Figure 46.
26
Phase - Degrees
INPUT RIPPLE, 3 A
Figure 47.
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POWER DISSIPATION ESTIMATE
The following formulas show how to estimate the IC power dissipation under continuous conduction mode (CCM)
operation. The power dissipation of the IC (Ptot) includes conduction loss (Pcon), dead time loss (Pd), switching
loss (Psw), gate drive loss (Pgd) and supply current loss (Pq).
Pcon = Io2 × RDS_on_Temp
Pd = ƒsw × Io × 0.7 × 40 × 10–9
Psw = 1/2 × Vin × Io × ƒsw× 8 × 10–9
Pgd = 2 × Vin × ƒsw× 2 × 10–9
Pq = Vin × 360 × 10–6
Where:
IO is the output current (A).
RDS_on_Temp is the on-resistance of the high-side MOSFET with given temperature (Ω).
Vin is the input voltage (V).
ƒsw is the switching frequency (Hz).
So
Ptot = Pcon + Pd + Psw + Pgd + Pq
For given TA,
TJ = TA + Rth × Ptot
For given TJMAX = 150°C
TAmax = TJ max – Rth × Ptot
Where:
Ptot is the total device power dissipation (W).
TA is the ambient temperature (°C).
TJ is the junction temperature (°C).
Rth is the thermal resistance of the package (°C/W).
TJMAX is maximum junction temperature (°C).
TAMAX is maximum ambient temperature (°C).
There are additional power losses in the regulator circuit due to the inductor AC and DC losses and trace
resistance that impact the overall efficiency of the regulator.
LAYOUT
Layout is a critical portion of good power supply design. There are several signal paths that conduct fast
changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise
or degrade the power supplies performance. Care should be taken to minimize the loop area formed by the
bypass capacitor connections and the VIN pins. See Figure 48 for a PCB layout example. The GND pins and
AGND pin should be tied directly to the power pad under the IC. The power pad should be connected to any
internal PCB ground planes using multiple vias directly under the IC. Additional vias can be used to connect the
top side ground area to the internal planes near the input and output capacitors. For operation at full rated load,
the top side ground area along with any additional internal ground planes must provide adequate heat dissipating
area.
Locate the input bypass capacitor as close to the IC as possible. The PH pin should be routed to the output
inductor. Since the PH connection is the switching node, the output inductor should be located very close to the
PH pins, and the area of the PCB conductor minimized to prevent excessive capacitive coupling. The boot
capacitor must also be located close to the device. The sensitive analog ground connections for the feedback
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voltage divider, compensation components, slow start capacitor and frequency set resistor should be connected
to a separate analog ground trace as shown. The RT/CLK pin is particularly sensitive to noise so the RT resistor
should be located as close as possible to the IC and routed with minimal lengths of trace. The additional external
components can be placed approximately as shown. It may be possible to obtain acceptable performance with
alternate PCB layouts, however this layout has been shown to produce good results and is meant as a guideline.
VIA to
Ground
Plane
UVLO SET
RESISTORS
VIN
INPUT
BYPASS
CAPACITOR
BOOT
PWRGD
EN
VIN
VIN
BOOT
CAPACITOR
VIN
OUTPUT
INDUCTOR
PH
VIN
PH
EXPOSED
POWERPAD
AREA
GND
PH
GND
VOUT
OUTPUT
FILTER
CAPACITOR
PH
SLOW START
CAPACITOR
RT/CLK
COMP
VSENSE
AGND
SS
FEEDBACK
RESISTORS
ANALOG
GROUND
TRACE
FREQUENCY
SET
RESISTOR
TOPSIDE
GROUND
AREA
COMPENSATION
NETWORK
VIA to Ground Plane
Figure 48. PCB Layout Example
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS54319RTER
ACTIVE
WQFN
RTE
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 150
54319
TPS54319RTET
ACTIVE
WQFN
RTE
16
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 150
54319
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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