TPS54521RHLT

TPS54521 www.ti.com SLVS981C – JUNE 2010 – REVISED AUGUST 2013 4.5V to 17V Input, 5A Synchronous Step Down Converter Check for Samples: TPS54521 FEATURES 1 • • • • • • • • • 2 • • • Integrated 57mΩ / 50mΩ MOSFETs Split Power Rail: 1.6V to 17V on PVIN 200kHz to 900kHz Switching Frequency Synchronizes to External Clock 0.8V Voltage Reference Low 2uA Shutdown Quiescent Current Hiccup Overcurrent Protection Monotonic Start-Up into Prebiased Outputs –40°C to 125°C Operating Junction Temperature Range Pin-to-Pin Compatible with the TPS54620 Adjustable Slow Start/Power Sequencing Power Good Output for Undervoltage and Overvoltage Monitoring Adjustable Input Undervoltage Lockout Supported by SwitcherPro™ Software Tool • • APPLICATIONS • • • • Flat Panel Digital TVs Set Top Boxes, Personal Video Recorders Net Books High Density 3.3V/5V Power Distribution from 12 V Bus DESCRIPTION The TPS54521 is a full featured 17V, 5A synchronous step down converter which is optimized for small designs through high efficiency and integrated high-side and low-side MOSFETs. Further space savings are achieved through current mode control, which reduces component count, and by selecting a high switching frequency, reducing the inductor's footprint. The output voltage startup ramp is controlled by the SS/TR pin which allows operation as either a stand alone power supply or in tracking situations. Power sequencing is also possible by correctly configuring the enable and the open drain power good pins. Cycle by cycle current limiting on the high-side FET protects the device in overload situations and is enhanced by a low-side sourcing current limit which prevents current runaway. Hiccup protection will be triggered if the overcurrent condition has persisted for longer than the preset time. Thermal shutdown disables the part when die temperature exceeds thermal shutdown temperature. The TPS54521 is available in a 14 pin, 3.5mm x 3.5mm QFN, thermally enhanced package. WHITE SPACE SIMPLIFIED SCHEMATIC 100 Cin 95 Cboot 90 85 VOUT Lo EN PH PWRGD Co R1 Efficiency - % PVIN VIN TPS54521 BOOT VIN 80 VOUT = 1.8 V VOUT = 3.3 V 75 VOUT = 5 V 70 65 VSENSE SS/TR RT/CLK GND COMP Css Rrt C2 R3 Exposed Thermal PAD R2 60 VIN = 12 V, Fsw = 500 kHz 55 50 0 0.5 1 1.5 2 2.5 3 Load Current - A 3.5 4 4.5 5 C1 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SwitcherPro is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010–2013, Texas Instruments Incorporated TPS54521 SLVS981C – JUNE 2010 – REVISED AUGUST 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) (1) (2) TJ PACKAGE PART NUMBER (2) –40°C to 125°C 14 Pin QFN TPS54521RHL For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. The RHL package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS54521RHLR). See applications section of data sheet for layout information. ABSOLUTE MAXIMUM RATINGS (1) over operating temperature range (unless otherwise noted) Input Voltage VALUE UNIT VIN –0.3 to 20 V PVIN –0.3 to 20 V EN –0.3 to 6 V BOOT –0.3 to 28 V VSENSE –0.3 to 3 V COMP –0.3 to 3 V PWRGD –0.3 to 6 V SS/TR –0.3 to 3 V RT/CLK –0.3 to 6 V 0 to 8 V –1 to 20 V BOOT-PH Output Voltage PH PH 10ns Transient Vdiff(GND to exposed thermal pad) Source Current Sink Current –3 to 20 V –0.2 to 0.2 V ±100 μA PH Current Limit A PH Current Limit A PVIN Current Limit A RT/CLK COMP PWRGD Electrostatic Discharge (HBM) QSS 009-105 (JESD22-A114A) Electrostatic Discharge (CDM) QSS 009-147 (JESD22-C101B.01) ±200 μA –0.1 to 5 mA 2 kV 500 V Operating Junction Temperature –40 to 125 °C Storage Temperature –65 to 150 °C (1) 2 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links :TPS54521 TPS54521 www.ti.com SLVS981C – JUNE 2010 – REVISED AUGUST 2013 THERMAL INFORMATION TPS54521 THERMAL METRIC (1) (2) QFN UNITS 14 PINS θJA 47.2 (3) θJA Junction-to-ambient thermal resistance θJCtop Junction-to-case (top) thermal resistance 64.8 θJB Junction-to-board thermal resistance 14.4 ψJT Junction-to-top characterization parameter 0.5 ψJB Junction-to-board characterization parameter 14.7 θJCbot Junction-to-case (bottom) thermal resistance 3.2 (1) (2) (3) 32 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Power rating at a specific ambient temperature TA should be determined with a junction temperature of 125°C. This is the point where distortion starts to substantially increase. Thermal management of the PCB should strive to keep the junction temperature at or below 125°C for best performance and long-term reliability. See power dissipation estimate in application section of this data sheet for more information. Test board conditions: (a) 2.5 inches × 2.5 inches, 4 layers, thickness: 0.062 inch (b) 2 oz. copper traces located on the top of the PCB (c) 2 oz. copper ground planes on the 2 internal layers and bottom layer (d) 4 0.010 inch thermal vias located under the device package Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links :TPS54521 3 TPS54521 SLVS981C – JUNE 2010 – REVISED AUGUST 2013 www.ti.com ELECTRICAL CHARACTERISTICS TJ= –40°C to 125°C, VIN = 4.5V to 17V, PVIN = 1.6V to 17V (unless otherwise noted) DESCRIPTION CONDITIONS MIN TYP MAX UNIT SUPPLY VOLTAGE (VIN AND PVIN PINS) PVIN operating input voltage 1.6 17 V VIN operating input voltage 4.5 17 V 4.5 V VIN internal UVLO threshold VIN rising 4.0 VIN internal UVLO hysteresis 150 VIN shutdown supply Current EN = 0 V VIN operating – non switching supply current VSENSE = 810 mV mV 2 5 μA 600 800 μA 1.21 1.26 V ENABLE AND UVLO (EN PIN) Enable threshold Rising Enable threshold Falling Input current Hysteresis current 1.10 1.17 V EN = 1.1 V 1.15 μA EN = 1.3 V 3.4 μA VOLTAGE REFERENCE 0 A ≤ Iout ≤ 5 A Voltage reference 0.776 0.800 0.824 V MOSFET High-side switch resistance (1) BOOT-PH = 3 V 74 105 mΩ High-side switch resistance (1) BOOT-PH = 6 V 57 95 mΩ VIN = 12 V 50 82 mΩ Low-side Switch Resistance (1) ERROR AMPLIFIER Error amplifier Transconductance (gm) –2 μA < ICOMP < 2 μA, V(COMP) = 1 V Error amplifier dc gain VSENSE = 0.8 V Error amplifier source/sink V(COMP) = 1 V, 100 mV input overdrive 1000 Start switching threshold 1300 μMhos 3100 V/V ±110 μA 0.25 COMP to Iswitch gm V 12 A/V CURRENT LIMIT High-side switch current limit threshold 7 9 A Low-side switch sourcing current limit 6 8 A Low-side switch sinking current limit 1 Hiccup wait time before triggering hiccup Hiccup time before restart (1) 4 2.6 A 512 cycles 16384 cycles Measured at pins Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links :TPS54521 TPS54521 www.ti.com SLVS981C – JUNE 2010 – REVISED AUGUST 2013 ELECTRICAL CHARACTERISTICS (continued) TJ= –40°C to 125°C, VIN = 4.5V to 17V, PVIN = 1.6V to 17V (unless otherwise noted) DESCRIPTION CONDITIONS MIN TYP MAX UNIT 140 150 °C 5 °C THERMAL SHUTDOWN Thermal shutdown Thermal shutdown hysteresis TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN) Minimum switching frequency Rrt = 240 kΩ (1%) 160 200 240 kHz Switching frequency Rrt = 100 kΩ (1%) 400 480 560 kHz Maximum switching frequency Rrt = 53 kΩ (1%) 765 900 1035 kHz Minimum pulse width 20 RT/CLK high threshold RT/CLK low threshold RT/CLK falling edge to PH rising edge delay ns 2 V 0.8 Measure at 500 kHz with RT resistor in series V 62 Switching frequency range (RT mode set point and PLL mode) 200 ns 900 kHz 135 ns PH (PH PIN) Minimum on time Measured at 90% to 90% of PH, TA = 25°C, IPH = 2A Minimum off time BOOT-PH ≥ 3 V 97 0 ns BOOT (BOOT PIN) BOOT-PH UVLO 2.1 3 V SLOW START AND TRACKING (SS/TR PIN) SS charge current SS/TR to VSENSE matching μA 2.3 V(SS/TR) = 0.4 V 29 60 mV VSENSE falling (Fault) 91 % Vref VSENSE rising (Good) 94 % Vref VSENSE rising (Fault) 109 % Vref VSENSE falling (Good) 106 % Vref POWER GOOD (PWRGD PIN) VSENSE threshold Output high leakage VSENSE = Vref, V(PWRGD) = 5.5 V Output low I(PWRGD) = 2 mA Minimum VIN for valid output V(PWRGD) < 0.5V at 100 μA Minimum SS/TR voltage for PWRGD valid 30 100 nA 0.3 V 0.6 1 V 1.2 1.4 V Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links :TPS54521 5 TPS54521 SLVS981C – JUNE 2010 – REVISED AUGUST 2013 www.ti.com DEVICE INFORMATION PIN ASSIGNMENTS RT/CLK 1 PWRGD 14 GND 2 13 BOOT GND 3 PVIN 4 PVIN 5 12 PH Exposed Thermal Pad (15) VIN 6 11 PH 10 EN 9 SS/TR 7 VSENSE 8 COMP PIN FUNCTIONS PIN NAME DESCRIPTION No. RT/CLK 1 Automatically selects between RT mode and CLK mode. An external timing resistor adjusts the switching frequency of the device; In CLK mode, the device synchronizes to an external clock. GND 2, 3 Return for control circuitry and low-side power MOSFET. PVIN 4, 5 Power input. Supplies the power switches of the power converter. VIN 6 Supplies the control circuitry of the power converter. VSENSE 7 Inverting input of the gm error amplifier. COMP 8 Error amplifier output, and input to the output switch current comparator. Connect frequency compensation to this pin. SS/TR 9 Slow-start and tracking. An external capacitor connected to this pin sets the internal voltage reference rise time. The voltage on this pin overrides the internal reference. It can be used for tracking and sequencing. EN 10 Enable pin. Float to enable. Adjust the input undervoltage lockout with two resistors. PH 11, 12 The switch node. BOOT 13 A bootstrap cap is required between BOOT and PH. The voltage on this cap carries the gate drive voltage for the high-side MOSFET. PWRGD 14 Open drain Power Good fault pin. Asserts low due to thermal shutdown, under-voltage, over-voltage, EN shutdown, or during slow start. Exposed Thermal PAD 15 Thermal pad of the package and signal ground. It must be soldered down for proper operation. 6 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links :TPS54521 TPS54521 www.ti.com SLVS981C – JUNE 2010 – REVISED AUGUST 2013 FUNCTIONAL BLOCK DIAGRAM PWRGD VIN EN Shutdown Ip Ih Enable Comparator Thermal Shutdown PVIN PVIN UVLO Shutdown UV Shutdown Logic Logic Hiccup Shutdown Enable Threshold OV Boot Charge Current Sense Minimum Clamp Pulse Skip ERROR AMPLIFIER VSENSE BOOT Boot UVLO SS/TR Voltage Reference HS MOSFET Current Comparator Power Stage & Deadtime Control Logic PH PH Slope Compensation Hiccup Shutdown VIN Overload Recovery and Clamp Oscillator with PLL Regulator LS MOSFET Current Limit Current Sense GND GND COMP RT/CLK Exposed Thermal Pad Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links :TPS54521 7 TPS54521 SLVS981C – JUNE 2010 – REVISED AUGUST 2013 www.ti.com TYPICAL CHARACTERISTICS CHARACTERISTIC CURVES HIGH-SIDE Rdson vs TEMPERATURE LOW-SIDE Rdson vs TEMPERATURE 75 VIN = 12 V RDS(on) – On Resistance – mΩ RDS(on) – On Resistance – mΩ 80 70 60 50 40 –50 –25 0 25 50 75 100 VIN = 12 V 65 55 45 35 –50 125 –25 TJ – Junction Temperature – °C 0 Figure 1. VOLTAGE REFERENCE vs TEMPERATURE 75 100 125 OSCILLATOR FREQUENCY vs TEMPERATURE 500 FSW – Oscillator Frequency – kHz Vref – Voltage Reference – V 50 Figure 2. 0.805 0.803 0.801 0.799 0.797 0.795 –50 –25 0 25 50 75 100 RT = 100 kΩ 495 490 485 480 475 470 –50 125 –25 TJ – Junction Temperature – °C 0 25 50 75 100 125 TJ – Junction Temperature – °C Figure 3. Figure 4. SHUTDOWN QUIESCENT CURRENT vs INPUT VOLTAGE EN PIN HYSTERESIS CURRENT vs TEMPERATURE 80 En = 0 V Tj = 125°C Tj = 25°C Tj = - 40°C Ih – Hysterisis Current – µA Isd – Shutdown Quiescent Current – mA 25 TJ – Junction Temperature – °C 70 VIN = 12 V EN = 1.3 V 60 50 40 –50 –25 0 25 50 75 100 125 TJ – Junction Temperature – °C Figure 5. 8 Figure 6. Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links :TPS54521 TPS54521 www.ti.com SLVS981C – JUNE 2010 – REVISED AUGUST 2013 TYPICAL CHARACTERISTICS (continued) EN PIN PULL-UP CURRENT vs TEMPERATURE EN PIN UVLO THRESHOLD vs TEMPERATURE 1.20 1.24 VIN = 12 V EN – UVLO Threshold – V Ip – Pullup Current – µA VIN = 12 V EN = 1.1 V 1.15 1.10 1.05 1.00 –50 –25 0 25 50 75 100 1.23 1.22 1.21 1.20 –50 125 –25 TJ – Junction Temperature – °C 0 75 100 125 Figure 8. NON-SWITCHING OPERATING QUIESCENT CURRENT vs INPUT VOLTAGE SLOW START CHARGE CURRENT vs TEMPERATURE 2.50 800 Iss – SS Charge Current – µA Iq – Non-Switching Operating Quiescent Current – μA 50 TJ – Junction Temperature – °C Figure 7. TJ = –40°C TJ = 25°C 700 TJ = 125°C 600 500 3 6 9 15 12 2.40 2.30 2.20 2.10 –50 400 18 –25 0 Figure 9. 50 75 100 125 Figure 10. (SS/TR - VSENSE) OFFSET vs TEMPERATURE PWRGD THRESHOLD vs TEMPERATURE 120 PWRGD Threshold – % of Vref 80 70 60 50 40 –50 25 TJ – Junction Temperature – °C VI – Input Voltage – V Voff – SS/TR to Vsense Offset – V 25 –25 0 25 50 75 100 125 VSENSE Rising 110 VSENSE Falling 100 VSENSE Rising 90 VSENSE Falling 80 –50 TJ – Junction Temperature – °C –25 0 25 50 75 100 125 TJ – Junction Temperature – °C Figure 11. Figure 12. Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links :TPS54521 9 TPS54521 SLVS981C – JUNE 2010 – REVISED AUGUST 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) HIGH-SIDE CURRENT LIMIT THRESHOLD vs INPUT VOLTAGE MINIMUM CONTROLLABLE ON TIME vs TEMPERATURE Tonmin – Minimum Controllable On Time – ns Icl – Current Limit Threshold – A 11 TJ = –40°C 10 TJ = 25°C 9 8 TJ = 125°C 13 8 VIN = 12 V IOUT = 2 A 110 100 90 80 70 –50 7 3 120 18 –25 0 Figure 13. 75 100 125 BOOT-PH UVLO THRESHOLD vs TEMPERATURE 6 2.2 5 4 RT = 100 KΩ VIN = 12 V IOUT = 2 A –25 0 25 50 75 100 125 150 Vboot – BOOT-PH UVLO THRESHOLD – V Dmin – Minimum Controllable Duty Ratio – % 50 Figure 14. MINIMUM CONTROLLABLE DUTY RATIO vs JUNCTION TEMPERATURE 3 –50 25 TJ – Junction Temperature – °C VI – Input Voltage – V 2.1 2.0 –50 TJ – Junction Temperature – °C –25 0 25 50 75 100 125 TJ – Junction Temperature – °C Figure 15. Figure 16. OVERVIEW The device is a 17-V, 5-A, synchronous step-down (buck) converter with two integrated n-channel MOSFETs. To improve performance during line and load transients the device implements a constant frequency, peak current mode control which also simplifies external frequency compensation. The wide switching frequency of 200 kHz to 900 kHz allows for efficiency and size optimization when selecting the output filter components. The switching frequency is adjusted using a resistor to ground on the RT/CLK pin. The device also has an internal phase lock loop (PLL) controlled by the RT/CLK pin that can be used to synchronize the switching cycle to the falling edge of an external system clock. The device has been designed for safe monotonic startup into pre-biased loads. The default start up is when VIN is typically 4.0V. The EN pin has an internal pull-up current source that can be used to adjust the input voltage under voltage lockout (UVLO) with two external resistors. In addition, the EN pin can be left floating for the device to automatically start with the internal pull-up current. The total operating current for the device is approximately 600μA when not switching and under no load. When the device is disabled, the supply current is typically less than 2μA. The integrated MOSFETs allow for high efficiency power supply designs with continuous output currents up to 5 amperes. The MOSFETs have been sized to optimize efficiency for lower duty cycle applications. 10 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links :TPS54521 TPS54521 www.ti.com SLVS981C – JUNE 2010 – REVISED AUGUST 2013 TYPICAL CHARACTERISTICS (continued) The device reduces the external component count by integrating the boot recharge circuit. The bias voltage for the integrated high-side MOSFET is supplied by a capacitor between the BOOT and PH pins. The boot capacitor voltage is monitored by a BOOT to PH UVLO (BOOT-PH UVLO) circuit allowing PH pin to be pulled low to recharge the boot capacitor. The device can operate at 100% duty cycle, as long as the boot capacitor voltage is higher than the preset BOOT-PH UVLO threshold, which is typically 2.1V. The output voltage can be stepped down to as low as the 0.8V voltage reference (Vref). The device has a power good comparator (PWRGD) with hysteresis which monitors the output voltage through the VSENSE pin. The PWRGD pin is an open drain MOSFET which is pulled low when the VSENSE pin voltage is less than 91% or greater than 109% of the reference voltage Vref and floats high when the VSENSE pin voltage is 94% to 106% of the Vref. The SS/TR (slow start/tracking) pin is used to minimize inrush currents or provide power supply sequencing during power up. A small value capacitor or resistor divider should be attached to the pin for slow start or critical power supply sequencing requirements. The device is protected from output overvoltage, overload and thermal fault conditions. The device minimizes excessive output overvoltage transients by taking advantage of the overvoltage circuit power good comparator. When the overvoltage comparator is activated, the high-side MOSFET is turned off and prevented from turning on until the VSENSE pin voltage is lower than 106% of the Vref. The device implements both high-side MOSFET overload protection and bidirectional low-side MOSFET overload protections which help control the inductor current and avoid current runaway. If the overcurrent condition has lasted for more than the hiccup wait time, the device will shut down and restart after the hiccup time. The device also shuts down if the junction temperature is higher than thermal shutdown trip point. The device is restarted under control of the slow start circuit automatically when the junction temperature drops 5°C typically below the thermal shutdown trip point. DETAILED DESCRIPTION Fixed Frequency PWM Control The device uses adjustable, fixed frequency, peak current mode control. The output voltage is compared through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives the COMP pin. An internal oscillator initiates the turn on of the high-side power switch. The error amplifier output is converted into a current reference which is compared to the high-side power switch current. When the power switch current reaches the current reference generated by the COMP voltage level, the high-side power switch is turned off and the low-side power switch is turned on. Continuous Current Mode Operation (CCM) As a synchronous buck converter, the device normally works in CCM (Continuous Conduction Mode) under all load conditions. VIN and Power VIN Pins (VIN and PVIN) The device allows for a variety of applications by using the VIN and PVIN pins together or separately. The VIN pin voltage supplies the internal control circuits of the device. The PVIN pin voltage provides the input voltage to the power converter system. If tied together, the input voltage for VIN and PVIN can range from 4.5V to 17V. If using the VIN separately from PVIN, the VIN pin must be between 4.5V and 17V, and the PVIN pin can range from as low as 1.6V to 17V. A voltage divider connected to the EN pin can adjust either input voltage UVLO appropriately. Adjusting the input voltage UVLO on the PVIN pin helps to provide consistent power up behavior. Voltage Reference The voltage reference system produces a precise voltage reference by scaling the output of a temperature stable bandgap circuit. Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links :TPS54521 11 TPS54521 SLVS981C – JUNE 2010 – REVISED AUGUST 2013 www.ti.com Adjusting the Output Voltage The output voltage is set with a resistor divider from the output (VOUT) to the VSENSE pin. It is recommended to use 1% tolerance or better divider resistors. Referring to the application schematic of Figure 34, start with a 10 kΩ resistor for R9 and use Equation 1 to calculate R8. To improve efficiency at light loads, consider using larger value resistors. If the values are too high, the regulator is more susceptible to noise and voltage errors from the VSENSE input current are noticeable. Vout - Vref R8 = R9 Vref (1) Where Vref = 0.8V The minimum output voltage and maximum output voltage can be limited by the minimum on time of the highside MOSFET and bootstrap voltage (BOOT-PH voltage) respectively. More discussions are located in Minimum Output Voltage and Bootstrap Voltage (BOOT) and Low Dropout Operation. Safe Start-up into Pre-Biased Outputs The device has been designed to prevent the low-side MOSFET from discharging a prebiased output. During monotonic pre-biased startup, the low-side MOSFET is not allowed to turn on until the SS/TR pin voltage is higher than the VSENSE pin voltage. Error Amplifier The device uses a transconductance error amplifier. The error amplifier compares the VSENSE pin voltage to the lower of the SS/TR pin voltage or the internal 0.8V voltage reference. The transconductance of the error amplifier is 1300 μA/V during normal operation. The frequency compensation network is connected between the COMP pin and ground. Slope Compensation The device adds a compensating ramp to the switch current signal. This slope compensation prevents subharmonic oscillations. The available peak inductor current remains constant over the full duty cycle range. Enable and Adjusting Under-Voltage Lockout The EN pin provides an electrical on/off control of the device. Once the EN pin voltage exceeds the threshold voltage, the device starts operation. If the EN pin voltage is pulled below the threshold voltage, the regulator stops switching and enters a low Iq state. The EN pin has an internal pull-up current source, allowing the user to float the EN pin for enabling the device. If an application requires controlling the EN pin, use an open drain or open collector output logic to interface with the pin. The device implements internal UVLO circuitry on the VIN pin. The device is disabled when the VIN pin voltage falls below the internal VIN UVLO threshold. The internal VIN UVLO threshold has a hysteresis of 150mV. If an application requires either a higher UVLO threshold on the VIN pin or a secondary UVLO on the PVIN pin, in split rail applications, then the EN pin can be configured as shown in Figure 17, Figure 18 or Figure 19. When using the external UVLO function, it is recommended to set the hysteresis to be greater than 500mV. The EN pin has a small pull-up current Ip which sets the default state of the pin to enable when no external components are connected. The pull-up current is also used to control the voltage hysteresis for the UVLO function since it increases by Ih once the EN pin crosses the enable threshold. The UVLO thresholds can be calculated using Equation 2 and Equation 3. 12 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links :TPS54521 TPS54521 www.ti.com SLVS981C – JUNE 2010 – REVISED AUGUST 2013 TPS54521 VIN ip ih R1 R2 EN Figure 17. Adjustable VIN Under Voltage Lock Out TPS54521 PVIN ip ih R1 R2 EN Figure 18. Adjustable PVIN Under Voltage Lock Out, VIN ≥ 4.5V TPS54521 PVIN VIN ip ih R1 R2 EN Figure 19. Adjustable VIN and PVIN Under Voltage Lock Out æV ö VSTART ç ENFALLING ÷ - VSTOP è VENRISING ø R1 = æ V ö Ip ç1 - ENFALLING ÷ + Ih VENRISING ø è R2 = VSTOP (2) R1´ VENFALLING - VENFALLING + R1(Ip + Ih ) (3) Where Ih = 3.4 μA, Ip = 1.15 μA, VENRISING = 1.21 V, VENFALLING = 1.17 V Adjustable Switching Frequency and Synchronization (RT/CLK) The RT/CLK pin can be used to set the switching frequency of the device in two modes. Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links :TPS54521 13 TPS54521 SLVS981C – JUNE 2010 – REVISED AUGUST 2013 www.ti.com In RT mode, a resistor (RT resistor) is connected between the RT/CLK pin and GND. The switching frequency of the device is adjustable from 200 kHz to 900 kHz by using a maximum of 240 kΩ and minimum of 53 kΩ respectively. In CLK mode, an external clock is connected directly to the RT/CLK pin. The device is synchronized to the external clock frequency with a PLL. The CLK mode overrides the RT mode. The device is able to detect the proper mode automatically and switch from the RT mode to CLK mode. Adjustable Switching Frequency (RT Mode) To determine the RT resistance for a given switching frequency, use Equation 4 or the curve in Figure 20. To reduce the solution size, one would set the switching frequency as high as possible, but tradeoffs of the supply efficiency and minimum controllable on time should be considered. -1.033 Rrt(kW) = 60728 × Fsw (kHz ) (4) 250 RT - Resistance - kΩ 200 150 100 50 0 200 300 400 500 600 700 800 900 Fsw - Oscillator Frequency - kHz Figure 20. RT Set Resistor vs Switching Frequency Synchronization (CLK mode) An internal Phase Locked Loop (PLL) has been implemented to allow synchronization between 200kHz and 900kHz, and to easily switch from RT mode to CLK mode. To implement the synchronization feature, connect a square wave clock signal to the RT/CLK pin with a duty cycle between 20% to 80%. The clock signal amplitude must transition lower than 0.8V and higher than 2.0V. The start of the switching cycle is synchronized to the falling edge of RT/CLK pin. In applications where both RT mode and CLK mode are needed, the device can be configured as shown in Figure 21. Before the external clock is present, the device works in RT mode and the switching frequency is set by RT resistor. When the external clock is present, the CLK mode overrides the RT mode. The first time the SYNC pin is pulled above the RT/CLK high threshold (2.0V), the device switches from the RT mode to the CLK mode and the RT/CLK pin becomes high impedance as the PLL starts to lock onto the frequency of the external clock. It is not recommended to switch from the CLK mode back to the RT mode, because the internal switching frequency drops to 100kHz first before returning to the switching frequency set by RT resistor. 14 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links :TPS54521 TPS54521 www.ti.com SLVS981C – JUNE 2010 – REVISED AUGUST 2013 RT/CLK mode select TPS54521 RT/CLK Rrt Figure 21. Works with Both RT mode and CLK mode Slow Start (SS/TR) The device uses the lower voltage of the internal voltage reference or the SS/TR pin voltage as the reference voltage and regulates the output accordingly. A capacitor on the SS/TR pin to ground implements a slow start time. The device has an internal pull-up current source of 2.3μA that charges the external slow start capacitor. The calculations for the slow start time (Tss, 10% to 90%) and slow start capacitor (Css) are shown in Equation 5. The voltage reference (Vref) is 0.8 V and the slow start charge current (Iss) is 2.3μA. Tss(ms) = Css(nF) ´ Vref(V) Iss(m A) (5) When the input UVLO is triggered, the EN pin is pulled below 1.21V, or a thermal shutdown event occurs the device stops switching and enters low current operation. At the subsequent power up, when the shutdown condition is removed, the device does not start switching until it has discharged its SS/TR pin to ground ensuring proper soft start behavior. Power Good (PWRGD) The PWRGD pin is an open drain output. Once the VSENSE pin is between 94% and 106% of the internal voltage reference the PWRGD pin pull-down is de-asserted and the pin floats. It is recommended to use a pullup resistor between the values of 10kΩ and 100kΩ to a voltage source that is 5.5V or less. The PWRGD is in a defined state once the VIN input voltage is greater than 1V but with reduced current sinking capability. The PWRGD achieves full current sinking capability once the VIN input voltage is above 4.5V. The PWRGD pin is pulled low when VSENSE is lower than 91% or greater than 109% of the nominal internal reference voltage. Also, the PWRGD is pulled low, if the input UVLO or thermal shutdown are asserted, the EN pin is pulled low, or the SS/TR pin is below 1.2V typically. Bootstrap Voltage (BOOT) and Low Dropout Operation The device has an integrated boot regulator, and requires a small ceramic capacitor between the BOOT and PH pins to provide the gate drive voltage for the high-side MOSFET. The boot capacitor is charged when the BOOT pin voltage is less than VIN and BOOT-PH voltage is below regulation. The value of this ceramic capacitor should be 0.1μF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10V or higher is recommended because of the stable characteristics over temperature and voltage. To improve dropout, the device is designed to operate at 100% duty cycle as long as the BOOT to PH pin voltage is greater than the BOOT-PH UVLO threshold which is typically 2.1V. When the voltage between BOOT and PH drops below the BOOT-PH UVLO threshold the high-side MOSFET is turned off and the low-side MOSFET is turned on allowing the boot capacitor to be recharged. In applications with split input voltage rails 100% duty cycle operation can be achieved as long as (VIN – PVIN) > 4V. A boot resistor in series with the boot capacitor should never be used on the TPS54521. Sequencing (SS/TR) Many of the common power supply sequencing methods can be implemented using the SS/TR, EN, and PWRGD pins. Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links :TPS54521 15 TPS54521 SLVS981C – JUNE 2010 – REVISED AUGUST 2013 www.ti.com The sequential method is illustrated in Figure 22 using two TPS54521 devices. The power good of the first device is coupled to the EN pin of the second device which enables the second power supply once the primary supply reaches regulation. Figure 23 shows the results of Figure 22. TPS54521 TPS54521 PWRGD = 2 V / div PWRGD EN EN SS/TR SS/TR EN = 2 V / div Vout1 = 1 V / div PWRGD Vout2 = 1 v / div Time = 2 msec / div Figure 22. Sequential Start Up Sequence Figure 23. Sequential Start Up using EN and PWRGD Figure 24 shows the method implementing ratio-metric sequencing by connecting the SS/TR pins of two devices together. The regulator outputs ramp up and reach regulation at the same time. When calculating the slow start time the pull-up current source must be doubled in Equation 5. Figure 25 shows the results of Figure 24. TPS54521 EN EN = 2 V / div SS/TR PWRGD Vout1 = 1 V / div TPS54521 Vout2 = 1 V / div EN Time = 2 msec / div SS/TR Figure 25. Ratio-metric Startup using Coupled SS/TR Pins PWRGD Figure 24. Ratiometric Start Up Sequence Ratio-metric and simultaneous power supply sequencing can be implemented by connecting the resistor network of R1 and R2 shown in Figure 26 to the output of the power supply that needs to be tracked or another voltage reference source. Using Equation 6 and Equation 7, the tracking resistors can be calculated to initiate the Vout2 slightly before, after or at the same time as Vout1. Equation 8 is the voltage difference between Vout1 and Vout2. To design a ratio-metric start up in which the Vout2 voltage is slightly greater than the Vout1 voltage when Vout2 reaches regulation, use a negative number in Equation 6 and Equation 7 for deltaV. Equation 8 results in a positive number for applications where the Vout2 is slightly lower than Vout1 when Vout2 regulation is achieved. Figure 27 and Figure 28 show the results for positive deltaV and negative deltaV respectively. 16 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links :TPS54521 TPS54521 www.ti.com SLVS981C – JUNE 2010 – REVISED AUGUST 2013 The deltaV variable is zero volts for simultaneous sequencing. To minimize the effect of the inherent SS/TR to VSENSE offset (Vssoffset, 29mV) in the slow start circuit and the offset created by the pull-up current source (Iss, 2.3μA) and tracking resistors, the Vssoffset and Iss are included as variables in the equations. Figure 29 shows the result when deltaV = 0V. To ensure proper operation of the device, the calculated R1 value from Equation 6 must be greater than the value calculated in Equation 9. R1 = Vout2 + D V Vssoffset ´ Vref Iss (6) Vref ´ R1 Vout2 + DV - Vref DV = Vout1 - Vout2 R1 > 2800 ´ Vout1- 180 ´ DV R2 = (7) (8) (9) TPS54521 EN VOUT1 SS/TR PWRGD TPS54521 EN VOUT 2 R1 SS/TR R2 PWRGD R4 R3 Figure 26. Ratiometric and Simultaneous Startup Sequence EN = 2 V / div Vout1 = 1 V / div Vout2 = 1 V / div Time = 2 msec / div Figure 27. Ratio-metric Startup with Vout1 Leading Vout2 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links :TPS54521 17 TPS54521 SLVS981C – JUNE 2010 – REVISED AUGUST 2013 www.ti.com EN = 2 V / div Vout1 = 1 V / div Vout2 = 1 V / div Time = 2 msec / div Figure 28. Ratio-metric Startup with Vout2 Leading Vout1 EN = 2 V / div Vout1 = 1 V / div Vout2 = 1 V / div Time = 2 msec / div Figure 29. Simultaneous Startup Output Overvoltage Protection (OVP) The device incorporates an output overvoltage protection (OVP) circuit to minimize output voltage overshoot. For example, when the power supply output is overloaded, the error amplifier compares the actual output voltage to the internal reference voltage. If the VSENSE pin voltage is lower than the internal reference voltage for a considerable time, the output of the error amplifier demands maximum output current. Once the condition is removed, the regulator output rises and the error amplifier output transitions to the steady state voltage. In some applications with small output capacitance, the power supply output voltage can respond faster than the error amplifier. This leads to the possibility of an output overshoot. The OVP feature minimizes the overshoot by comparing the VSENSE pin voltage to the OVP threshold. If the VSENSE pin voltage is greater than the OVP threshold the high-side MOSFET is turned off preventing current from flowing to the output and minimizing output overshoot. When the VSENSE voltage drops lower than the OVP threshold, the high-side MOSFET is allowed to turn on at the next clock cycle. Overcurrent Protection The device is protected from overcurrent conditions by cycle-by-cycle current limiting on both the high-side MOSFET and the low-side MOSFET. High-side MOSFET overcurrent protection High-side MOSFET overcurrent protection is achieved by an internal current comparator that monitors the current in the high-side MOSFET on a cycle-by-cycle basis. If this current exceeds the current limit threshold, the highside MOSFET is turned off for the remainder of that switching cycle. 18 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links :TPS54521 TPS54521 www.ti.com SLVS981C – JUNE 2010 – REVISED AUGUST 2013 During normal operation, the device implements current mode control which uses the COMP pin voltage to control the turn off of the high-side MOSFET and the turn on of the low-side MOSFET, on a cycle by cycle basis. Each cycle, the switch current and the current reference generated by the COMP pin voltage are compared. When the peak switch current intersects the current reference, the high-side switch is turned off. Low-side MOSFET overcurrent protection While the low-side MOSFET is turned on, its conduction current is monitored by the internal circuitry. During normal operation, the low-side MOSFET sources current to the load. At the end of every clock cycle, the low-side MOSFET sourcing current is compared to the internally set low-side sourcing current limit. If the low-side sourcing current is exceeded, the high-side MOSFET is not turned on and the low-side MOSFET stays on for the next cycle. The high-side MOSFET is turned on again when the low-side current is below the low-side sourcing current limit at the start of a cycle. The low-side MOSFET may also sink current from the load. If the low-side sinking current limit is exceeded, the low-side MOSFET is turned off immediately for the rest of that clock cycle. In this scenario both MOSFETs are off until the start of the next cycle. Furthermore, if an output overload condition (as measured by the COMP pin voltage) has lasted for more than the hiccup wait time which is programmed for 512 switching cycles, the device will shut down itself and restart after the hiccup time which is set for 16384 cycles. The hiccup mode helps to reduce the device power dissipation under severe overcurrent conditions. Thermal Shutdown The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds 150°C typically. The device reinitiates the power up sequence when the junction temperature drops below 145°C typically. Small Signal Model for Loop Response Figure 30 shows an equivalent model for the device's control loop which can be modeled in a circuit simulation program to check frequency response and transient responses. The error amplifier is a transconductance amplifier with a gm of 1300μA/V. The error amplifier can be modeled using an ideal voltage controlled current source. The resistor Roea (2.38 MΩ) and capacitor Coea (20.7 pF) model the open loop gain and frequency response of the error amplifier. The 1-mV ac voltage source between the nodes a and b effectively breaks the control loop for the frequency response measurements. Plotting a/c and c/b show the small signal responses of the power stage and frequency compensation respectively. Plotting a/b shows the small signal response of the overall loop. The dynamic loop response can be checked by replacing the RL with a current source with the appropriate load step amplitude and step rate in a time domain analysis. PH VOUT Power Stage 12 A/V a b c 0.8 V R4 Coea C6 R8 RESR VSENSE CO COMP C4 Roea gm 1300 mA/V RL R9 Figure 30. Small Signal Model for Loop Response Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links :TPS54521 19 TPS54521 SLVS981C – JUNE 2010 – REVISED AUGUST 2013 www.ti.com Simple Small Signal Model for Peak Current Mode Control Figure 31 is a simple small signal model that can be used to understand how to design the frequency compensation. The device's power stage can be approximated to a voltage controlled current source (duty cycle modulator) supplying current to the output capacitor and load resistor. The control to output transfer function is shown in Equation 10 and consists of a dc gain, one dominant pole and one ESR zero. The quotient of the change in switch current and the change in COMP pin voltage (node c in Figure 30) is the power stage transconductance (gmps) which is 12 A/V for the device. The DC gain of the power stage is the product of gmps and the load resistance (RL), as shown in Equation 11 with resistive loads. As the load current increases, the DC gain decreases. This variation with load may seem problematic at first glance, but fortunately the dominant pole moves with load current (see Equation 12). The combined effect is highlighted by the dashed line in Figure 32. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover frequency the same for the varying load conditions which makes it easier to design the frequency compensation. VOUT VC RESR RL gm ps CO Figure 31. Simplified Small Signal Model for Peak Current Mode Control VOUT Adc VC RESR fp RL gm ps CO fz Figure 32. Simplified Frequency Response for Peak Current Mode Control æ ç1+ 2p VOUT = Adc ´ è VC æ ç1+ è 2p ö s ÷ ´ ¦z ø ö s ÷ ´ ¦p ø (10) Adc = gmps ´ RL ¦p = 20 (11) 1 C O ´ R L ´ 2p (12) Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links :TPS54521 TPS54521 www.ti.com ¦z = SLVS981C – JUNE 2010 – REVISED AUGUST 2013 1 CO ´ RESR ´ 2p (13) Where gmea is the GM amplifier gain (1300μA/V) gmps is the power stage gain (12A/V). RL is the load resistance CO is the output capacitance. RESR is the equivalent series resistance of the output capacitor. Small Signal Model for Frequency Compensation The device uses a transconductance amplifier for the error amplifier and readily supports two of the commonly used Type II compensation circuits and a Type III frequency compensation circuit, as shown in Figure 33. In Type 2A, one additional high frequency pole, C6, is added to attenuate high frequency noise. In Type III, one additional capacitor, C11, is added to provide a phase boost at the crossover frequency. See Designing Type III Compensation for Current Mode Step-Down Converters (SLVA352) for a complete explanation of Type III compensation. The design guidelines below are provided for advanced users who prefer to compensate using the general method. The below equations only apply to designs whose ESR zero is above the bandwidth of the control loop. This is usually true with ceramic output capacitors. See the Application Information section for a step-by-step design procedure using higher ESR output capacitors with lower ESR zero frequencies. VOUT C11 R8 Type 3 VSENSE COMP Type 2A Vref R9 gm ea Roea R4 Coea C6 Type 2B R4 C4 C4 Figure 33. Types of Frequency Compensation The general design guidelines for device loop compensation are as follows: 1. Determine the crossover frequency, fc. A good starting point is 1/10th of the switching frequency, fsw. 2. R4 can be determined by: 2p ´ ¦ c ´ VOUT ´ Co R4 = gmea ´ Vref ´ gmps (14) Where: gmea is the GM amplifier gain (1300μA/V) gmps is the power stage gain (12A/V) Vref is the reference voltage (0.8V) æ ö 1 ç ¦p = ÷ ´ ´ p C R 2 ø O L 3. Place a compensation zero at the dominant pole: è C4 can be determined by: R ´ Co C4 = L R4 (15) 4. C6 is optional. It can be used to cancel the zero from the ESR (Equivalent Series Resistance) of the output capacitor Co. Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links :TPS54521 21 TPS54521 SLVS981C – JUNE 2010 – REVISED AUGUST 2013 www.ti.com RESR ´ Co R4 (16) 5. Type III compensation can be implemented with the addition of one capacitor, C11. This allows for slightly higher loop bandwidths and higher phase margins. If used, C11 is calculated from Equation 17. 1 C11 = (2 × p × R8 × fc ) (17) C6 = APPLICATION INFORMATION Design Guide – Step-By-Step Design Procedure This example details the design of a high frequency switching regulator using a Poscap output capacitor and Type III frequency compensation. A few parameters must be known in order to start the design process. These parameters are typically determined at the system level. For this example, we start with the following known parameters: Table 1. Parameter Value Output Voltage 5V Output Current 5A Transient Response to a 3A load step ΔVout = 1 % (50 mV) Input Voltage 12 V nominal, 8 V to 17 V Output Voltage Ripple 1.5% (75 mV p-p) Start Input Voltage (Rising Vin) 6.806 V Stop Input Voltage (Falling Vin) 4.824 V Switching Frequency 700 kHz Typical Application Schematic The application schematic of Figure 34 was developed to meet the requirements above. The design procedure is given in this section. For more information about Type II and Type III frequency compensation circuits, see Designing Type III Compensation for Current Mode Step-Down Converters (SLVA352) and Design Calculator (SLVC219). + Figure 34. Typical Application Circuit 22 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links :TPS54521 TPS54521 www.ti.com SLVS981C – JUNE 2010 – REVISED AUGUST 2013 Operating Frequency The first step is to decide on a switching frequency for the regulator. There is a trade off between higher and lower switching frequencies. Higher switching frequencies may produce a smaller solution size using lower valued inductors and smaller output capacitors compared to a power supply that switches at a lower frequency. However, the higher switching frequency causes additional switching losses, which hurt the converter’s efficiency and thermal performance. In this design, a moderate switching frequency of 700 kHz is selected to achieve both a small solution size and a high efficiency operation. This frequency is set using the resistor at the RT/CLK pin (R3). Using Equation 4, the resistance required for a switching frequency of 700 kHz is 69.9 kΩ. A 69.8 kΩ resistor is used for this design. Output Inductor Selection To calculate the value of the output inductor Equation 18 is used. Kind is a coefficient that represents the amount of inductor ripple current relative to the maximum output current. The inductor ripple current is filtered by the output capacitor. Therefore, choosing high inductor ripple currents impacts the selection of the output capacitor, since the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. In general, the inductor ripple value is at the discretion of the designer; however, Kind is normally from 0.3 to 0.4 for the majority of low cost applications. Vinmax - Vout Vout L1 = × Iout × Kind Vinmax × f sw (18) For this design example, using Kind = 0.35, the inductor value is calculated to be 2.9 µH. A 3.3 µH inductor from Coilcraft’s MSS1260 series was chosen. For the output filter inductor, it is important that the RMS current and saturation current ratings not be exceeded. The inductor ripple current, RMS current, and peak inductor current can be found from Equation 19, Equation 20, and Equation 21. Vinmax - Vout Vout × Iripple = L1 Vinmax × f sw (19) 1 æ Vout × (Vinmax - Vout ) ö ILrms = Iout + × ç ÷÷ 12 çè Vinmax × L1× f sw ø 2 2 ILpeak = Iout + (20) Iripple 2 (21) For this design, the inductor ripple current is 1.53 A, the RMS inductor current is 5.02 A, and the peak inductor current is 5.76 A. The chosen inductor has a RMS current rating of 7 A and a saturation current rating of 10.4 A. The current flowing through the inductor is the inductor ripple current plus the output current. During power up, faults, or transient load conditions, the inductor current can increase above the calculated peak inductor current level calculated above. In transient conditions, the inductor current can increase up to the switch current limit of the device. For this reason, the most conservative approach is to specify an inductor with a saturation current rating equal to or greater than the switch current limit rather than the peak inductor current. Output Capacitor Selection There are two primary considerations for selecting the output capacitor: the minimum capacitance required to meet the transient response specification and the maximum impedance at the switching frequency to meet the output voltage ripple requirement. Any output capacitor type (ceramic, tantalum, polymer, electrolytic, etc.) can be used with the TPS54521 to meet the design specifications. The desired response to a large change in the load current is the first criterion. The output capacitor needs to supply the load with current when the regulator cannot. This situation would occur if there are desired hold-up times for the regulator where the output capacitor must hold the output voltage above a certain level for a specified amount of time after the input power is removed. The regulator is also temporarily not able to supply sufficient output current if there is a large, fast increase in the current needs of the load, such as transitioning from no load to full load. The regulator usually needs two or more clock cycles for the control loop to see the Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links :TPS54521 23 TPS54521 SLVS981C – JUNE 2010 – REVISED AUGUST 2013 www.ti.com change in load current and output voltage and adjust the duty cycle to react to the change. The output capacitor must be sized to supply the extra current to the load until the control loop responds to the load change. The output capacitance must be large enough to supply the difference in current for 2 clock cycles while only allowing a tolerable amount of droop in the output voltage. Equation 22 shows the minimum output capacitance necessary to accomplish this. 2 × DIout Co > f sw × DVout (22) Where ΔIout is the change in output current, fsw is the regulator's switching frequency and ΔVout is the allowable change in the output voltage. For this example, the transient load response is specified as a 1% change in Vout for a load step of 3A. Using these numbers (ΔIout = 3.0 A and ΔVout= 0.01 x 5 = 0.05 V) gives a minimum capacitance of 171 μF. The next consideration is the maximum impedance at the switching frequency required to meet the output voltage ripple specification. The ripple current in the inductor is absorbed by the output capacitor and creates a ripple voltage across the capacitor's ESR and reactive impedance. Equation 23 calculates the maximum impedance to meet the ripple voltage specification of 75 mV. Equation 23 yields 49 mΩ for this design. V ripple Zeq = Iripple (23) This impedance at the switching frequency is the sum of its ESR and the absolute value of its reactive impedance. Equation 24 calculates the impedance at the switching frequency for any capacitor and must yield a resultant Zcap less than the Zeq found in Equation 23 to meet the output voltage ripple specification. The 6TPB220M (220 µF, 40 mΩ ESR) Poscap from Sanyo meets the impedance requirements of Equation 23 and the capacitance requirements of Equation 22. 1 Zcap = ESR + 2p × f sw × Ceff (24) Ceff in Equation 24 is the effective capacitance of the output capacitor. This capacitance is equal to the rated capacitance for most capacitor types, except for ceramics. The capacitance of ceramic capacitors is highly dependent on the DC output voltage due to the DC bias effect, which reduces the effective capacitance as the DC voltage on the capacitor is increased. Equation 25 is used to estimate the effective capacitance of a ceramic capacitor, based on its voltage rating, the output voltage, and its nominal capacitance. (( Vrated - Vout ) × Crated ) Ceff = Vrated (25) Capacitors generally have limits to the amount of ripple current they can handle without failing or producing excessive heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor data sheets specify the RMS (Root Mean Square) value of the maximum ripple current. Equation 26 can be used to calculate the RMS ripple current the output capacitor needs to support. For this application, Equation 26 yields 441 mA, which is less than the output capacitor's rating of 2 A. Vout × (Vinmax - Vout ) Icorms = 12 × Vinmax × L1× f sw (26) Input Capacitor Selection The TPS54521 requires a high quality ceramic, type X5R or X7R, input decoupling capacitor of roughly 4.7 µF on each input voltage rail (VIN and PVIN). In some applications, additional bulk capacitance may also be required for the PVIN input. The voltage rating of the input capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple current rating greater than the maximum input current ripple of the TPS54521. The input ripple current for this design, using Equation 27, is 2.42 A. Icirms = Iout × 24 Vout (Vinmin - Vout ) × Vinmin Vinmin Submit Documentation Feedback (27) Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links :TPS54521 TPS54521 www.ti.com SLVS981C – JUNE 2010 – REVISED AUGUST 2013 The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors because they have a high capacitance to volume ratio and are fairly stable over temperature. The capacitance value of a ceramic capacitor decreases as the DC bias across a capacitor increases. For this example design, a ceramic capacitor with at least a 25 V voltage rating is required to support the maximum input voltage. For this example, one 10 μF and one 4.7 µF 25 V capacitors in parallel have been selected, as the VIN and PVIN inputs are tied together so the TPS54521 may operate from a single supply. The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be calculated using Equation 28. Using the design example values, Ioutmax=5 A, Cin=14.7 μF, Fsw=700 kHz, Equation 28 yields an input voltage ripple of 121 mV. Ioutmax × 0.25 DVin = Cin × f sw (28) Slow Start Capacitor Selection The slow start capacitor determines the minimum amount of time it takes for the output voltage to reach its nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This is also used if the output capacitance is very large and would require large amounts of current to quickly charge the capacitor to the output voltage level. The large currents necessary to charge the capacitor may make the TPS54521 reach the current limit or excessive current draw from the input power supply may cause the input voltage rail to sag. Limiting the output voltage slew rate solves both of these problems. The soft start capacitor value can be calculated using Equation 29. The example circuit has the soft start time set to an arbitrary value of 3.5 ms which requires a 10 nF capacitor. In the TPS54521, Iss is 2.3 uA and Vref is 0.8 V. Tss(ms) × Iss( m A ) C7(nF) = Vref ( V ) (29) Bootstrap Capacitor Selection A 0.1 µF ceramic capacitor must be connected between the BOOT to PH pin for proper operation. It is recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have 10 V or higher voltage rating. Under Voltage Lockout Set Point The Under Voltage Lock Out (UVLO) can be adjusted using the external voltage divider network of R1 and R2. R1 is connected between VIN and the EN pin of the TPS54521 and R2 is connected between EN and GND. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down or brownouts when the input voltage is falling. For the example design, the supply should turn on and start switching once the input voltage increases above 6.806V (UVLO start or enable). After the regulator starts switching, it should continue to do so until the input voltage falls below 4.824 V (UVLO stop or disable). Equation 2 and Equation 3 can be used to calculate the values for the upper and lower resistor values. For the stop voltages specified, the nearest standard resistor value for R1 is 511 kΩ and for R2 is 100 kΩ. Output Voltage Feedback Resistor Selection The resistor divider network, R8 and R9, is used to set the output voltage. For this example design, 10 kΩ was selected for R9. Using Equation 30, R8 is calculated as 52.5 kΩ. The nearest standard 1% resistor is 52.3 kΩ. Vout - Vref R8 = R9 Vref (30) Minimum Output Voltage Due to the internal design of the TPS54521, there is a minimum output voltage limit for any given input voltage. The output voltage can never be lower than the internal voltage reference of 0.8 V. Above 0.8 V, the output voltage may be limited by the minimum controllable on time. The minimum output voltage in this case is given by Equation 31. Voutmin = Ontimemin × Fsmax (Vinmax + Ioutmin (RDS2min - RDS1min ))- Ioutmin (RL + RDS2min ) Where: Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links :TPS54521 25 TPS54521 SLVS981C – JUNE 2010 – REVISED AUGUST 2013 www.ti.com Voutmin = minimum achievable output voltage Ontimemin = minimum controllable on-time (135 nsec maximum) Fsmax = maximum switching frequency including tolerance Vinmax = maximum input voltage Ioutmin = minimum load current RDS1min = minimum high side MOSFET on resistance (57 mΩ typical) RDS2min = minimum low side MOSFET on resistance (50 mΩ typical) RL = series resistance of output inductor (31) Compensation Component Selection There are several industry techniques used to compensate DC/DC regulators. The method presented here is easy to calculate and yields high phase margins. For most conditions, the regulator has a phase margin between 60 and 90 degrees. The method presented here ignores the effects of the slope compensation that is internal to the TPS54521. Since the slope compensation is ignored, the actual crossover frequency is usually lower than the crossover frequency used in the calculations. Use SwitcherPro™ software for a more accurate design. With the low frequency zero from the Poscap output capacitor adding phase and by using type III compensation to give an additional phase boost, a high bandwidth, high phase margin design can be realized. This design targets a crossover frequency (bandwidth) of 1/10th of the switching frequency (70 kHz). First, the modulator pole, fpmod, and the ESR zero, fzmod, must be calculated using Equation 32 and Equation 33. They are at 723 Hz and 18.1 kHz, respectively. Iout f pmod = 2 × p × Vout × Co (32) 1 f zmod = 2 × p × RESR × Co (33) Now the compensation components can be calculated. First, calculate the value for C6 for a crossover frequency of 70 kHz. Using Equation 34, the nearest standard value for C6 is 220 pF. gmea × Vref × gmps × ESR C6 = 2p × f c × Vout (34) Along with C6, R4 creates a pole to cancel the gain caused by the ESR zero of the power stage, fzmod. To keep some of the phase from the zero, this pole is placed at roughly twice the frequency of the zero. The value of R4 needed to set the pole at the desired frequency is given by Equation 35. (ESR × Co ) R4 = (2 × C6 ) (35) Next calculate the value of C4. Together with R4, C4 places a compensation zero at the modulator pole frequency, fpmod. Use Equation 36 to determine the value of C4. (Vout × Co ) C4 = (Iout × R4 ) (36) Using Equation 35 and Equation 36, the standard values for R4 and C4 are 20 kΩ and 0.01 µF. In order to provide a zero around the crossover frequency to boost the phase at crossover, a feedforward capacitor (C11) is added in parallel to R8. The value of this capacitor is given by Equation 37. 1 C11 = (2 × p × R8 × fc ) (37) The closest standard value is 47 pF. Use of the feedforward capacitor, C11, creates a low AC impedance path from the output voltage to the VSENSE input of the IC that can couple noise at the switching frequency into the control loop. Use of a feedforward capacitor is not recommended for high output voltage ripple designs (greater than 15 mV peak to peak at the VSENSE input) operating at duty cycles of less than 30%. When using the feedforward capacitor, C11, always limit the closed loop bandwidth to no more than 1/10th of the switching frequency, fsw. 26 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links :TPS54521 TPS54521 www.ti.com SLVS981C – JUNE 2010 – REVISED AUGUST 2013 Application Curves from the Design Example STARTUP with VIN (1 Ω Load) LOAD TRANSIENT Vin = 12 V Vout = 50 mV / div (AC coupled) Vin = 10 V / div EN = 2 V / div SS/TR = 1 V / div Iout = 1 A / div (0 A to 3 A load step) Vout = 2 V / div Time = 2 msec / div Time = 50 μsec / div Figure 35. Figure 36. STARTUP with VIN (No Load) STARTUP with EN (1 Ω Load) Vin = 10 V / div Vin = 10 v / div EN = 2 V / div EN = 2 V / div SS/TR = 1 V / div SS/TR = 1 V / div Vout = 2 V / div Vout = 2 V / div Time = 2 msec / div Time = 2 msec / div Figure 37. Figure 38. STARTUP with EN (No Load) STARTUP on VIN with PRE-BIAS (1 Ω Load) Vin = 10 V / div Vin = 5 V / div EN = 2 V / div SS/TR = 1 V / div Vout = 2 V / div Vout starting from 1 V pre-bias voltage Vout = 2 V / div Time = 2 msec / div Time = 2 msec / div Figure 39. Figure 40. Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links :TPS54521 27 TPS54521 SLVS981C – JUNE 2010 – REVISED AUGUST 2013 www.ti.com STARTUP and SHUTDOWN on EN with PRE-BIAS (1 Ω Load) SHUTDOWN with VIN (1 Ω Load) Vin = 10 V / div EN = 2 V / div EN = 2 V / div SS/TR = 1 V / div Vout = 2 V / div Vout = 2 V / div Vout starting and stopping from 1 V pre-bias voltage Time = 2 msec / div Time = 2 msec / div Figure 41. Figure 42. SHUTDOWN with EN (1 Ω Load) OUTPUT VOLTAGE RIPPLE (1 Ω Load) Vin = 10 V / div Vin = 12 V Vout = 50 mV / div (AC coupled) EN = 2 V / div Inductor Current = 2 A / div SS/TR = 1 V / div PH = 10 V / div Vout = 2 V / div Time = 200 μsec / div Time = 1 μsec / div Figure 43. Figure 44. INPUT VOLTAGE RIPPLE (1 Ω Load) Vin = 200 mV / div (AC coupled) OVERCURRENT HICCUP MODE Vin = 12 V Vin = 12 V Load = 0.4 Ω Vout = 5 V / div Inductor Current = 10 A / div Inductor Current = 2 A / div PH = 10 V / div PH = 10 V / div SS/TR = 1 V / div Time = 1 μsec / div Time = 20 msec / div Figure 45. 28 Figure 46. Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links :TPS54521 TPS54521 www.ti.com SLVS981C – JUNE 2010 – REVISED AUGUST 2013 CLOSED LOOP RESPONSE LINE REGULATION 0.05 180 60 150 50 0.04 Phase 40 120 30 90 Gain - dB Gain 10 30 0 0 -30 -10 -60 -20 -90 -30 Vin = 12 V Load = 5 A -40 -120 Percent Line Regulation - % 60 20 Phase - Deg 0.03 0.02 Iout = 5 A 0.01 0 Iout = 2.5 A -0.01 -0.02 -0.03 -60 -180 100000 10000 100 Frequency - Hz Iout = 0 A -0.04 1000000 -150 1000 -50 -0.05 8 9 10 11 12 13 14 15 16 Figure 47. Figure 48. LOAD REGULATION TRACKING PERFORMANCE 10 0.05 10 Vout Vin = 10 V 0.04 17 Input Voltage - V Vin = 8 V 1 1 0.1 0.01 0.1 Ideal Vsense Vsense 0.01 0.01 0.001 0.001 -0.02 0.0001 0.0001 -0.03 0.00001 0.00001 0 Vin = 15 V -0.01 Vin = 17 V Vsense Voltage - V Vin = 12 V 0.02 Output Voltage - V Percent Load Regulation - % 0.03 -0.04 -0.05 0.5 0 1 1.5 2 3 3.5 2.5 Output Current - A 4.5 4 5 0.000001 0.001 0.000001 0.01 1 10 Track In Voltage - V Figure 49. Figure 50. MAXIMUM AMBIENT TEMPERATURE vs IC POWER DISSIPATION JUNCTION TEMPERATURE vs IC POWER DISSIPATION 125 125 TA = room temperature, no air flow TA = room temp TJ - Junction Temperature - °C TA max - Maximum Ambient Temperature - °C 0.1 100 75 50 100 75 50 25 25 0 0.5 1 1.5 2 2.5 3 Pic - IC Power Dissipation - W 3.5 Figure 51. 0 0.5 1 1.5 2 2.5 3 Pic - IC Power Dissipation - W 3.5 Figure 52. Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links :TPS54521 29 TPS54521 SLVS981C – JUNE 2010 – REVISED AUGUST 2013 www.ti.com EFFICIENCY vs LOAD CURRENT 100 95 90 Efficiency - % 85 Vin = 8 V Vin = 12 V 80 Vin = 17 V 75 70 65 60 55 50 0 1 3 2 Load Current - A 4 5 Figure 53. Thermal Performance Figure 54. Thermal Signature of Example Circuit Operating at VIN=12V,VOUT=5V/5A, TA = Room Temperature Table 2. Bill of Materials COUNT 30 RefDes Value Description Size Part Number MFR 1 C2 10µF Capacitor, Ceramic, 25V, X5R, 20% 1206 Std Std 1 C3 4.7µF Capacitor, Ceramic, 25V, X5R, 10% 0805 Std Std 2 C4, C7 0.01µF Capacitor, Ceramic, 50V, X7R, 10% 0603 Std Std 1 C5 0.1µF Capacitor, Ceramic, 16V, X7R, 10% 0603 Std Std 1 C6 220pF Capacitor, Ceramic, 50V, C0G, 5% 0603 Std Std 6TPB220M Sanyo 1 C9 220µF Capacitor, Polymer, 6.3V, 40 mΩ ESR, ±20% 0.138 x 0.110 inch 1 C11 47pF Capacitor, Ceramic, 50V, C0G, 5% 0603 Std Std 1 L1 3.3µH Inductor, 12.6mΩ DCR, 7A, ± 30% 0.484 x 0.484 inch MSS1260332NL Coilcraft 1 R1 511K Resistor, Chip, 1/16W, 1% 0603 Std Std 1 R2 100K Resistor, Chip, 1/16W, 1% 0603 Std Std 1 R3 69.8K Resistor, Chip, 1/16W, 1% 0603 Std Std 1 R4 20K Resistor, Chip, 1/16W, 1% 0603 Std Std 1 R8 52.3K Resistor, Chip, 1/16W, 1% 0603 Std Std 1 R9 10.0K Resistor, Chip, 1/16W, 1% 0603 Std Std Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links :TPS54521 TPS54521 www.ti.com SLVS981C – JUNE 2010 – REVISED AUGUST 2013 Table 2. Bill of Materials (continued) COUNT 1 RefDes U1 Value Description Size Part Number MFR TPS54521RHL IC, 17V Input, 5A Output, Sync. Step Down Switcher With Integrated FET QFN14 TPS54521RHL TI PCB Layout Guidelines Layout is a critical portion of good power supply design. See Figure 55 for a PCB layout example. The top layer contains the main power traces for VIN, VOUT, and the PH node. Also on the top layer are connections for the remaining pins of the TPS54521 and a large top side area filled with ground. The top layer ground area should be connected to the internal ground layer(s) using vias at the input bypass capacitor, the output filter capacitor and directly under the TPS54521 device to provide a thermal path from the exposed thermal pad land to ground. The GND pin should be tied directly to the exposed thermal pad under the IC. For operation at full rated load, the top side ground area together with the internal ground plane, must provide adequate heat dissipating area. There are several signals paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supply's performance. To help eliminate these problems, the PVIN pin should be bypassed to ground with a low ESR ceramic bypass capacitor with X5R or X7R dielectric. Care should be taken to minimize the loop area formed by the bypass capacitor connections, the PVIN pins, and the ground connections. The VIN pin must also be bypassed to ground using a low ESR ceramic capacitor with X5R or X7R dielectric. Make sure to connect this capacitor to the quiet analog ground trace rather than the power ground trace of the PVIN bypass capacitor. Since the PH connection is the switching node, the output inductor should be located close to the PH pins, and the area of the PCB conductor minimized to prevent excessive capacitive coupling. The output filter capacitor ground should use the same power ground trace as the PVIN input bypass capacitor. Try to minimize this conductor length while maintaining adequate width. The small signal components should be grounded to the analog ground path as shown. The RT/CLK pin is sensitive to noise so the RT resistor should be located as close as possible to the IC and routed with minimal lengths of trace. The additional external components can be placed approximately as shown. It may be possible to obtain acceptable performance with alternate PCB layouts. However, this layout has been shown to produce good results and is meant as a guideline. Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links :TPS54521 31 TPS54521 SLVS981C – JUNE 2010 – REVISED AUGUST 2013 www.ti.com TOPSIDE GROUND AREA FREQUENCY SET RESISTOR PVIN INPUT BYPASS CAPACITOR RT/CLK PWRGD GND GND OUTPUT FILTER CAPACITOR BOOT CAPACITOR BOOT EXPOSED THERMAL PAD AREA PH PVIN PH PVIN EN VIN SS/TR VSENSE PVIN OUTPUT INDUCTOR VOUT PH COMP VIN SLOW START CAPACITOR UVLO SET RESISTORS VIN INPUT BYPASS CAPACITOR FEEDBACK RESISTORS COMPENSATION NETWORK ANALOG GROUND TRACE 0.010 in. Diameter Thermal VIA to Ground Plane VIA to Ground Plane Etch Under Component Figure 55. PCB Layout Estimated Circuit Area The estimated printed circuit board area for the components used in the design of Figure 34 is 0.5 in2 (323 mm2). This area does not include test points or connectors. 32 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links :TPS54521 TPS54521 www.ti.com SLVS981C – JUNE 2010 – REVISED AUGUST 2013 REVISION HISTORY Changes from Original (July 2010) to Revision A Page • Added "Type 3" block around C11 ..................................................................................................................................... 21 • Changed Equation 25 ......................................................................................................................................................... 24 • Changed graphics in Application Curves from the Design Example section ...................................................................... 27 • Deleted graph JUNCTION TEMPERATURE vs LOAD CURRENT .................................................................................... 29 • Changed Figure 54 ............................................................................................................................................................. 30 Changes from Revision A (August 2010) to Revision B Page • Deleted Swift™ from the data sheet title .............................................................................................................................. 1 • Deleted Feature Item: For SWIFT™ Documentation and SwitcherPro™, visit http://www.ti.com/swift ............................... 1 Changes from Revision B (February 2012) to Revision C • Page Changed BOOT-PH From: 0 to 7 V To: 0 to 8 V in the ABSOLUTE MAXIMUM RATINGS table ....................................... 2 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links :TPS54521 33 PACKAGE OPTION ADDENDUM www.ti.com 19-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) TPS54521RHLR ACTIVE VQFN RHL 14 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 54521 Samples TPS54521RHLT ACTIVE VQFN RHL 14 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 54521 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of