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TPS560200
SLVSC81C – SEPTEMBER 2013 – REVISED FEBRUARY 2016
TPS560200 4.5-V to 17-V Input, 500-mA Synchronous Step-Down Converter With
Advanced Eco-Mode™
1 Features
3 Description
•
The TPS560200 is an 17-V, 500-mA, low-Iq, adaptive
on-time D-CAP2 mode synchronous monolithic buck
converter with integrated MOSFETs in easy-to-use 5pin SOT-23 package.
1
•
•
•
•
•
•
•
•
•
•
•
•
Integrated Monolithic 0.95-Ω High-Side and 0.33Ω Low-Side MOSFETs
500-mA Continuous Output Current
Output Voltage Range: 0.8 V to 6.5 V
0.8-V Voltage Reference With ±1.3% Accuracy
Over Temperature
Auto-Skip Advanced Eco-Mode™ for High
Efficiency at Light Loads
D-CAP2™ Mode Enables Fast Transient
Responses
No External Compensation Needed
600-kHz Switching Frequency
2-ms Internal Soft-Start
Safe Start-Up into Prebiased VOUT
Thermal Shutdown
–40°C to 125°C Operating Junction Temperature
Range
Available in 5-Pin SOT-23 Package
The TPS560200 lets system designers complete the
suite of various end-equipment power bus regulators
with a cost-effective, low component count and low
standby current solution. The main control loop for
the device uses the D-CAP2 mode control that
provides a fast transient response with no external
compensation components. The adaptive on-time
control supports seamless transition between PWM
mode at higher load conditions and advanced EcoMode operation at light loads.
The TPS560200 also has a proprietary circuit that
enables the device to adopt to both low equivalent
series resistance (ESR) output capacitors, such as
POSCAP or SP-CAP, and ultra-low ESR ceramic
capacitors. The device operates from 4.5-V to 17-V
VIN input. The output voltage can be programmed
between 0.8 V and 6.5 V. The device also features a
fixed 2-ms soft-start time. The device is available in
the 5-pin SOT-23 package.
2 Applications
•
•
•
•
Set Top Boxes
Modems
DTBs
ASDLs
Device Information(1)
PART NUMBER
TPS560200
PACKAGE
SOT (5)
BODY SIZE (NOM)
2.90 mm × 1.60 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
Lo
VIN
VIN
VOUT
PH
Cin
Co
R1
EN
VSENSE
R2
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS560200
SLVSC81C – SEPTEMBER 2013 – REVISED FEBRUARY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
4
6
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 7
7.1 Overview ................................................................... 7
7.2 Functional Block Diagram ......................................... 7
7.3 Feature Description................................................... 7
7.4 Device Functional Modes.......................................... 9
8
Application and Implementation ........................ 10
8.1 Application Information............................................ 10
8.2 Typical Application ................................................. 10
9 Power Supply Recommendations...................... 14
10 Layout................................................................... 14
10.1 Layout Guidelines ................................................. 14
10.2 Layout Example .................................................... 14
11 Device and Documentation Support ................. 15
11.1
11.2
11.3
11.4
Device Support......................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
15
15
15
15
12 Mechanical, Packaging, and Orderable
Information ........................................................... 15
4 Revision History
Changes from Revision B (February 2015) to Revision C
•
Deleted SWIFT™ from the data sheet title ........................................................................................................................... 1
Changes from Revision A (Janurary 2015) to Revision B
•
2
Page
Removed note from ENABLE (EN PIN) to indicate that the parameters are production tested ........................................... 5
Changes from Original (September 2013) to Revision A
•
Page
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1
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5 Pin Configuration and Functions
DBV Package
5-Pin SOT-23
(Top View)
EN
1
GND
2
PH
3
5
VSENSE
4
VIN
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
EN
1
I
GND
2
—
Enable pin. Float to enable
Return for control circuitry and low-side power MOSFET
PH
3
O
The switch node
VIN
4
I
Supplies the control circuitry of the power converter
VSENSE
5
I
Converter feedback input. Connect to output voltage with feedback resistor divider
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6 Specifications
6.1 Absolute Maximum Ratings (1)
Input voltage
Output voltage
MIN
MAX
VIN
–0.3
20
EN
–0.3
7
VSENSE
–0.3
3
PH
–0.6
20
PH 10-ns transient
–2
Sink current
V
20
EN
Source current
±100
µA
PH
Current limit
A
PH
Current limit
A
Operating junction temperature
–40
125
Storage temperature, Tstg
–65
150
(1)
UNIT
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
V
±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VI
Input voltage range
4.5
17
UNIT
V
TJ
Operating junction temperature
–40
125
°C
6.4 Thermal Information
TPS560200
THERMAL METRIC
(1)
DBV
UNIT
5 Pins
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
100
RθJB
Junction-to-board thermal resistance
75.5
ψJT
Junction-to-top characterization parameter
29.2
ψJB
Junction-to-board characterization parameter
3.7
RθJC(bot)
Junction-to-case (bottom) thermal resistance
28.7
(1)
166.8
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
TJ = –40°C to 125°C, VIN = 4.5 V to 17 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE (VIN PIN)
VIN Operating input voltage
VIN Internal UVLO threshold
4.5
VIN Rising
VIN Internal UVLO hysteresis
4
3.9
17
4.35
200
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4.5
V
V
mV
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Electrical Characteristics (continued)
TJ = –40°C to 125°C, VIN = 4.5 V to 17 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN Shutdown supply current
EN = 0 V, VIN = 12 V
2.0
3.7
9
µA
VIN Operating– non switching supply current
VSENSE = 850 mV, VIN = 12 V
35
60
95
µA
1.16
1.29
V
ENABLE (EN PIN)
Enable threshold
Internal Soft-Start
Rising
Falling
1.05
VSENSE ramps from 0 V to 0.8 V
1.13
V
2
ms
OUTPUT VOLTAGE
25°C, VIN = 12 V, VOUT = 1.05 V, IOUT = 5
mA, Pulse-Skipping
Voltage reference
0.796
0.804
0.812
V
25°C, VIN = 12 V, VOUT = 1.05 V, IOUT =
100 mA, Continuous current mode
0.792
0.800
0.808
V
VIN = 12 V, VOUT = 1.05 V, IOUT = 100
mA, Continuous current mode
0.789
0.800
0.811
V
MOSFET
High-side switch resistance (1) (2)
VIN = 12 V
0.50
0.95
1.50
Ω
Low-side switch resistance (1)
VIN = 12 V
0.20
0.33
0.55
Ω
LOUT = 10 µH, Valley current, VOUT = 1.05
V
550
650
775
mA
CURRENT LIMIT
Low-side switch sourcing current limit
THERMAL SHUTDOWN
Thermal shutdown
Thermal shutdown hysteresis
170
°C
10
°C
ON-TIME TIMER CONTROL
On time
VIN = 12 V
Minimum off time
25°C, VSENSE = 0.5 V
130
165
200
ns
250
400
ns
63
69
%VREF
OUTPUT UNDERVOLTAGE PROTECTION
Output UVP threshold
Falling
Hiccup time
(1)
(2)
56
15
ms
Not production tested
Measured at pins
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6.6 Typical Characteristics
VIN = 12 V, TA = 25°C (unless otherwise noted).
6
Ivccsdn - Shutdown Current (µA)
ICC - Supply Current (µA)
100
80
60
40
20
0
EN = 0 V
5
4
3
2
1
0
±50
0
50
100
±50
150
TJ Junction Temperature (ƒC)
50
100
150
TJ Junction Temperature (ƒC)
Figure 1. Supply Current vs Junction Temperature
C002
Figure 2. Shutdown Current vs Junction Temperature
40
700
IOUT = 500 mA
Switching Frequency (kHz)
675
EN Input Current (µA)
0
C001
30
20
10
0
650
625
600
575
VOUT = 3.3 V
550
VOUT = 1.05 V
VOUT = 1.8 V
525
500
±10
0
2
4
6
8
10
EN Input Voltage (V)
4
6
8
10
12
14
16
18
VIN - Input Voltage (V)
C003
Figure 3. EN Input Current vs EN Input Voltage
C004
Figure 4. Switching Frequency vs Input Voltage
800
0.806
700
0.804
VSENSE Voltage (V)
fsw - Switching Frequency (kHz)
IO = 100 mA
600
500
VOUT = 3.3 V
400
300
VOUT = 1.05 V
200
0.800
0.798
0.796
100
VOUT = 1.8 V
0.794
±50
0
0.0
0.1
0.2
0.3
0.4
0.5
IO - Output Current (A)
0
50
100
TJ Junction Temperature (ƒC)
150
C006
C005
Figure 5. Switching Frequency vs Output Current
6
0.802
Figure 6. VSENSE Voltage vs Junction Temperature
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7 Detailed Description
7.1 Overview
The TPS560200 is a 500-mA synchronous step-down (buck) converter with two integrated N-channel MOSFETs.
It operates using D-CAP2 mode control. The fast transient response of D-CAP2 control reduces the output
capacitance required to meet a specific level of performance. Proprietary internal circuitry allows the use of lowESR output capacitors including ceramic and special polymer types.
7.2 Functional Block Diagram
VIN
VREF
VSENSE
HS
Drive
VSS
VREF
Soft
Start
EN
SSDONE
START
VIN
XCON
PH
UVLO
VREF
Control
Logic
VIN
LS
Drive
TON
One-Shot
PGND
AGND
GND
VTHERMAL
PH
Thermal
Shutdown
Bandgap
Reference
ZCD
ZCD
VREF
BGOK
VREF
PGND
LS
OCP
7.3 Feature Description
7.3.1 PWM Operation
The main control loop of the TPS560200 is an adaptive on-time pulse width modulation (PWM) controller that
supports a proprietary D-CAP2 mode control. D-CAP2 mode control combines constant on-time control with an
internal compensation circuit for pseudo-fixed frequency and low external component count configuration with
both low-ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal
one-shot timer expires. This one shot is set by the converter input voltage, VIN, and the output voltage, VOUT, to
maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The
one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the
reference voltage. An internal ramp is added to reference voltage to simulate output ripple, eliminating the need
for ESR induced output ripple from D-CAP2 mode control.
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Feature Description (continued)
7.3.2 PWM Frequency and Adaptive On-Time Control
TPS560200 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The
TPS560200 runs with a pseudo-constant frequency of 600 kHz by using the input voltage and output voltage to
set the on-time, one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the
output voltage; therefore, when the duty ratio is VOUT/VIN, the frequency is constant.
7.3.3 Advanced Auto-Skip Eco-Mode Control
The TPS560200 is designed with advanced auto-skip Eco-Mode to increase higher light-load efficiency. As the
output current decreases from heavy-load condition, the inductor current is also reduced. If the output current is
reduced enough, the inductor current ripple valley reaches the zero level, which is the boundary between
continuous conduction and discontinuous conduction modes. The rectifying low-side MOSFET is turned off when
its zero inductor current is detected. As the load current further decreases the converter run into discontinuous
conduction mode. The on-time is kept approximately the same as is in continuous conduction mode. The off-time
increases as it takes more time to discharge the output capacitor to the level of the reference voltage with
smaller load current. The transition point to the light load operation IOUT(LL) current can be calculated in
Equation 1.
(V -V )×VOUT
1
IOUT(LL) =
× IN OUT
2×LOUT ×fsw
VIN
(1)
7.3.4 Soft-Start and Prebiased Soft-Start
The TPS560200 has an internal 2-ms soft-start. When the EN pin becomes high, internal soft-start function
begins ramping up the reference voltage to the PWM comparator.
The TPS560200 contains a unique circuit to prevent current from being pulled from the output during start-up if
the output is prebiased. When the soft-start commands a voltage higher than the prebias level (internal soft-start
becomes greater than feedback voltage VVSENSE), the controller slowly activates synchronous rectification by
starting the first low-side FET gate driver pulses with a narrow on-time. It then increments that on-time on a
cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter.
This scheme prevents the initial sinking of the prebias output, and ensure that the out voltage (VOUT) starts and
ramps up smoothly into regulation and the control loop is given time to transition from prebiased start-up to
normal mode operation.
7.3.5 Current Protection
The output overcurrent protection (OCP) is implemented using a cycle-by-cycle valley detect control circuit. The
switch current is monitored by measuring the low-side FET switch voltage between the PH pin and GND. This
voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature
compensated.
During the on-time of the high-side FET switch, the switch current increases at a linear rate determined by VIN,
VOUT, the on-time and the output inductor value. During the on time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current Iout. The TPS560200 constantly
monitors the low-side FET switch voltage, which is proportional to the switch current, during the low-side on-time.
If the measured voltage is above the voltage proportional to the current limit, an internal counter is incremented
per each switching cycle and the converter maintains the low-side switch on until the measured voltage is below
the voltage corresponding to the current limit at which time the switching cycle is terminated and a new switching
cycle begins. In subsequent switching cycles, the on-time is set to a fixed value and the current is monitored in
the same manner.
There are some important considerations for this type of overcurrent protection. The peak current is the average
load current plus one half of the peak-to-peak inductor current. The valley current is the average load current
minus one half of the peak-to-peak inductor current. Because the valley current is used to detect the overcurrent
threshold, the load current is higher than the overcurrent threshold. Also, when the current is being limited, the
output voltage tends to fall as the demanded load current may be higher than the current available from the
converter. This protection is nonlatching. When the VSENSE voltage becomes lower than 63% of the target
voltage, the UVP comparator detects it. After 7 µs detecting the UVP voltage, device shuts down and re-starts
after hiccup time.
8
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Feature Description (continued)
When the overcurrent condition is removed, the output voltage returns to the regulated value.
7.3.6 Thermal Shutdown
TPS560200 monitors the temperature of itself. If the temperature exceeds the threshold value (typically 170°C),
the device is shut off. This is nonlatch protection.
7.4 Device Functional Modes
7.4.1 Normal Operation
When the input voltage is above the UVLO threshold and the EN voltage is above the enable threshold, the
TPS560200 can operate in its normal switching modes. Normal continuous conduction mode (CCM) occurs when
the minimum switch current is above 0 A. In CCM, the TPS560200 operates at a quasi-fixed frequency of 600
kHz.
7.4.2 Eco-Mode Operation
When the TPS560200 is in the normal CCM operating mode and the switch current falls to 0 A, the TPS560200
begins operating in pulse-skipping Eco-Mode. Each switching cycle is followed by a period of energy-saving
sleep time. The sleep time ends when the VFB voltage falls below the Eco-Mode threshold voltage. As the output
current decreases the perceived time between switching pulses increases.
7.4.3 Standby Operation
When the TPS560200 is operating in either normal CCM or Eco-Mode, it may be placed in standby by asserting
the EN pin low.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS560200 is used as a step-down converter which converts a voltage of 4.5 V to 17 V to a lower voltage.
WEBENCH® software is available to aid in the design and analysis of circuits.
8.2 Typical Application
U1
TPS560200
VIN 4.5-17V
4
C1
C2
10µF
0.1µF
1
5
VIN
PH
L1
VOUT 1.05V, 0.5 A
EN
VSENSE
GND
10µH
3
C3
C4
10µF
10µF
R1
6.19k
C5
open
R2
20.0k
2
Figure 7. Typical Application Schematic
8.2.1 Design Requirements
To begin the design process, the user must know a few application parameters:
Table 1. Design Parameters
PARAMETER
Input voltage range
VALUES
4.5 V to 17 V
Output voltage
1.05 V
Output current
500 mA
Output voltage ripple
10 mV/pp
8.2.2 Detailed Design Procedure
8.2.2.1 Output Voltage Resistors Selection
The output voltage is set with a resistor divider from the output node to the VFB pin. TI recommends using 1%
tolerance or better divider resistors. Start by using Equation 2 to calculate VOUT.
To improve efficiency at light loads, consider using larger value resistors, high resistance is more susceptible to
noise, and the voltage errors from the VSENSE input current are more noticeable.
R1´ 0.8 V
R2 =
VOUT -0.8V
(2)
8.2.2.2 Output Filter Selection
The output filter used with the TPS560200 is an LC circuit. This LC filter has double pole at:
F =
P
2p L
10
1
OUT
x COUT
(3)
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At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the TPS560200. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain
rolls off at a –40 dB per decade rate and the phase drops rapidly. D-CAP2 introduces a high frequency zero that
reduces the gain roll off to –20 dB per decade and increases the phase to 90 degrees one decade above the
zero frequency. The inductor and capacitor selected for the output filter must be selected so that the double pole
of Equation 3 is located below the high frequency zero but close enough that the phase boost provided by the
high frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the
values recommended in Table 2.
Table 2. Recommended Component Values
C5
(pF)
L1
(µH)
Output Voltage
(V)
R1
(kΩ)
R2
(kΩ)
1.0
4.99
20.0
10
10 + 10
1.05
6.19
20.0
10
10 + 10
1.2
10.0
20.0
10
10 + 10
1.5
17.4
20.0
10
10 + 10
1.8
24.9
20.0
optional
10
10 + 10
2.5
42.2
20.0
optional
10
10 + 10
3.3
61.9
20.0
optional
10
10 + 10
5.0
105
20.0
optional
10
10 + 10
MIN
TYP
MAX
C3 + C4
(µF)
Because the DC gain is dependent on the output voltage, the required inductor value increases as the output
voltage increases. Additional phase boost can be achieved by adding a feed-forward capacitor (C5) in parallel
with R1. The feed-forward capacitor is most effective for output voltages at or above 1.8 V.
The inductor peak-to-peak ripple current, peak current, and RMS current are calculated using Equation 4,
Equation 5, and Equation 6. The inductor saturation current rating must be greater than the calculated peak
current and the RMS or heating current rating must be greater than the calculated RMS current. Use 600 kHz for
fSW.
Use 600 kHz for fSW. Make sure the chosen inductor is rated for the peak current of Equation 5 and the RMS
current of Equation 6.
ILPP =
V
- VOUT
V
OUT x IN(max)
V
L
x fsw
IN(max)
OUT
(4)
ILPP
ILPEAK = IOUT +
2
IL
OUT (RMS)
=
IOUT 2 +
(5)
1
2
I
12 LPP
(6)
For this design example, the calculated peak current is 0.582 A and the calculated RMS current is 0.502 A. The
inductor used is a Würth 744777910 with a peak current rating of 2.6 A and an RMS current rating of 2 A.
The capacitor value and ESR determines the amount of output voltage ripple. The TPS560200 is intended for
use with ceramic or other low-ESR capacitors. The recommended values are given in Table 2. Use Equation 7 to
determine the required RMS current rating for the output capacitor.
IC
OUT (RMS)
=
VOUT x (VIN - VOUT )
12 x VIN x LOUT x fsw
(7)
For this design two MuRata GRM32DR61E106KA12L 10-µF output capacitors are used. The typical ESR is 2
mΩ each. The calculated RMS current is 0.047 A and each output capacitor is rated for 3 A.
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8.2.2.3 Input Capacitor Selection
The TPS560200 requires an input decoupling capacitor and a bulk capacitor is needed depending on the
application. A ceramic capacitor over 10 μF is recommended for the decoupling capacitor. An additional 0.1-µF
capacitor (C2) from pin 4 to ground is optional to provide additional high frequency filtering. The capacitor voltage
rating must be greater than the maximum input voltage.
8.2.3 Application Curves
VIN = 12 V, VOUT = 1.05 V, TA = 25°C (unless otherwise noted).
100
90
90
80
80
70
Efficiency - %
Efficiency - %
70
VIN = 5 V
60
VIN = 12 V
50
40
30
60
50
40
30
20
20
10
10
0
0.0
0.1
0.2
0.3
0.4
0
0.001
0.5
Output Current - A
0.01
0.1
1
Output Current - A
C015
Figure 8. Efficiency
C016
Figure 9. Light-Load Efficiency
1.5
0.50
VIN = 5 V
0.40
1.0
0.30
Line Regulation - %
Load Regulation - %
VIN = 12 V
VIN = 5 V
VIN = 12 V
0.5
0.0
±0.5
IOUT = 0.25 A
0.20
0.10
0.00
±0.10
±0.20
±0.30
±1.0
±0.40
±1.5
±0.50
0.0
0.1
0.2
0.3
0.4
0.5
Output Current - A
4
10
12
14
16
18
C018
Figure 11. Line Regulation
60
180
20
60
0
0
Gain
-20
-60
-40
-120
-60
-180
1000000
100
1000
10000
100000
VOUT = 50 mV/div (ac coupled)
120
Phase
Frequency - Hz
Phase - Degrees
40
Gain - dB
8
Input Voltage - V
Figure 10. Load Regulation
IOUT = 200 mA/div
125 mA to 375 mA load step
slew rate = 500 mA / µsec
Time = 200 µs/div
C019
Figure 12. Loop Response, IOUT = 0.25 A
12
6
C017
Figure 13. Transient Response, 25% to 75% Load Step
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VIN = 5 V/div
VOUT = 50 mV/div (ac coupled)
EN = 5 V/div
IOUT = 200 mA/div
10 mA to 250 mA load step
slew rate = 500 mA / µsec
VOUT = 500 mV/div
Time = 200 µs/div
Time = 2 ms/div
Figure 15. Start-Up Relative to EN
Figure 14. Transient Response, 2% to 50% Load Step
VOUT = 20 mV/div (ac coupled)
VOUT = 20 mV/div (ac coupled)
PH = 5 V/div
PH = 5 V/div
Time = 1 µs/div
Figure 16. Output Ripple, IOUT = 500 mA
Time = 5 µs/div
Figure 17. Output Ripple, IOUT = 30 mA
VOUT = 20 mV/div (ac coupled)
PH = 5 V/div
Time = 2 ms/div
Figure 18. Output Ripple, IOUT = 0 mA
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13
TPS560200
SLVSC81C – SEPTEMBER 2013 – REVISED FEBRUARY 2016
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9 Power Supply Recommendations
The TPS560200 is designed to operate from input supply voltage in the range of 4.5 V to 17 V. Buck converters
require the input voltage to be higher than the output voltage for proper operation. The maximum recommended
operating duty cycle is 65%. Using that criteria, the minimum recommended input voltage is VO / 0.65.
10 Layout
10.1 Layout Guidelines
The VIN pin should be bypassed to ground with a low-ESR ceramic bypass capacitor. Take care to minimize the
loop area formed by the bypass capacitor connection, the VIN pin, and the GND pin of the IC. The typical
recommended bypass capacitance is 10-μF ceramic with a X5R or X7R dielectric and the optimum placement is
closest to the VIN and GND pins of the device. An additional high-frequency bypass capacitor may be added.
See Figure 19 for a PCB layout example. The GND pin should be tied to the PCB ground plane at the pin of the
IC. The PH pin should be routed to a small copper area directly adjacent to the pin. Make the circulating loop
from PH to the output inductor, output capacitors and back to GND as tight as possible while preserving
adequate etch width to reduce conduction losses in the copper. Connect the exposed thermal pad to bottom or
internal layer ground plane using vias as shown. Additional vias may be used adjacent to the IC to tie top-side
copper to the internal or bottom layer copper. The additional external components can be placed approximately
as shown. It may be possible to obtain acceptable performance with alternate layout schemes; however, this
layout produced good results and is intended as a guideline.
10.2 Layout Example
VIN
VIN
HIGH FREQENCY
BYPASS
CAPACITOR
GND
VIN
OUTPUT
INDUCTOR
PH
VIN
INPUT
BYPASS
CAPACITOR
VOUT
GND
VSENSE
EN
TO ENABLE
CONTROL
GND
FEEDBACK
RESISTORS
OUTPUT
FILTER
CAPACITOR
GND
OPTIONAL
FEED FORWARD
CAPACITOR
VIA to Ground Plane
Figure 19. Layout Schematic
14
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TPS560200
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SLVSC81C – SEPTEMBER 2013 – REVISED FEBRUARY 2016
11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Trademarks
Eco-Mode, D-CAP2 are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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15
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS560200DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
L562
TPS560200DBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
L562
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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