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TPS57112C-Q1
SLVSDU5A – APRIL 2018 – REVISED NOVEMBER 2019
TPS57112C-Q1 Automotive 2.95-V to 6-V, 2-A, 2-MHz Synchronous Buck Converter
1 Features
3 Description
•
•
The TPS57112C-Q1 device is a full-featured 6-V, 2A, synchronous step-down current-mode converter
with two integrated MOSFETs.
•
•
•
•
•
•
•
•
•
Qualified for automotive applications
AEC-Q100 qualified with the following results:
– Device temperature grade 1: –40°C to +125°C
ambient operating temperature range
– Device HBM ESD classification level H2
– Device CDM ESD classification level C3B
Two 12-mΩ (typical) MOSFETs for high efficiency
at 2-A loads
200-kHz to 2-MHz switching frequency
0.8 V ± 1% voltage reference over temperature
(–40°C to +150°C)
Synchronizes to external clock
Adjustable slow start and sequencing
UV and OV power-good output
–40°C to +150°C operating junction temperature
range
Thermally enhanced 3-mm × 3-mm 16-Pin WQFN
Pin-compatible to TPS54418
2 Applications
•
•
•
•
•
Infotainment head unit
Hybrid instrument cluster
Telematics control unit
ADAS camera module
Point-of-load regulation for high-performance
DSPs, FPGAs, ASICs, and microprocessors
V(VIN)
VIN
The TPS57112C-Q1 device provides accurate
regulation for a variety of loads with a ±1% voltage
reference (Vref) over temperature.
The integrated 12-mΩ MOSFETs and 515-μA typical
supply current maximize efficiency. Using the enable
pin to enter the shutdown mode reduces supply
current to 5.5 µA, typical.
The internal undervoltage lockout setting is 2.45 V,
but programming the threshold with a resistor network
on the enable pin can increase the setting. The slowstart pin controls the output-voltage start-up ramp. An
open-drain power-good signal indicates when the
output is within 93% to 107% of its nominal voltage.
Frequency foldback and thermal shutdown protect the
device during an overcurrent condition.
Device Information
PART NUMBER
PACKAGE
TPS57112C-Q1
WQFN (16)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
1. For all available packages, see the orderable
addendum at the end of the data sheet.
Efficiency vs Output Current
Simplified Schematic
TPS57112C-Q1
The TPS57112C-Q1 device enables small designs by
integrating the MOSFETs, implementing currentmode control to reduce external component count,
reducing inductor size by enabling up to 2-MHz
switching frequency, and minimizing the IC footprint
with a small 3-mm × 3-mm thermally enhanced QFN
package.
100
C(BOOT)
V(VIN) = 3 V
95
BOOT
90
R4
C(I)
V(VIN) = 5 V
L(O)
EN
85
PH
R5
VO
C(O)
R1
PWRGD
VSENSE
SS/TR
RT/CLK
COMP
C(SS)
Rt
R3
C1
GND
AGND
Thermal Pad
Efficiency (%)
1
80
75
70
65
R2
60
f(SW) = 500 kHZ
55
50
VO = 1.8 V
0
0.5
1
Output Current (A)
1.5
2
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS57112C-Q1
SLVSDU5A – APRIL 2018 – REVISED NOVEMBER 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4
4
4
5
5
6
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Switching Characteristics ..........................................
Typical Characteristics Curves .................................
Detailed Description ............................................ 11
7.1 Overview ................................................................. 11
7.2 Functional Block Diagram ....................................... 12
7.3 Feature Description................................................. 12
7.4 Device Functional Modes........................................ 13
8
Application and Implementation ........................ 22
8.1 Application Information............................................ 22
8.2 Typical Application .................................................. 22
9 Power Supply Recommendations...................... 31
10 Layout................................................................... 32
10.1 Layout Guidelines ................................................. 32
10.2 Layout Example .................................................... 33
11 Device and Documentation Support ................. 34
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Support Resources ...............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
34
34
34
34
34
34
34
12 Mechanical, Packaging, and Orderable
Information ........................................................... 35
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (April 2018) to Revision A
•
2
Page
First public release of data sheet .......................................................................................................................................... 1
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5 Pin Configuration and Functions
VIN
1
VIN
2
VIN
EN
PWRGD
BOOT
RTE Package
16-Pin WQFN With Thermal Pad
Top View
16
15
14
13
12
PH
11
PH
Exposed Thermal Pad
PH
GND
4
9
SS/TR
AGND
5
6
7
8
RT/CLK
10
COMP
3
VSENSE
GND
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
AGND
5
—
Connect analog ground electrically to GND close to the device.
BOOT
13
O
There is a requirement for a bootstrap capacitor between BOOT and PH. A voltage on this capacitor
that is below the minimum required by the BOOT UVLO forces the output to switch off until the capacitor
recharges.
COMP
7
O
Error amplifier output, and input to the output-switch current comparator. Connect frequencycompensation components to this pin.
EN
15
I
Enable pin, internal pullup current source. Pull below 1.2 V to disable. Float to enable. One can use this
pin to set the on-off threshold (adjust UVLO) with two additional resistors.
GND
3
4
—
Power ground. Connect this pin electrically to the thermal pad directly under the IC.
O
The source of the internal high-side power MOSFET, and drain of the internal low-side (synchronous)
rectifier MOSFET.
10
PH
11
12
PWRGD
14
O
An open-drain output; asserts low if output voltage is low due to thermal shutdown, overcurrent,
overvoltage, undervoltage, or EN shutdown.
RT/CLK
8
I
Resistor-timing or external-clock input pin
SS/TR
9
I
Slow-start and tracking. An external capacitor connected to this pin sets the output-voltage rise time.
Another use of this pin is for tracking.
I
Input supply voltage, 2.95 V to 6 V.
I
Inverting node of the transconductance (gm) error amplifier
1
VIN
2
16
VSENSE
Thermal pad
6
—
Connect the GND pin to the exposed thermal pad for proper operation. Connect this thermal pad to any
internal PCB ground plane using multiple vias for good thermal performance.
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6 Specifications
6.1 Absolute Maximum Ratings
See
(1)
MIN
VIN
Input voltage
Output voltage
–0.3
EN
–0.3
7
BOOT
–0.3
PH + 7
VSENSE
–0.3
3
COMP
–0.3
3
PWRGD
–0.3
7
SS/TR
–0.3
3
RT/CLK
–0.3
7
BOOT-PH
–0.3
7
PH
–0.6
7
–2
10
PH 10-ns transient
Source current
Sink current
MAX
UNIT
7
V
V
EN
100
RT/CLK
100
COMP
100
µA
PWRGD
SS/TR
µA
10
mA
100
µA
Junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–65
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
over operating free-air temperature range (unless otherwise noted)
VALUE
Human-body model (HBM), per AEC Q100-002 (1)
V(ESD)
(1)
Electrostatic
discharge
Charged-device model (CDM), per AEC
Q100-011
UNIT
±2000
All pins
±500
Corner pins (1, 4, 5, 8, 9, 12, 13, 16)
±500
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
V(VIN)
Input voltage
2.95
6
V
TA
Operating ambient temperature
–40
125
°C
4
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6.4 Thermal Information
TPS57112C-Q1
THERMAL METRIC (1)
RTE (WQFN)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
43.8
°C/W
RθJC(top)
Junction-to-ambient thermal resistance
46.1
°C/W
RθJB
Junction-to-top characterization parameter
15.5
°C/W
ψJT
Junction-to-board characterization parameter
0.7
°C/W
ψJB
Junction-to-case(top) thermal resistance
15.5
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal resistance
3.8
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
TJ = –40°C to +150°C, VIN = 2.95 V to 6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
VIN UVLO START (output turns on, device starts
switching)
2.45
2.6
VIN UVLO STOP (output turns off, device stops
switching)
2.28
2.5
UNIT
SUPPLY VOLTAGE (VIN PIN)
Internal undervoltage lockout threshold
V
Shutdown supply current
V(EN) = 0 V, 25°C, 2.95 V ≤ V(VIN) ≤ 6 V
5.5
15
μA
Quiescent current – I(q)
V(VSENSE) = 0.9 V, V(VIN) = 5 V, 25°C, Rt = 400 kΩ
515
750
μA
Rising
1.25
Falling
1.18
Enable threshold + 50 mV
–3.2
Enable threshold – 50 mV
–1.65
ENABLE AND UVLO (EN PIN)
Enable threshold
Input current
V
μA
VOLTAGE REFERENCE (VSENSE PIN)
Voltage reference
2.95 V ≤ V(VIN) ≤ 6 V, –40°C 2930 ´ VO(1) - 145 ´ ( VO(1) - VO(2) )
(7)
TPS57112C-Q1
BOOT1
EN1
PH1
VO(1)
EN1
SS/TR1
PWRGD1
SS2
VO(1)
R1
TPS57112C-Q1
VO(2)
BOOT2
EN2
R2
PH2
VO(2)
SS/TR2
VSENSE2
PWRGD2
Figure 27. Schematic for Ratiometric and
Simultaneous Start-Up Sequence
Figure 28. Ratiometric Start-Up Using Coupled
SS/TR Pins
7.4.5 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
The switching frequency of the TPS57112C-Q1 device is adjustable over a wide range from 200 kHz to 2000
kHz by placing a resistor on the RT/CLK pin with a value calculated by Equation 8. An internal amplifier holds
this pin at a fixed voltage when using an external resistor to ground to set the switching frequency. The RT/CLK
is typically 0.5 V. To determine the timing resistance for a given switching frequency, use the curve in Figure 5 or
Equation 8.
247 530 (MW /s)
Rt (kW ) =
f (SW )1.0533 (kHz )
(8)
f (SW ) (kHz ) =
131 904 (MW /s)
Rt 0.9492 (kW )
(9)
To reduce the solution size, set the switching frequency as high as possible, but consider tradeoffs of the
efficiency, maximum input voltage, and minimum controllable on-time.
The minimum controllable on-time is typically 65 ns at full-current load and 120 ns at no load, and limits the
maximum operating input voltage or output voltage.
16
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Device Functional Modes (continued)
7.4.6 Overcurrent Protection
The TPS57112C-Q1 device implements a cycle-by-cycle current limit. During each switching cycle, a comparison
occurs between a voltage derived from the high-side switch current and the voltage on the COMP pin. When the
instantaneous switch-current voltage intersects the COMP voltage, the high-side switch turns off. During
overcurrent conditions that pull the output voltage low, the error amplifier responds by driving the COMP pin high,
increasing the switch current. An internal clamp on the error amplifier output functions as a switch-current limit.
7.4.7 Frequency Shift
To operate at high switching frequencies and provide protection during overcurrent conditions, the TPS57112CQ1 device implements a frequency shift. Without the frequency shift, during an overcurrent condition the low-side
MOSFET may not turn off long enough to reduce the current in the inductor, causing a current runaway. With
frequency shift, an overcurrent condition reduces the switching frequency from 100% to 50%, then 25%, as the
voltage decreases from 0.8 V to 0 V on the VSENSE pin. The frequency shift allows the low-side MOSFET to be
off long enough to decrease the current in the inductor. During start-up, the switching frequency increases as the
voltage on VSENSE increases from 0 V to 0.8 V. See Figure 6 for details.
7.4.8 Reverse Overcurrent Protection
The TPS57112C-Q1 device implements low-side current protection by detecting the voltage across the low-side
MOSFET. When the converter sinks current through its low-side FET, the control circuit turns off the low-side
MOSFET if the reverse current is typically more than 4.5 A. By implementing this additional protection scheme,
the converter is able to protect itself from excessive current during power cycling and start-up into pre-biased
outputs.
7.4.9 Synchronize Using the RT/CLK Pin
The RT/CLK pin can synchronize the converter to an external system clock. See . To implement the
synchronization feature in a system, connect a square wave to the RT/CLK pin with an on-time of at least 75 ns.
If the square wave pulls the pin above the PLL upper threshold, a mode change occurs, and the pin becomes a
synchronization input. The CLK mode disables the internal amplifier, and the pin is a high-impedance clock input
to the internal PLL. Stopping the clocking edges re-enables the internal amplifier, and the mode returns to the
frequency set by the resistor. The square-wave amplitude at this pin must transition lower than 0.6 V and higher
than 1.6 V, typically. The synchronization frequency range is 300 kHz to 2000 kHz. The rising edge of PH
synchronizes to the falling edge of the RT/CLK pin.
TPS57112C-Q1
SYNC Clock = 2 V/div
RT/CLK
PLL
PH = 2 V/div
Clock
Source
Rt
Time = 500 ns/div
Figure 29. Synchronizing to a System Clock
Figure 30. Plot of Synchronizing to System Clock
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Device Functional Modes (continued)
7.4.10 Power Good (PWRGD Pin)
The PWRGD pin output is an open-drain MOSFET. The output goes low when the VSENSE voltage enters the
fault condition by falling below 91% or rising above 109% of the nominal internal reference voltage. There is a
2% hysteresis on the threshold voltage, so when the VSENSE voltage rises to the good condition above 93% or
falls below 107% of the internal voltage reference, the PWRGD output MOSFET turns off. TI recommends using
a pullup resistor between the values of 1 kΩ and 100 kΩ to a voltage source that is 6 V or less. PWRGD is in a
valid state once the VIN input voltage is greater than 1.1 V.
7.4.11 Overvoltage Transient Protection
The TPS57112C-Q1 device incorporates an overvoltage transient protection (OVTP) circuit to minimize voltage
overshoot when recovering from output fault conditions or strong unload transients. The OVTP feature minimizes
the output overshoot by implementing a circuit to compare the VSENSE pin voltage to the OVTP threshold,
which is 109% of the internal voltage reference. A VSENSE pin voltage greater than the OVTP threshold
disables the high-side MOSFET, preventing current from flowing to the output and minimizing output overshoot.
The VSENSE voltage dropping lower than the OVTP threshold allows the high-side MOSFET to turn on during
the next clock cycle.
7.4.12 Thermal Shutdown
The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 168°C.
The thermal shutdown forces the device to stop switching when the junction temperature exceeds the thermal
trip threshold. Once the die temperature decreases below 148°C, the device reinitiates the power-up sequence
by discharging the SS pin to below 60 mV. The thermal shutdown hysteresis is 20°C.
7.4.13 Small-Signal Model for Loop Response
Figure 31 shows an equivalent model for the TPS57112C-Q1 control loop, which one can model in a circuit
simulation program to check frequency response and dynamic load response. The error amplifier is a
transconductance amplifier with a gm of 245 μS. One can model the error amplifier using an ideal voltagecontrolled current source. Resistor R0 and capacitor C0 model the open-loop gain and frequency response of the
amplifier. The 1-mV ac voltage source between nodes a and b effectively breaks the control loop for the
frequency-response measurements. Plotting a over c vs frequency shows the small-signal response of the
frequency compensation. Plotting a over b vs frequency shows the small-signal response of the overall loop. One
can check the dynamic loop response by replacing R(L) with a current source with the appropriate load-step
amplitude and step rate in a time-domain analysis.
PH
VO
Power Stage
14 S
a
b
R1
c
R(ESR)
R(L)
COMP
0.8 V
R3
C0
C2
C1
R0
gm
245 µS
VSENSE
C(OUT)
R2
Figure 31. Small-Signal Model for Loop Response
18
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Device Functional Modes (continued)
7.4.14 Simple Small-Signal Model for Peak-Current-Mode Control
Figure 31 is a simple small-signal model that one can use to understand how to design the frequency
compensation. A voltage-controlled current source (duty-cycle modulator) supplying current to the output
capacitor and load resistor approximates the TPS57112C-Q1 power stage. Equation 10 shows the control-tooutput transfer function, which consists of a dc gain, one dominant pole, and one ESR zero. The quotient of the
change in switch current and the change in COMP pin voltage (node c in Figure 31) is the power-stage
transconductance. The gm for the TPS57112C-Q1 device is 14 S. The low-frequency gain of the power-stage
frequency response is the product of the transconductance and the load resistance, as shown in Equation 11. As
the load current increases and decreases, the low-frequency gain decreases and increases, respectively. This
variation with load may seem problematic at first glance, but the dominant pole moves with load current [see
Equation 12]. The dashed line in the right half of Figure 32 highlights the combined effect. As the load current
decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover frequency the same
for the varying load conditions, which makes it easier to design the frequency compensation.
VO
V(C)
A(dc)
R(ESR)
gm(ps)
f(p)
R(L)
C(OUT)
f(z)
Figure 32. Simple Small-Signal Model and Frequency Response for Peak-Current-Mode Control
æ
ö
s
ç 1+
÷
ç 2p × f ( z) ÷
VO
è
ø
= A (dc) ´
V(C)
æ
ö
s
ç 1+
÷
ç 2p × f(p) ÷
è
ø
A (dc) = gm(ps) ´ R (L)
f (p) =
f (z) =
(10)
(11)
1
C(OUT) ´ R (L) ´ 2p
(12)
1
C(OUT) ´ R (ESR) ´ 2p
(13)
7.4.15 Small-Signal Model for Frequency Compensation
The TPS57112C-Q1 device uses a transconductance amplifier for the error amplifier and readily supports two of
the commonly used frequency-compensation circuits. Figure 33 shows the compensation circuits. The most likely
implementation of Type 2B circuits is in high-bandwidth power-supply designs using low-ESR output capacitors.
Type 2A includes one additional high-frequency pole to attenuate high-frequency noise.
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Device Functional Modes (continued)
VO
R1
VSENSE
gm(ea)
Type 2A
COMP
Vref
R3
R3
R2
R0
C0
5pF
Type 2B
C2
C1
C1
Figure 33. Types of Frequency Compensation
20
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Device Functional Modes (continued)
The design guidelines for TPS57112C-Q1 loop compensation are as follows:
1. Calculate the modulator pole, f(p,mod), and the ESR zero, f(z,mod), using Equation 14 and Equation 15. Derating
the output capacitor (C(OUT)) may be necessary if the output voltage is a high percentage of the capacitor
rating. Use the capacitor manufacturer information to derate the capacitor value. Use Equation 16 and
Equation 17 to estimate a starting point for the crossover frequency, f(c). Equation 16 is the geometric mean
of the modulator pole and the ESR zero, and Equation 17 is the mean of modulator pole and the switching
frequency. Use the lower value of Equation 16 or Equation 17 as the maximum crossover frequency.
I O(max)
f (p,mod) =
2p ´ VO ´ C(OUT)
(14)
f (z,mod) =
1
2p ´ R (ESR) ´ C(OUT)
f (c) =
f (p,mod) ´ f (z,mod)
f (c) =
f (p,mod) ´
(15)
(16)
f (SW)
2
2. Use Equation 18 to calculate the value of R3.
2p ´ f (c) ´ VO ´ C(OUT)
R3 =
g m(ea) ´ Vref ´ g m(ps)
(17)
where
•
•
gm(ea) is the amplifier gain (245 μS)
gm(ps) is the power-stage gain (14 S)
(18)
f (p)
3. Place a compensation zero at the dominant pole
4. Use Equation 19 to calculate the value of C1.
R (L) ´ C(OUT)
C1 =
R3
1
=
C(OUT) ´ R (L) ´ 2p
(19)
5. The use of C2 is optional. If using C2 is necessary, use it to cancel the zero from the ESR of C(OUT).
R (ESR) ´ C(OUT)
C2 =
R3
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
Details on how to use this device in automotive applications appear throughout this device specification. The
following sections provide the typical application use case with equations and methods on selecting the external
components, as well as layout guidelines.
8.2 Typical Application
TPS57112C-Q1
2
Figure 34. High-Frequency, 1.8-V Output Power-Supply Design With Adjusted UVLO
8.2.1 Design Requirements
This example details the design of a high-frequency switching-regulator design using ceramic output capacitors.
A few parameters must be known to start the design process. These parameters are typically determined at the
system level. For this example, use the following known parameters:
PARAMETER
VALUE
Output voltage
1.8 V
Transient response for load step from 1 A to 2 A
ΔV(OUT) = 5%
Maximum output current
2A
Input voltage
5 V nominal, 3 V to 6 V
Output-voltage ripple
< 30 mV p-p
Switching frequency (f(SW))
1000 kHz
22
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8.2.2 Detailed Design Procedure
8.2.2.1 Selecting the Switching Frequency
The first step is to decide on a switching frequency for the regulator. Typically, one wants to choose the highest
switching frequency possible, because this produces the smallest solution size. The high switching frequency
allows for lower-valued inductors and smaller output capacitors compared to a power supply that switches at a
lower frequency. However, the highest switching frequency causes extra switching losses, which hurt the
performance of the converter. The converter is capable of running from 200 kHz to 2 MHz. Unless a small
solution size is an ultimate goal, select a moderate switching frequency of 1 MHz to achieve both a small solution
size and high-efficiency operation. Using Equation 8, calculate the value of R5 to be 180 kΩ. The choice for the
design is a standard 1% 182-kΩ value.
8.2.2.2 Output Inductor Selection
The inductor selected works for the entire TPS57112C-Q1 input-voltage range. To calculate the value of the
output inductor, use Equation 21. The k(IND) coefficient represents the amount of ripple current in the inductor
relative to the maximum output current. The output capacitor filters the inductor ripple current. Therefore,
choosing high inductor ripple currents impacts the selection of the output capacitor, because the output capacitor
must have a ripple-current rating equal to or greater than the inductor ripple current. In general, the inductor
ripple value is at the discretion of the designer; however, k(IND) is normally from 0.1 to 0.3 for the majority of
applications.
For this design example, use k(IND) = 0.3; the calculated value of the inductor is 2.2 µH. For this design, the
choice is a nearest standard value of 1.5 μH. For the output-filter inductor, it is important not to exceed the rms
current and saturation current ratings. Use Equation 23 and Equation 24 to find the rms and peak inductor
currents.
For this design, the rms inductor current is 2 A and the peak inductor current is 2.42 A. The chosen inductor is a
Coilcraft XLA4020-152ME_. It has a saturation current rating of 9.6 A and an rms current rating of 7.5 A.
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The current flowing through the inductor is the inductor ripple current plus the output current. During power up,
faults, or transient load conditions, the inductor current can increase above the calculated peak inductor current
level calculated previously. In transient conditions, the inductor current can increase up to the switch-current limit
of the device. For this reason, the most conservative approach is to specify an inductor with a saturation current
rating equal to or greater than the switch-current limit rather than the peak inductor current.
VI(max) - VO
VO
´
L1 =
I O ´ k (IND)
VI(max) ´ f (SW)
(21)
I(ripple) =
VI(max) - VO
L1
I(Lrms) = I O2 +
I(Lpeak) = I O +
24
´
VO
VI(max) ´ f (SW)
æ VO ´ (VI(max) - VO )
1
´ ç
ç VI(max) ´ L1 ´ f (SW)
12
è
(22)
ö
÷
÷
ø
2
(23)
I(ripple)
2
(24)
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8.2.2.3 Output Capacitor
There are three primary considerations for selecting the value of the output capacitor. The output capacitor
determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in
load current. The output capacitance must be selected based on the most-stringent of these three criteria.
The desired response to a large change in the load current is the first criterion. The output capacitor must supply
the load with current when the regulator cannot. This situation would occur if there are desired hold-up times for
the regulator where the output capacitor must hold the output voltage above a certain level for a specified
amount of time after removal of the input power. The regulator is temporarily not able to supply sufficient output
current if there is a large, fast increase in the current needs of the load, such as transitioning from no load to a
full load. The regulator usually needs two or more clock cycles for the control loop to see the change in load
current and output voltage and adjust the duty cycle to react to the change. Sizing of the output capacitor must
be adequate to supply the extra current to the load until the control loop responds to the load change. The output
capacitance must be large enough to supply the difference in current for two clock cycles while only allowing a
tolerable amount of droop in the output voltage. Equation 25 shows the minimum output capacitance necessary
to meet this requirement.
For this example, the transient load response is specified as a 5% change in VO for a load step from 0 A (no
load) to 1.5 A (50% load). For this example, ΔIO = 1.5 A – 0 A = 1.5 A and ΔVO = 0.05 × 1.8 = 0.09 V. Using
these numbers gives a minimum capacitance of 33 μF. This value does not take the ESR of the output capacitor
into account in the output voltage change. For ceramic capacitors, the ESR is usually small enough to ignore in
this calculation.
Equation 26 calculates the minimum output capacitance needed to meet the output voltage ripple specification.
In this case, the maximum output-voltage ripple is 30 mV. Under this requirement, Equation 26 yields 2.3 µF.
2 ´ DI O
C(OUT) >
f (SW ) ´ DVO
where
•
•
•
C(OUT)
ΔIO is the change in output current
f(SW) is the switching frequency of the regulator
ΔVO is the allowable change in the output voltage
(25)
1
1
´
>
8 ´ f (SW ) VO(ripple)
I(ripple)
where
•
•
•
f(SW) is the switching frequency
VO(ripple) is the maximum allowable output voltage ripple
I(ripple) is the inductor ripple current
(26)
Equation 27 calculates the maximum ESR an output capacitor can have to meet the output-voltage ripple
specification. Equation 27 indicates the ESR should be less than 55 mΩ. In this case, the ESR of the ceramic
capacitor is much less than 55 mΩ.
Factor in additional capacitance de-ratings for aging, temperature, and dc bias, which increase this minimum
value. For this example, use two 22-μF 10-V X5R ceramic capacitors with 3 mΩ of ESR.
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Capacitors generally have limits to the amount of ripple current they can handle without failing or producing
excess heat. Specify an output capacitor that can support the inductor ripple current. Some capacitor data sheets
specify the root-mean-square (RMS) value of the maximum ripple current. One can use Equation 28 to calculate
the rms ripple current the output capacitor must support. For this application, Equation 28 yields 333 mA.
VO(ripple)
R (ESR) <
I(ripple)
(27)
I(Co,rms) =
VO ´ (VI(max) - VO )
12 ´ VI(max) ´ L1 ´ f (SW )
(28)
8.2.2.4 Input Capacitor
The TPS57112C-Q1 device requires a high-quality ceramic, type X5R or X7R, input decoupling capacitor with at
least 4.7 μF of effective capacitance, and in some applications a bulk capacitance. The effective capacitance
includes any dc bias effects. The voltage rating of the input capacitor must be greater than the maximum input
voltage. The capacitor must also have a ripple-current rating greater than the maximum input ripple current of the
TPS57112C-Q1 device. Calculate the input ripple current using Equation 29.
The value of a ceramic capacitor varies significantly over temperature and the amount of dc bias applied to the
capacitor. Minimize the capacitance variations due to temperature by selecting a dielectric material that is stable
over temperature. The usual selection for power regulator capacitors is an X5R or X7R ceramic dielectric,
because they have a high capacitance-to-volume ratio and are fairly stable over temperature. The output
capacitor selection must also take the dc bias into account. The capacitance value of a capacitor decreases as
the dc bias across a capacitor increases.
This example design requires a ceramic capacitor with at least a 10-V voltage rating to support the maximum
input voltage. The selection for this example is one 10-μF capacitor in parallel with one 0.1-μF capacitor, both
with 10-V ratings. The input capacitance value determines the input ripple voltage of the regulator. Use
Equation 30 to calculate the input voltage ripple.
I(Ci,rms) = I O ´
DVI =
VO
VI(min)
´
(VI(min) - VO )
VI(min)
(29)
I O(max) ´ 0.25
C(IN) ´ f (SW )
(30)
Using the design example values, IO(max) = 2 A, C(IN) = 10 μF, f(SW) = 1 MHz, yields an input voltage ripple of 50
mV and an RMS input ripple current of 0.98 A.
8.2.2.5 Slow-Start Capacitor
The slow-start capacitor determines the minimum amount of time it takes for the output voltage to reach its
nominal programmed value during power up. Slow start is useful if a load requires a controlled voltage-slew rate.
Another use for slow start is if the output capacitance is large and would require large amounts of current to
charge the capacitor quickly to the output-voltage level. The large currents necessary to charge the capacitor
may make the TPS57112C-Q1 device reach the current limit, or excessive current draw from the input power
supply may cause the input voltage rail to sag. Limiting the output-voltage slew rate solves both of these
problems.
One can calculate the slow-start capacitor value using Equation 31. For the example circuit, the slow-start time is
not too critical because the output-capacitor value is 44 μF which does not require much current to charge to 1.8
V. The example circuit has the slow-start time set to an arbitrary value of 4 ms, which requires a 10 nF capacitor.
In the TPS57112C-Q1 device, I(SS/TR) is 2.2 μA and Vref is 0.8 V.
t (SS) (ms) ´ I(SS/TR) (mA)
C(SS) (nF) =
Vref (V)
(31)
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8.2.2.6 Bootstrap Capacitor Selection
Connect a 0.1-μF ceramic capacitor between the BOOT and PH pins for proper operation. TI recommends using
a ceramic capacitor with X5R or better-grade dielectric. The capacitor should have a 10-V or higher voltage
rating.
8.2.2.7 Output Voltage and Feedback Resistor Selection
For the example design, the R6 selection is 100 kΩ. Using Equation 32, the calculated value of R7 is 80 kΩ. The
nearest standard 1% resistor is 80.5 kΩ.
Vref
R7 =
´ R6
VO - Vref
(32)
Because of the internal design of the TPS57112C-Q1 device, any given input voltage has a minimum output
voltage limit. The output voltage can never be lower than the internal voltage reference of 0.8 V. Above 0.8 V,
the output voltage may be limited by the minimum controllable on time. The minimum output voltage in this case
is given by Equation 33
(
)
(
VO(min) = t (ONmin) ´ f(SWmax) ´ VI(max) - I O(min) ´ 2 ´ rDS(on) - I O(min) ´ R (L) + rDS(on)
)
where
•
•
•
•
•
•
•
VO(min) = minimum achievable output voltage
t(ONmin) = minimum controllable on-time (65 ns typical. 120 ns no load)
f(SWmax) = maximum switching frequency, including tolerance
VI(max) = maximum input voltage
IO(min) = minimum load current
rDS(on) = minimum high-side MOSFET on-resistance (15 mΩ–19 mΩ)
R(L) = series resistance of output inductor
(33)
There is also a maximum achievable output voltage which is limited by the minimum off-time. The maximum
output voltage is given by Equation 34
(
) (
)
(
VO(max) = 1 - t (OFFmax) ´ f (SWmax) ´ VI(min) - I O(max) ´ 2 ´ rDS(on) - I O(max) ´ R (L) + rDS(on)
)
where
•
•
•
•
•
•
•
VO(max) = maximum achievable output voltage
t(OFFmax) = maximum off-time (60 ns typical)
f(SWmax) = maximum switching frequency, including tolerance
VI(min) = minimum input voltage
IO(max) = maximum load current
rDS(on) = maximum high-side MOSFET on-resistance (19 mΩ–30 mΩ)
R(L) = series resistance of output inductor
(34)
8.2.2.8 Compensation
There are several industry techniques used to compensate dc-dc regulators. The method presented here is easy
to calculate and yields high phase margins. For most conditions, the regulator has a phase margin between 60
and 90 degrees. The method presented here ignores the effects of the slope compensation that is internal to the
TPS57112C-Q1 device. As a result of ignoring the slope compensation, the actual crossover frequency is usually
lower than the crossover frequency used in the calculations. Use SwitcherPro software for a more-accurate
design.
To get started, calculate the modulator pole, f(p,mod), and the ESR zero, f(z,mod), using Equation 35 and
Equation 36. For C(OUT), derating the capacitor is not needed, as the 1.8-V output is a small percentage of the
10-V capacitor rating. If the output is a high percentage of the capacitor rating, use the manufacturer information
for the capacitor to derate the capacitor value. Use Equation 37 and Equation 38 to estimate a starting point for
the crossover frequency, f(c). For the example design, f(p,mod) is 6.03 kHz and f(z,mod) is 1210 kHz. Equation 37 is
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the geometric mean of the modulator pole and the ESR zero, and Equation 38 is the mean of modulator pole and
the switching frequency. Equation 37 yields 85.3 kHz and Equation 38 gives 54.9 kHz. Use the lower value of
Equation 37 and Equation 38 as the approximate crossover frequency. For this example, f(c) is 56 kHz. Next,
calculate the compensation components. Use a resistor in series with a capacitor to create a compensating zero.
A capacitor in parallel with these two components forms the compensating pole (if needed).
I O(max)
f (p,mod) =
2p ´ VO ´ C(OUT)
(35)
f (z,mod) =
1
2p ´ R (ESR) ´ C(OUT)
f (c) =
f (p,mod) ´ f (z,mod)
f (c) =
f (p,mod) ´
(36)
(37)
f (SW)
2
(38)
The compensation design takes the following steps:
1. Set up the anticipated crossover frequency. Use Equation 39 to calculate the resistor value for the
compensation network. In this example, the anticipated crossover frequency (f(c)) is 56 kHz. The power-stage
gain (gmps) is 14 S, and the error-amplifier gain (gmea) is 245 μS.
2p ´ f (c) ´ VO ´ C(OUT)
R3 =
g m(ea) ´ Vref ´ g m(ps)
(39)
2. Place compensation zero at the pole formed by the load resistor and the output capacitor. Calculate the
capacitor for the compensation network from Equation 40.
R0 ´ C0
C3 =
R3
(40)
3. An extra pole can be added to attenuate high-frequency noise. In this application, the extra pole is not
necessary.
From the procedures above, the compensation network includes a 7.68-kΩ resistor and a 3300-pF capacitor.
8.2.2.9 Power-Dissipation Estimate
The following formulas show how to estimate the IC power dissipation under continuous-conduction-mode (CCM)
operation. The power dissipation of the IC (PT) includes conduction loss (P(con)), dead-time loss (P(d)), switching
loss (P(SW)), gate-drive loss (P(gd)), and supply-current loss (P(q)).
P(con) = I O 2 ´ rDS(on)(Temp)
where
•
•
IO is the output current (A)
rDS(on)(Temp) is the on-resistance of the high-side MOSFET with given temperature (Ω)
P(d) = f (SW ) ´ I O ´ 0.7 ´ 60 ´ 10
(41)
-9
where
•
f(SW) is the switching frequency (Hz)
P(SW ) = 1/2 ´ VI ´ I O ´ f (SW ) ´ 8 ´ 10
(42)
-9
where
•
VI is the input voltage (V)
(43)
P(gd) = 2 ´ VI ´ f (SW ) ´ 2 ´ 10 -9
(44)
P(q) = VI ´ 515 ´ 10 -6
(45)
Therefore:
PT = P(con) + P(d) + P(SW ) + P(gd) + P(q)
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where
•
PT is the total device power dissipation (W)
(46)
For a given TA:
T J = TA + R qJA ´ PT
where
•
•
•
TA is the ambient temperature (°C)
TJ is the junction temperature (°C)
RθJA is the thermal resistance of the package (°C/W)
(47)
For a given TJ(max):
T A(max) = TJ(max) - R qJA ´ PT
where
•
•
TJ(max) is maximum junction temperature (°C)
TA(max) is maximum ambient temperature (°C)
(48)
Additional power losses occur in the regulator circuit because of the inductor ac and dc losses and trace
resistance that impact the overall efficiency of the regulator.
8.2.3 Application Curves
100
100
90
90
80
80
V(VIN) = 3.3 V
70
V(VIN) = 5 V
Efficiency (%)
Efficiency (%)
70
60
50
40
60
V(VIN) = 5 V
50
40
30
30
20
20
10
10
0
0
0.5
1.5
1
0
0.01
2
0.1
1
10
Output Current (A)
Output Current (A)
Figure 35. Efficiency versus Load Current
Figure 36. Efficiency versus Load Current
100
100
95
95
90
90
VO = 1.05 V
VO = 1.8 V
80
75
70
75
70
65
60
60
55
55
50
50
0.5
1
1.5
2
0.5
0
Output Current (A)
V(VIN) = 3.3 V
f(SW) = 1 MHz
VO = 1.05 V
VO = 3.3 V
80
65
0
VO = 1.8 V
85
Efficiency (%)
85
Efficiency (%)
V(VIN) = 3.3 V
1
1.5
2
Output Current (A)
TA = 25ºC
Figure 37. Efficiency versus Load Current
1 MHz, 3.3 VIN, TA = 25°C
V(VIN) = 5 V
f(SW) = 1 MHz
TA = 25ºC
Figure 38. Efficiency versus Load Current
1 MHz, 5 VIN, TA = 25°C
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V(VIN) = 2 V/div
V(VIN) = 2 V/div
EN = 1 V/div
EN = 1 V/div
SS/TR = 1 V/div
SS/TR = 1 V/div
VO = 1 V/div
VO = 1 V/div
Time = 5 ms/div
Time = 500 ms/div
Figure 39. Power-Up VO, V(VIN)
Figure 40. Power-Down VO, V(VIN)
V(VIN) = 5 V/div
VO = 100 mV/div (ac-coupled)
VO = 2 V/div
IO = 1 A/div (0-A to 1.5-A load step)
EN = 2 V/div
PWRGD = 5 V/div
Time = 5 ms/div
Time = 200 µs/div
Figure 42. Power-Up VO, V(VIN)
Figure 41. Transient Response, 1.5-A Step
V(VIN) = 5 V/div
VO = 20 mV/div (ac-coupled)
VO = 2 V/div
PH = 2 V/div
EN = 2 V/div
PWRGD = 5 V/div
Time = 500 ns/div
Time = 5 ms/div
Figure 43. Power-Up VO, EN
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Figure 44. Output Ripple, 2 A
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Gain (dB)
V(VIN) = 100 mV/div (ac coupled)
PH = 2 V/div
60
180
50
40
150
120
30
20
90
60
10
30
0
–10
0
–30
–20
–30
–60
–90
–120
–40
Gain
Phase
–50
–60
10
100
0.4
0.4
0.3
0.3
0.2
V(VIN) = 5 V
0.1
0
V(VIN) = 3.3 V
–0.1
1000
10k
Frequency - Hz
–150
–180
1M
100k
Figure 46. Closed-Loop Response, V(VIN) (5 V), 2 A
Output Voltage Deviation (%)
Output Voltage Deviation (%)
Time = 400 ns/div
Figure 45. Input Ripple, 2 A
Phase (degrees)
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–0.2
0.2
0.1
0
–0.1
–0.2
–0.3
–0.3
–0.4
0
0.5
1
1.5
2
–0.4
3
3.5
4
4.5
5
5.5
6
Input Voltage (V)
Output Current (A)
IO = 2 A
Figure 47. Load Regulation versus Load Current
Figure 48. Regulation versus Input Voltage
9 Power Supply Recommendations
By design, the TPS57112C-Q1 device works with an analog supply voltage range of 2.95 V to 6 V. Ensure good
regulation for the input supply, and connect the supply to the VIN pins with the appropriate input capacitor as
calculated in the Input Capacitor section. If the input supply is located more than a few inches from the
TPS57112C-Q1 device, the design may require extra capacitance in addition to the recommended value.
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10 Layout
10.1 Layout Guidelines
Layout is a critical portion of good power-supply design. There are several signal paths that conduct fastchanging currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise
or degrade the power-supply performance. Take care to minimize the loop area formed by the bypass capacitor
connections and the VIN pins. See Figure 49 for a PCB layout example. Tie the GND pins and AGND pin directly
to the thermal pad under the IC. Connect the thermal pad to any internal PCB ground planes using multiple vias
directly under the IC. One can use additional vias to connect the top-side ground area to the internal planes near
the input and output capacitors. For operation at full-rated load, the top-side ground area, along with any
additional internal ground planes, must provide adequate heat dissipating area.
Locate the input bypass capacitor as close to the IC as possible. Route the PH pins to the output inductor.
Because the PH connection is the switching node, locate the output inductor close to the PH pins, and minimize
the area of the PCB conductor to prevent excessive capacitive coupling. Also locate the boot capacitor close to
the device. Connect the sensitive analog ground connections for the following to a separate analog ground trace
as shown:
• Feedback voltage divider
• Compensation components
• Slow-start capacitor
• Frequency-set resistor
The RT/CLK pin is particularly sensitive to noise, so locate the RT resistor as close as possible to the IC and
route traces to minimize their lengths. One can place the additional external components approximately as
shown. It may be possible to obtain acceptable performance with alternate PCB layouts. However, this layout,
meant as a guideline, demonstrably produces good results.
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10.2 Layout Example
VIA to
Ground
Plane
UVLO SET
RESISTORS
VIN
INPUT
BYPASS
CAPACITOR
BOOT
PWRGD
EN
VIN
VIN
BOOT
CAPACITOR
VIN
OUTPUT
INDUCTOR
PH
VIN
PH
EXPOSED
POWERPAD
AREA
GND
GND
OUTPUT
FILTER
CAPACITOR
PH
PH
VOUT
SLOW START
CAPACITOR
RT/CLK
COMP
VSENSE
AGND
SS
FEEDBACK
RESISTORS
ANALOG
GROUND
TRACE
FREQUENCY
SET
RESISTOR
COMPENSATION
NETWORK
TOPSIDE
GROUND
AREA
VIA to Ground Plane
Figure 49. PCB Layout Example
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.1.2 Development Support
For more SWIFT™ documentation, see the TI Web site at www.ti.com/swift.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Enable Functionality and Adjusting Undervoltage Lockout for TPS57112-Q1
• Texas Instruments, Interfacing TPS57xxx-Q1,TPS65320-Q1 Family, and TPS65321-Q1 Devices With Low
Impendence External Clock Drivers
• Texas Instruments, TPS57112-Q1 High Frequency (2.35 MHz) Operation
• Texas Instruments, TPS57112EVM User's Guide
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
SWIFT, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
34
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS57112CQRTERQ1
ACTIVE
WQFN
RTE
16
3000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
7112Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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