TPS61103PWG4

   www.ti.com TPS61100, TPS61103 TPS61106, TPS61107    SLVS411B – JUNE 2002 – REVISED APRIL 2004 DUAL-OUTPUT, SINGLE-CELL BOOST CONVERTER • FEATURES • • • • • • • • • • Synchronous 95% Efficient Boost Converter Integrated 120 mA LDO for Second Output Voltage TSSOP-20 and QFN-24 Package 65 µA (Typ) Total Device Quiescent Current 0.8 V to 3.3 V Input Voltage Range Adjustable Output Voltage up to 5.5 V and Fixed Output Voltage Options Power-Save Mode for Improved Efficiency at Low Output Power Battery Supervision Power Good Output Pushbutton Function for Start-Up • • • • Low EMI-Converter (Integrated Antiringing Switch) Load Disconnect During Shutdown Auto Discharge Allows the Device to Discharge Output Capacitor During Shutdown Overtemperature Protection EVM Available (TPS6110XEVM-216) APPLICATIONS • • All Single or Dual Cell Battery Operated Products Which Use Two System Voltages Like DSP C5X Applications Internet Audio Player, PDAs, Digital Still Cameras and Other Portable Equipment TYPICAL APPLICATION SWN VBAT Battery VOUT LBI VCC1 TPS61100 FB Control Inputs OFF ON OFF ON OFF OFF ON OFF ON ON SKIPEN ADEN EN ENPB LDOEN GND PGOOD LBO1 LBO2 Control Outputs LDOIN LDOOUT VCC2 PGND LDOSENSE Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2002–2004, Texas Instruments Incorporated TPS61100, TPS61103 TPS61106, TPS61107 www.ti.com SLVS411B – JUNE 2002 – REVISED APRIL 2004 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION The TPS6110x devices provide a complete power supply solution for products powered by either one or two Alkaline, NiCd, or NiMH battery cells. The converter generates two stable output voltages that are either adjusted by an external resistor divider or fixed internally on the chip. It stays in operation with supply voltages down to 0.8 V. The implemented boost converter is based on a fixed frequency, pulse-width-modulation (PWM) controller using a synchronous rectifier to obtain maximum efficiency. The maximum peak current in the boost switch is limited to a value of 1800 mA. The converter can be disabled to minimize battery drain. During shutdown, the load is completely disconnected from the battery. An auto discharge function allows discharging the output capacitors during shutdown mode. This is especially useful in microcontroller applications where the microcontroller or microprocessor should not remain active due to the stored voltage on the output capacitors. Programming the ADEN-pin disables this feature. A low-EMI mode is implemented to reduce ringing and in effect lower radiated electromagnetic energy when the converter enters the discontinuous conduction mode. A power good output at the boost stage provides additional control of cascaded power supply components. The built-in LDO can be used for a second output voltage derived either from the boost output or directly from the battery. The output voltage of this LDO can be programmed by an external resistor divider or is fixed internally on the chip. The LDO can be enabled separately i.e., using the power good of the boost stage. The device is packaged in a 20-pin TSSOP (20 PW) package or in a 24-pin QFN (24 RGE) package. AVAILABLE PACKAGE OPTIONS PACKAGE CODE 20-Pin TSSOP PW 24-Pin QFN RGE AVAILABLE OUTPUT VOLTAGE OPTIONS TA 40°C to 85°C (1) 2 OUTPUT VOLTAGE DC/DC OUTPUT VOLTAGE LDO PART NUMBER (1) PART NUMBER (1) Adjustable Adjustable TPS61100PW TPS61100RGE 3.3 V Adjustable TPS61103PW TPS61103RGE 3.3 V 1.5 V TPS61106PW TPS61106RGE 3.3 V 1.8 V TPS61107PW TPS61107RGE The PW package is available taped and reeled. Add R suffix to device type (e.g., TPS61100PWR) to order quantities of 2000 devices per reel. The RGE package is only available in reels. Add R suffix to device type (e.g. TPS61100RGER) to order quantities of 3000 devices per reel. TPS61100, TPS61103 TPS61106, TPS61107 www.ti.com SLVS411B – JUNE 2002 – REVISED APRIL 2004 FUNCTIONAL BLOCK DIAGRAM SWN VOUT VBAT AntiRinging Auto Discharge PGND Gate CONTROL PGND PGND Regulator Error Amplifier FB Vref Control Logic Oscillator Temperature Control EN ENPB PGOOD LDOEN SKIPEN ADEN GND LBI LBO1 LBO2 LDOIN LDOOUT Low Dropout Regulator Auto Discharge Low Battery Comparator LDOSENSE GND 3 TPS61100, TPS61103 TPS61106, TPS61107 www.ti.com SLVS411B – JUNE 2002 – REVISED APRIL 2004 Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION PW RGE ADEN 5 3 I Auto discharge enable (1/VBAT enabled, 0/GND disabled) EN 4 2 I Boost-enable input. (1/VBAT enabled, 0/GND disabled) ENPB 3 24 I Boost-enable input (pushbutton). (0/GND enabled. 1/VBAT disabled) FB 20 21 I Boost-voltage feedback of adjustable versions GND 10 8 I/O LBI 2 23 I Low battery comparator input (comparator enabled with EN) LBO1 12 11 O Low battery comparator output 1 (open drain) LBO2 13 12 O Low battery comparator output 2 (open drain) LDOEN 7 5 I LDO-enable input (1/VBAT enabled, 0/GND disabled) LDOOUT 9 7 O LDO output LDOIN 8 6 I LDO input LDOSENSE 6 4 I LDO feedback for voltage adjustment, must be connected to LDOOUT at fixed output voltage versions NC 17 1 PGND 11 9, 10 I/O Power ground PGOOD 15 15 O Boost output power good (1 : good, 0 : failure) (open drain) SKIPEN 18 18 I Enable/disable Power save mode (1: VBAT enabled, 0: GND disabled) 14, 16 13, 14, 16, 17 I Boost switch input No connection VBAT 1 22 I Supply pin VOUT 19 19, 20 O Boost output PW PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 NC – No internal connection 4 20 19 18 17 16 15 14 13 12 11 FB VOUT SKIPEN NC SWN PGOOD SWN LBO2 LBO1 PGND ENPB LBI VBAT FB VOUT VOUT VBAT LBI ENPB EN ADEN LDOSENSE LDOEN LDOIN LDOOUT GND RGE PACKAGE (TOP VIEW) NC EN ADEN LDOSENSE LDOEN LDOIN TPS6110X LDOOUT GND PGND PGND LBO1 LBO2 SWN Control/logic ground SKIPEN SWN SWN PGOOD SWN SWN TPS61100, TPS61103 TPS61106, TPS61107 www.ti.com SLVS411B – JUNE 2002 – REVISED APRIL 2004 DETAILED DESCRIPTION SYNCHRONOUS RECTIFIER The device integrates an N-channel and a P-channel MOSFET transistor to realize a synchronous rectifier. Because the commonly used discrete Schottky rectifier is replaced with a low RDS(ON) PMOS switch, the power conversion efficiency reaches 95%. To avoid ground shift due to the high currents in the NMOS switch, two separate ground pins are used. The reference for all control functions is the GND pin. The source of the NMOS switch is connected to PGND. Both grounds must be connected on the PCB at only one point close to the GND pin. A special circuit is applied to disconnect the load from the input during shutdown of the converter. In conventional synchronous rectifier circuits, the backgate diode of the high-side PMOS is forward biased in shutdown and allows current flowing from the battery to the output. This device however uses a special circuit which takes the cathode of the backgate diode of the high-side PMOS and disconnects it from the source when the regulator is not enabled (EN = low). The benefit of this feature for the system design engineer is that the battery is not depleted during shutdown of the converter. No additional components have to be added to the design to make sure that the battery is disconnected from the output of the converter. CONTROLLER CIRCUIT The controller circuit of the device is based on a fixed frequency multiple feedforward controller topology. Input voltage, output voltage, and voltage drop on the NMOS switch are monitored and forwarded to the regulator. So changes in the operating conditions of the converter directly affect the duty cycle and must not take the indirect and slow way through the control loop and the error amplifier. The control loop, determined by the error amplifier, only has to handle small signal errors. The input for it is the feedback voltage on the FB pin or, at fixed output voltage versions, the voltage on the internal resistor divider. It is compared with the internal reference voltage to generate an accurate and stable output voltage. The peak current of the NMOS switch is also sensed to limit the maximum current flowing through the switch and the inductor. The nominal peak current limit is set to 1500 mA. An internal temperature sensor prevents the device from getting overheated in case of excessive power dissipation. DEVICE ENABLE The device is put into operation when EN is set high. It is put into a shutdown mode when EN is set to GND. It also can be enabled with a low signal on ENPB. This forces the converter to start up as long as the low signal is applied. During this time EN must be set high to prevent the converter from going down into shutdown mode again. If EN is high, a negative signal on ENPB is ignored. In shutdown mode, the regulator stops switching, all internal control circuitry including the low-battery comparator is switched off, and the load is isolated from the input (as described in the synchronous rectifier section). This also means that the output voltage can drop below the input voltage during shutdown. During start-up of the converter, the duty cycle and the peak current are limited in order to avoid high peak currents drawn from the battery. An undervoltage lockout function prevents device start-up if the supply voltage on VBAT is lower than approximately 0.7 V. When in operation and the battery is being discharged, the device automatically enters the shutdown mode if the voltage on VBAT drops below approximately 0.7 V. This undervoltage lockout function is implemented in order to prevent the malfunctioning of the converter. LDO ENABLE When the voltage is applied at VBAT, the LDO can be separately enabled and disabled by using the LDOEN pin in the same way as the EN pin at the dc/dc converter stage described above. POWER GOOD The PGOOD pin stays high impedance when the dc/dc converter delivers an output voltage within a defined voltage window. So it can be used to enable the converter after pushbutton start-up, or to enable any connected circuitry such as cascaded converters (LDO) or processor circuits. 5 TPS61100, TPS61103 TPS61106, TPS61107 www.ti.com SLVS411B – JUNE 2002 – REVISED APRIL 2004 DETAILED DESCRIPTION (continued) POWER SAVE MODE The SKIPEN pin can be used to select different operation modes. To enable power save, SKIPEN must be set high. Power save mode is used to improve efficiency at light load. In power save mode the converter only operates when the output voltage trips below a set threshold voltage. It ramps up the output voltage with one or several pulses and goes again into power save mode once the output voltage exceeds the set threshold voltage. This power save mode can be disabled by setting the SKIPEN to GND. AUTO DISCHARGE The auto discharge function is needed in applications where the supply voltage of a microcontroller, microprocessor or memory has to be removed during shutdown in order to make sure that the system quickly goes in a defined state. The auto discharge function is enabled when the ADEN is set high. It is disabled when the ADEN is set to GND. When the auto discharge function is enabled, the output capacitor is discharged after the device is programmed in the shutdown mode. The output capacitor is discharged by an integrated switch of 400 Ω, hence the discharge time depends on the size of the output capacitor. LOW BATTERY DETECTOR CIRCUIT—LBI/LBO The low-battery detector circuit is typically used to supervise the battery voltage and to generate an error flag when the battery voltage drops below a user-set threshold voltage. The function is active only when the device is enabled. When the device is disabled, both LBO-pin are high-impedance. There are three programmed thresholds, 400 mV, 450 mV, and 500 mV. The outputs on LBO1 and LBO2 are shown as follows: LBI INPUT (mV) LBO1 LBO2 0-400 0 0 400-450 1 0 450-500 0 1 500-VBAT 1 1 1 means that the output stays at high-impedance and 0 means that the output goes active low. If there is only one LBO output needed, both outputs can be tied together. Then the switching threshold is at 500 mV at LBI. The battery voltage, at which the detection circuit switches, can be programmed with a resistive divider connected to the LBI-pin. The resistive divider scales down the battery voltage to a voltage level of 400 mV (450 mV, 500 mV), which is then compared to the LBI threshold voltage. The LBI-pin has a built-in hysteresis of 10 mV. See the application section for more details about the programming of the LBI-threshold. If the low-battery detection circuit is not used, the LBI-pin should be connected to GND (or to VBAT) and the LBO-pin can be left unconnected. Do not let the LBI-pin float. LOW-EMI SWITCH The device integrates a circuit that removes the ringing that typically appears on the SW-node when the converter enters discontinuous current mode. In this case, the current through the inductor ramps to zero and the rectifying PMOS switch is turned off to prevent a reverse current flowing from the output capacitors back to the battery. Due to the remaining energy that is stored in parasitic components of the semiconductor and the inductor, a ringing on the SW-pin is induced. The integrated antiringing switch clamps this voltage to VBAT and therefore dampens ringing. LDO The built-in LDO can be used to generate a second output voltage derived from the dc/dc converter output, from the battery, or from another power source like an ac adapter or a USB power rail. The LDOSENSE input must be connected to LDOOUT at fixed output voltage versions. 6 www.ti.com TPS61100, TPS61103 TPS61106, TPS61107 SLVS411B – JUNE 2002 – REVISED APRIL 2004 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) UNIT Input voltage range on VBAT, LBI, SKIPEN, EN, ENPB, ADEN, FB, LDOEN -0.3 V to 3.6 V Input voltage range on SWN, VOUT, LDOIN, LDOOUT, LDOSENSE, PGOOD, LBO1, LBO2 -0.3 V to 7 V Operating free air temperature range, TA -40°C to 85°C Maximum junction temperature, TJ Storage temperature range, Tstg 150°C -65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10s (1) 260°C Stresses beyond those listed under,, absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under,, recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS MIN NOM VI Supply voltage at VBAT 0.8 L Boost—inductor 4.7 Ci Boost—input capacitor Co Boost—output capacitor Ci LDO—input capacitor Co LDO—output capacitor TJ Operating virtual junction temperature 22 1 -40 MAX 3.3 UNIT V 10 µH 10 µF 100 µF 1 µF 2.2 µF 125 °C 7 TPS61100, TPS61103 TPS61106, TPS61107 www.ti.com SLVS411B – JUNE 2002 – REVISED APRIL 2004 ELECTRICAL CHARACTERISTICS over recommended free-air temperature range and over recommended input voltage range (typical at an ambient temperature range of 25°C) (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT BOOST STAGE VI(b) Vo(b) RL > = 66 Ω at Vo = 3.3 V Input voltage for start-up Input voltage once started Output voltage 1.5 PW package, VBAT ≥ 1.5 V Minimum possible output power Vref Reference voltage f Oscillator frequency 0.85 0.8 Switch current limit Vo = 3.3 V V 3.3 V 5.5 600 500 515 mV 320 500 800 kHz 1200 1500 1800 mA 610 Boost switch on resistance Vo = 3.3 V Sync switch on resistance Vo = 3.3 V Total accuracy V mW 485 Startup current limit mA 180 300 mΩ 180 300 mΩ -3% Auto discharge switch resistance Boost quiescent current 1.1 3% Ω 400 VBAT IO = 0 mA, VEN = VBAT = 3.3 V, Vo = 3.3 V, ENLDO = 0 25 40 µA VOUT IO = 0 mA, VEN = VBAT = 3.3 V, Vo = 3.3 V, ENLDO = 0 12 20 µA VEN = 0 V 0.5 5 µA Boost shutdown current LDO STAGE VI(LDO) Input voltage range 1.5 7 V Vo(LDO) Output voltage 0.9 3.6 V Io(LDO) Output current VI ≥ 1.8 V 120 VI < 1.8 V 80 270 LDO short circuit current limit 500 mA 300 mV Minimum voltage drop VI ≥ 1.8 V, Io(LDO) = 120 mA Total accuracy Io ≥ 1 mA ±3% Line regulation LDOIN change form 1.8 V to 2.6 V at 100 mA 0.6% Load regulation Load change from 10% to 90% 0.6% Auto discharge switch resistance LDO quiescent current LDO shutdown current 8 mA Ω 400 LDOIN VBAT LDOIN = 7 V, VBAT = 1.2 V, EN = 0 27 40 27 40 0.01 1 µA µA TPS61100, TPS61103 TPS61106, TPS61107 www.ti.com SLVS411B – JUNE 2002 – REVISED APRIL 2004 ELECTRICAL CHARACTERISTICS (CONTINUED) over recommended free-air temperature range and over recommended input voltage range (typical at an ambient temperature range of 25°C) (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CONTROL STAGE VIL LBI1 voltage threshold VLBI voltage decreasing 390 400 410 mV LBI2 voltage threshold VLBI voltage decreasing 440 450 460 mV LBI3 voltage threshold VLBI voltage decreasing 490 500 510 mV LBI input hysteresis 10 mV LBI input current EN = Vbat or GND 0.01 0.1 LBO1 output low voltage Vo = 3.3 V, IOL = 10 µA 0.04 0.4 LBO1 output low current 10 µA V µA LBO1 output leakage current VLBO = 3.3 V 0.01 0.1 µA LBO2 output low voltage Vo = 3.3 V, IOL = 10 µA 0.04 0.4 V VLBO = 3.3 V 0.01 0.1 µA LBO2 output low current 10 LBO2 output leakage current VIL EN, ENPB, LDOEN, SKIPEN and ADEN input low voltage VIH EN, ENPB, LDOEN, SKIPEN and ADEN input high voltage µA 0.2 × VBAT 0.8 × VBAT EN, ENPB, LDOEN, SKIPEN and ADEN input current Clamped on GND or VBAT Powergood threshold Vo = 3.3 V 0.9xVo 0.01 0.1 0.92xVo 0.95xVo Powergood delay 30 Powergood output low voltage Vo = 3.3 V, IOL = 10 µA µs 0.04 Powergood output low current µA 0.4 10 V µA Powergood output leakage current 0.01 0.1 µA Overtemperature protection 140 °C Overtemperature hysteresis 20 °C PARAMETER MEASUREMENT INFORMATION U1 L1 10 µH SWN VBAT Power Supply C3 10 µF List of Components: U1 = TPS6110x L1 = SUMIDA CDRH74–100 C3, C5, C6 = X7R/X5R Ceramic C4 = Low ESR Tantalum R3 C6 2.2 µF FB LBI R2 LDOIN SKIPEN LDOOUT ADEN LDOSENSE EN ENPB LDOEN GND VCC1 Boost Output VOUT R1 LBO1 LBO2 PGOOD PGND C4 100 µF R6 VCC2 LDO Output R5 C5 R4 R7 R8 R9 Control Outputs TPS6110x 9 TPS61100, TPS61103 TPS61106, TPS61107 www.ti.com SLVS411B – JUNE 2002 – REVISED APRIL 2004 TYPICAL CHARACTERISTICS Table of Graphs BOOST CONVERTER Maximum output current Efficiency Figure vs Input voltage for VOUT = 3.3 V, 5.0 V 1 vs Input voltage for VOUT = 1.8 V, 2.5 V 2 vs Output current for VIN = 1.2 V, VOUT = 1.5 V 3 vs Output current for VIN = 1.2 V, VOUT = 2.5 V 4 vs Output current for VIN = 1.2 V, VOUT = 3.3 V 5 vs Output current for VIN = 1.8 V, VOUT = 2.5 V 6 vs Output current for VIN = 2.4 V, VOUT = 3.3 V 7 vs Output current for VIN = 2.4 V, VOUT = 5.0 V 8 vs Input voltage for Iout = 10 mA/100 mA/200 mA, VOUT = 3.3 V 9 Output voltage vs Output current TPS61103/6 10 Minimum start-up supply voltage vs Load resistance 11 No-load supply current into VBAT vs Input voltage 12 No-load supply current into VOUT vs Input voltage 13 Output voltage (ripple) in continuous modeInductor current 14 Output voltage (ripple) in power save modeInductor current 15 Load transient response for output current step of 40 mA to 120 mA 16 Line transient response for supply voltage step from 1 V to 1.5 V at Iout = 100 mA 17 Boost converter start-up after enable 18 vs Input voltage for VOUT = 2.5 V, 3.3 V 19 Waveforms LDO Maximum output current vs Input voltage for VOUT = 1.5 V, 1.8 V 20 Output voltage vs Output current TPS61106 21 Dropout voltage vs Output current TPS61100 at 3.3 V TPS61106 22 No-load supply current into LDOIN vs Input voltage 23 PSRR vs Frequency 24 Load transient response for output current step of 20 mA to 100 mA 25 Line transient response for supply voltage step from 1.8 V to 2.4 V at Iout = 100 mA 26 LDO start-up after enable 27 Waveforms 10 TPS61100, TPS61103 TPS61106, TPS61107 www.ti.com SLVS411B – JUNE 2002 – REVISED APRIL 2004 MAXIMUM OUTPUT CURRENT vs INPUT VOLTAGE MAXIMUM OUTPUT CURRENT vs INPUT VOLTAGE 1.2 1.4 TPS61100 1.2 1 Maximum Output Current - A Maximum Output Current - A TPS61100 0.8 VO = 3.3 V 0.6 VO = 5 V 0.4 0.2 0.8 VO = 1.8 V 0.6 VO = 2.5 V 0.4 0.2 0 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 VI - Input Voltage - V 1 1.2 1.4 1.6 1.8 2 VI - Input Voltage - V Figure 1. Figure 2. EFFICIENCY vs OUTPUT CURRENT EFFICIENCY vs OUTPUT CURRENT 100 100 90 90 80 80 70 70 Efficiency - % Efficiency - % 0 0.8 1 60 50 40 30 2.2 2.4 60 50 40 30 20 20 TPS61100 VO = 1.5 V, VBAT = 1.2 V 10 0 0.1 1 10 100 IO - Output Current - mA Figure 3. TPS61100 VO = 2.5 V, VBAT = 1.2 V 10 1000 0 0.1 1 10 100 IO - Output Current - mA 1000 Figure 4. 11 TPS61100, TPS61103 TPS61106, TPS61107 www.ti.com SLVS411B – JUNE 2002 – REVISED APRIL 2004 TYPICAL CHARACTERISTICS (continued) EFFICIENCY vs OUTPUT CURRENT 100 100 90 90 80 80 70 70 Efficiency - % Efficiency - % EFFICIENCY vs OUTPUT CURRENT 60 50 40 30 40 20 TPS61106 VBAT = 1.2 V 10 0 0.1 1 10 100 IO - Output Current - mA TPS61100 VO = 2.5 V, VBAT = 1.8 V 10 0 1000 0.1 1 10 100 IO - Output Current - mA Figure 5. Figure 6. EFFICIENCY vs OUTPUT CURRENT EFFICIENCY vs OUTPUT CURRENT 100 100 90 90 80 80 70 70 Efficiency - % Efficiency - % 50 30 20 60 50 40 1000 60 50 40 30 30 20 20 TPS61106 VBAT = 2.4 V 10 TPS61100 VO = 5 V, VBAT = 2.4 V 10 0 0 0.1 1 10 100 IO - Output Current - mA Figure 7. 12 60 1000 0.1 1 10 IO - Output Current - mA Figure 8. 100 TPS61100, TPS61103 TPS61106, TPS61107 www.ti.com SLVS411B – JUNE 2002 – REVISED APRIL 2004 TYPICAL CHARACTERISTICS (continued) EFFICIENCY vs INPUT VOLTAGE OUTPUT VOLTAGE vs OUTPUT CURRENT 100 3.34 90 3.32 TPS61103/6 80 3.3 IO = 10 mA VO - Output Voltage - V 70 Efficiency - % VBAT = 1.2 V IO = 100 mA IO = 250 mA 60 50 40 30 3.28 3.26 3.24 3.22 20 10 3.2 TPS61106 0 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3.18 0.1 3 3.2 Figure 9. Figure 10. MINIMUM START-UP SUPPLY VOLTAGE vs LOAD RESISTANCE NO-LOAD SUPPLY CURRENT INTO VBAT vs INPUT VOLTAGE 1000 30 1 85°C µA TPS61106 0.95 25 No-Load Supply Current Into VBAT - Minimum Startup Supply Voltage - V 100 10 IO - Output Current - mA VI - Input Voltage - V 0.9 0.85 0.8 0.75 0.7 10 1 100 Load Resistance - Ω Figure 11. 1k 25°C -40°C 20 15 10 5 0 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VI - Input Voltage - V Figure 12. 13 TPS61100, TPS61103 TPS61106, TPS61107 www.ti.com SLVS411B – JUNE 2002 – REVISED APRIL 2004 TYPICAL CHARACTERISTICS (continued) NO-LOAD SUPPLY CURRENT INTO VOUT vs INPUT VOLTAGE OUTPUT VOLTAGE IN CONTINUOUS MODE N0-Load Supply Current Into - VOUT - µA 16 TPS61106 Output Voltage 20 mV/Div, AC 85°C 14 12 25°C -40°C 10 Inductor Current 200 mA/Div, DC 8 6 4 2 0 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 Timebase - 1 µs/Div VI - Input Voltage - V Figure 13. Figure 14. OUTPUT VOLTAGE IN POWER SAVE MODE LOAD TRANSIENT RESPONSE Output Voltage 50 mV/Div, AC Inductor Current 200 mA/Div, DC Timebase - 500 µs/Div Figure 15. 14 Output Current 50 mA/Div, DC Output Voltage 20 mV/Div, AC Timebase - 500 µs/Div Figure 16. TPS61100, TPS61103 TPS61106, TPS61107 www.ti.com SLVS411B – JUNE 2002 – REVISED APRIL 2004 TYPICAL CHARACTERISTICS (continued) LINE TRANSIENT RESPONSE BOOST-CONVERTER START-UP AFTER ENABLE Input Voltage 500 mV/Div, DC Enable 2 V/Div, DC Output Voltage 2 V/Div, DC Voltage at SW 2 V/Div, DC Output Voltage 50 mV/Div, AC Input Current 500 mA/Div, DC Timebase - 400 µs/Div Timebase - 2 ms/Div Figure 17. Figure 18. MAXIMUM LDO OUTPUT CURRENT vs LDO INPUT VOLTAGE MAXIMUM LDO OUTPUT CURRENT vs LDO INPUT VOLTAGE 0.35 Maximum LDO Output Current - A Maximum LDO Output Current - A 0.35 VO = 2.5 V 0.3 0.25 VO = 3.3 V 0.2 0.15 0.1 0.3 VO = 1.5 V 0.25 VO = 1.8 V 0.2 0.15 0.1 2.5 3 3.5 4 4.5 5 5.5 LDO Input Voltage - V Figure 19. 6 6.5 7 1.5 2 2.5 4.5 3 3.5 4 LDO Input Voltage - V 5 5.5 6 Figure 20. 15 TPS61100, TPS61103 TPS61106, TPS61107 www.ti.com SLVS411B – JUNE 2002 – REVISED APRIL 2004 TYPICAL CHARACTERISTICS (continued) LDO OUTPUT VOLTAGE vs LDO OUTPUT CURRENT LDO DROPOUT VOLTAGE vs LDO OUTPUT CURRENT 1.51 3.5 TPS61106 LDOIN = 1.8 V 3 LDO Dropout Voltage - V LDO Output Voltage - V 1.5 1.49 1.48 1.47 1.46 2.5 2 TPS61106 (LDO OUTPUT VOLTAGE 1.5 V) 1.5 1 TPS61100 (LDO OUTPUT VOLTAGE 3.3 V) 0.5 1.45 0 50 100 150 0 200 0 LDO Output Current - mA Figure 22. SUPPLY CURRENT INTO LDOIN vs LDOIN INPUT VOLTAGE PSRR vs FREQUENCY 500 80 85°C LDO Output Current 10 mA 70 30 25°C 60 25 -40°C 20 15 PSRR - dB Supply Current Into LDOIN - µ A 200 300 400 LDO Output Current - mA Figure 21. 35 50 40 LDO Output Current 100 mA 30 10 20 5 0 16 100 TPS61106 LDOIN = 3.3 V 10 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 0 1k LDOIN Input Voltage - V 100k f - Frequency - Hz Figure 23. Figure 24. 10k 1M 10M TPS61100, TPS61103 TPS61106, TPS61107 www.ti.com SLVS411B – JUNE 2002 – REVISED APRIL 2004 TYPICAL CHARACTERISTICS (continued) LDO LOAD TRANSIENT RESPONSE LDO LINE TRANSIENT RESPONSE Output Current 50 mA/Div, DC Input Voltage 1 V/Div, DC Output Voltage 10 mV/Div, AC Output Voltage 20 mV/Div, AC Timebase - 2 ms/Div Timebase - 1 ms/Div Figure 25. Figure 26. LDO START-UP AFTER ENABLE LDO-Enable 2 V/Div, DC LDO-Output Voltage 1 V/Div, DC Input Current 50 mA/Div, DC Timebase - 50 µs/Div Figure 27. 17 TPS61100, TPS61103 TPS61106, TPS61107 www.ti.com SLVS411B – JUNE 2002 – REVISED APRIL 2004 APPLICATION INFORMATION DESIGN PROCEDURE The TPS6110x boost converters are intended for systems powered by a single-cell NiCd or NiMH battery with a typical terminal voltage between 0.9 V and 1.6 V. They can also be used in systems powered by two-cell NiCd or NiMH batteries with a typical stack voltage between 1.8 V and 3.2 V. Additionally, single- or dual-cell, primary and secondary alkaline battery cells can be the power source in systems where the TPS6110x is used. Programming the Output Voltage Boost Converter The output voltage of the TPS61100 boost converter section can be adjusted with an external resistor divider. The typical value of the voltage on the FB pin is 500 mV. The maximum allowed value for the output voltage is 5.5 V. The current through the resistive divider should be about 100 times greater than the current into the FB pin. The typical current into the FB pin is 0.01 µA and the voltage across R6 is typically 500 mV. Based on those two values, the recommended value for R6 should be lower than 500 kΩ, in order to set the divider current at 1 µA or higher. Because of internal compensation circuitry the value for this resistor should be in the range of 200 kΩ. From that, the value of resistor R3, depending on the needed output voltage (VO), can be calculated using Equation 1: V V O –1  180 k

O –1 R3  R6
V 500 mV FB (1)     If as an example, an output voltage of 3.3 V is needed, a 1-MΩ resistor should be chosen for R3. U1 L1 10 µH SWN VBAT Power Supply C3 10 µF R3 C6 2.2 µF FB LBI LDOIN R6 SKIPEN LDOOUT ADEN LDOSENSE EN R5 ENPB R4 R2 LDOEN GND VCC1 Boost Output VOUT R1 LBO1 LBO2 PGOOD PGND C4 100 µF VCC2 LDO Output C5 R7 R8 R9 Control Outputs TPS61100 Figure 28. Typical Application Circuit for Adjustable Output Voltage Option LDO Programming the output voltage at the LDO follows almost the same rules as at the boost converter section. The maximum programmable output voltage at the LDO is 3.3 V. Since reference and internal feedback circuitry are similar, as they are at the boost converter section, R4 also should be in the 200-kΩ range. The calculation of the value of R5 can be done using the following Equation 2: V V O –1  180 k

O –1 R5  R4
V 500 mV FB (2)     If as an example, an output voltage of 1.5 V is needed, a 360 kΩ-resistor should be chosen for R5. 18 TPS61100, TPS61103 TPS61106, TPS61107 www.ti.com SLVS411B – JUNE 2002 – REVISED APRIL 2004 APPLICATION INFORMATION (continued) Programming the LBI/LBO Threshold Voltage The current through the resistive divider should be about 100 times greater than the current into the LBI pin. The typical current into the LBI pin is 0.01 µA, and the voltage across R2 is equal to the LBI voltage threshold that is generated on-chip, which has a value of 400 mV, 450 mV or 500 mV. The recommended value for R2is therefore in the range of 500 kΩ. From that, the value of resistor R1, depending on the desired minimum battery voltage VBAT, can be calculated using Equation 3. R1  R2
 V V BAT  –1 LBI-threshold  390 k

  V BAT –1 450 mV (3) For example, if the low-battery detection circuit should flag an error condition for the 450 mV threshold on the LBO outputs at a battery voltage of 1.23 V, a 680-kΩ resistor should be chosen for R1. The resulting battery voltages of the other thresholds can be calculated using Equation 4: V V
R1  1  500 mV
680 k
 1 BAT LBI-threshold R2 390 k
(4)     The result for the 500-mV threshold in our example is 1.37 V and for the 400-mV threshold 1.1 V. This results in the following truth table for the battery supervisor outputs: VBAT [V] LBO1 LBO2 0-1.1 0 0 1.1-1.23 1 0 1.23-1.37 0 1 1.37-VBAT max 1 1 If the application requires only a simple LBI/LBO function both LBO outputs can be connected together. The LBI threshold then is 500 mV. The outputs of the low battery supervisor are simple open-drain outputs that go active low if the dedicated battery voltage drops below the programmed threshold voltage on LBI. The output requires a pullup resistor with a recommended value of 1 MΩ. The maximum voltage which is used to pull up the LBO outputs should not exceed the output voltage of the boost converter. If not used, the LBO pin can be left floating or tied to GND. Inductor Selection A boost converter normally requires two main passive components for storing energy during the conversion. A boost inductor and a storage capacitor at the output are required. To select the boost inductor, it is recommended to keep the possible peak inductor current below the current limit threshold of the power switch in the chosen configuration. For example, the current limit threshold of the TPS6110x's switch is 1200 mA at an output voltage of 3.3 V. The highest peak current through the inductor and the switch depends on the output load, the input (VBAT), and the output voltage (VOUT). Estimation of the maximum average inductor current can be done using Equation 5: V OUT I I
L OUT V
0.8 BAT (5) For example, for an output current of 100 mA at 3.3 V, at least 515 mA of current flows through the inductor at a minimum input voltage of 0.8 V. 19 TPS61100, TPS61103 TPS61106, TPS61107 www.ti.com SLVS411B – JUNE 2002 – REVISED APRIL 2004 The second parameter for choosing the inductor is the desired current ripple in the inductor. Normally, it is advisable to work with a ripple of less than 20% of the average inductor current. A smaller ripple reduces the magnetic hysteresis losses in the inductor, as well as output voltage ripple and EMI. But in the same way, regulation time at load changes rises. In addition, a larger inductor increases the total system costs. With those parameters, it is possible to calculate the value for the inductor by using Equation 6: V L 
V –V BAT OUT BAT
I
ƒ
V L OUT  (6) Parameter 0 is the switching frequency and∆ IL is the ripple current in the inductor, i.e., 20% × IL. In this example, the desired inductor has the value of 12 µH. With this calculated value and the calculated currents, it is possible to choose a suitable inductor. Care has to be taken that load transients and losses in the circuit can lead to higher currents as estimated in Equation 5. Also, the losses in the inductor caused by magnetic hysteresis losses and copper losses are a major parameter for total circuit efficiency. Table 1. Inductors VENDOR RECOMMENDED INDUCTOR SERIES CDRH73 CDRH74 Sumida CDRH5D18 CDRH6D38 DR73 Coiltronics DR74 LQS66C Murata LQN6C SLF 7045 TDK SLF 7032 Wurth Electronic WE-PD Type M WE-PD Type S CAPACITOR SELECTION Input Capacitor At least a 10-µF input capacitor is recommended to improve transient behavior of the regulator and EMI behavior of the total power supply circuit. A ceramic capacitor or a tantalum capacitor with a 100-nF ceramic capacitor in parallel, placed close to the IC, is recommended. Output Capacitor Boost Converter The major parameter necessary to define the output capacitor is the maximum allowed output voltage ripple of the converter. This ripple is determined by two parameters of the capacitor, the capacitance and the ESR. It is possible to calculate the minimum capacitance needed for the defined ripple, supposing that the ESR is zero, by using Equation 7: I C min  
V V OUT OUT BAT ƒ

V
V OUT  Parameter f is the switching frequency and ∆V is the maximum allowed ripple. 20 (7) TPS61100, TPS61103 TPS61106, TPS61107 www.ti.com SLVS411B – JUNE 2002 – REVISED APRIL 2004 With a chosen ripple voltage of 15 mV, a minimum capacitance of 10 µF is needed. The total ripple is larger due to the ESR of the output capacitor. This additional component of the ripple can be calculated using Equation 8:
V I
R ESR OUT ESR (8) An additional ripple of 10 mV is the result of using a tantalum capacitor with a low ESR of 100 mΩ. The total ripple is the sum of the ripple caused by the capacitance and the ripple caused by the ESR of the capacitor. In this example, the total ripple is 25 mV. It is possible to improve the design by enlarging the capacitor or using smaller capacitors in parallel to reduce the ESR or by using better capacitors with lower ESR, like ceramics. So, trade-offs have to be made between performance and costs of the converter circuit. Output Capacitor LDO To ensure stable output regulation, it is required to use an output capacitor at the LDO output. We recommend using ceramic capacitors in the range from 1 µF up to 4.7 µF. At 4.7 µF and above it is recommended to use standard ESR tantalum. There is no maximum capacitance value. LAYOUT CONSIDERATIONS As for all switching power supplies, the layout is an important step in the design, especially at high peak currents and high switching frequencies. If the layout is not carefully done, the regulator could show stability problems as well as EMI problems. Therefore, use wide and short traces for the main current path and for the power ground tracks. The input capacitor, output capacitor, and the inductor should be placed as close as possible to the IC. Use a common ground node for power ground and a different one for control ground to minimize the effects of ground noise. Connect these ground nodes at any place close to one of the ground pins of the IC. The feedback divider should be placed as close as possible to the control ground pin of the IC. To lay out the control ground, it is recommended to use short traces as well, separated from the power ground traces. This avoids ground shift problems, which can occur due to superimposition of power ground current and control ground current. APPLICATION EXAMPLES U1 L1 10 µH SWN VBAT VOUT C6 2.2 µF R1 C3 10 µF LBI R2 List of Components: U1 = TPS61106 L1 = SUMIDA CDRH74–100 C3, C5, C6 = X7R/X5R Ceramic C4 = Low ESR Tantalum LDOIN SKIPEN LDOOUT ADEN LDOSENSE EN ENPB LDOEN GND C4 100 µF C5 2.2 µF R7 R8 LBO1 LBO2 PGOOD PGND 3.3 V, >250 mA 1.5 V, >120 mA R9 LBO1 LBO2 PGOOD TPS61106 Figure 29. Solution for Maximum Output Power 21 TPS61100, TPS61103 TPS61106, TPS61107 www.ti.com SLVS411B – JUNE 2002 – REVISED APRIL 2004 U1 L1 SWN 10 µH VBAT 3.3 V VOUT C6 2.2 µF R1 C3 10 µF LBI R2 LDOIN SKIPEN LDOOUT ADEN LDOSENSE EN ENPB List of Components: U1 = TPS61106 L1 = SUMIDA 5D18–100 C3, C5, C6 = X7R/X5R Ceramic C4 = Low ESR, Low Profile Tantalum LDOEN C4 100 µF 1.5 V C5 2.2 µF R7 R8 R9 LBO1 LBO2 LBO1 LBO2 PGOOD PGOOD PGND GND TPS61106 Figure 30. Low Profile Solution, Maximum Height 1,8 mm 6V C7 U1 0.1 µF L1 10 µH VOUT 3.3 V C6 2.2 µF R1 LBI R2 List of Components: U1 = TPS61106 L1 = SUMIDA CDRH74–100 C3, C5, C6, C7, C8 = X7R/X5R Ceramic C4 = Low ESR Tantalum DS1 = BAT54S C8 1 µF SWN VBAT C3 10 µF DS1 LDOIN SKIPEN LDOOUT ADEN LDOSENSE EN ENPB LDOEN GND C4 100 µF 1.5 V C5 2.2 µF R7 R8 R9 LBO1 LBO2 PGOOD PGND TPS61106 Figure 31. Dual Power Supply With Auxiliary Positive Output Voltage 22 LBO1 LBO2 PGOOD TPS61100, TPS61103 TPS61106, TPS61107 www.ti.com SLVS411B – JUNE 2002 – REVISED APRIL 2004 –3 V C7 U1 C8 1 µF 0.1 µF L1 10 µH DS1 SWN VBAT VOUT 3.3 V C6 2.2 µF R1 C3 10 µF LBI R2 C4 100 µF LDOIN 1.5 V SKIPEN LDOOUT ADEN LDOSENSE EN List of Components: U1 = TPS61106 L1 = SUMIDA CDRH74–100 C3, C5, C6, C7, C8 = X7R/X5R Ceramic C4 = Low ESR Tantalum DS1 = BAT54S C5 2.2 µF R7 ENPB LDOEN GND R8 R9 LBO1 LBO2 PGOOD PGND LBO1 LBO2 PGOOD TPS61106 Figure 32. Dual Power Supply With Auxiliary Negative Output Voltage U1 L1 10 µH SWN VBAT C3 10 µF VOUT R3 R1 C6 22 µF FB LBI R6 R2 LDOIN LDOOUT SKIPEN ADEN LDOSENSE EN ENPB List of Components: U1 = TPS61100 L1 = SUMIDA CDRH74–100 C3, C5 = X7R/X5R Ceramic C6 = X7R/X5R Ceramic or Low ESR Tantalum LDOEN GND 3.3 V R5 C5 2.2 µF R4 LBO1 LBO2 PGOOD PGND R7 R8 R9 LBO1 LBO2 PGOOD TPS61100 Figure 33. Single Output Using LDO as Filter 23 TPS61100, TPS61103 TPS61106, TPS61107 www.ti.com SLVS411B – JUNE 2002 – REVISED APRIL 2004 U1 L1 SWN 10 µH VBAT 3.3 V VOUT C6 2.2 µF R1 C3 10 µF LBI R2 C4 100 µF LDOIN 1.5 V LDOOUT C5 2.2 µF SKIPEN LDOSENSE ADEN EN ENPB LBO1 LDOEN LBO2 PGOOD GND PGND R10 List of Components: U1 = TPS61106 L1 = SUMIDA 5D18–100 C3, C5, C6 = X7R/X5R Ceramic C4 = Low ESR Tantalum R7 R8 R9 LBO1 LBO2 TPS61106 Figure 34. Simple Solution Using a Pushbutton for Start-Up D1 USB-Input 4.2 V – 5.5 V List of Components: U1 = TPS61100 L1 = SUMIDA CDRH73–100 C3, C6 = X7R/X5R Ceramic C4 = Low ESR Tantalum D1 = ON-Semiconductor MBR0520 D2 R12 180 kΩ U1 L1 10 µH SWN VBAT VOUT R1 C3 10 µF R3 1 MΩ LBI LDOIN R2 R10 680 kΩ SYNC ADEN EN GND R6 180 kΩ R5 1.022 MΩ LDOSENSE ENPB R11 1 MΩ C4 100 µF LDOOUT LDOEN LBO1 LBO2 PGOOD PGND R4 180 kΩ TPS61100 Figure 35. Dual Input Power Supply 24 C6 2.2 µF FB VCC 3.3 V System Supply R7 R8 R9 Control Outputs TPS61100, TPS61103 TPS61106, TPS61107 www.ti.com SLVS411B – JUNE 2002 – REVISED APRIL 2004 U1 L1 10 µH SWN VBAT INPUT C3 10 µF VOUT OUTPUT R3 R1 LBI FB C6 2.2 µF C4 100 µF R11 R6 R2 R10 LDOIN LDOOUT LDOOUT SKIPEN SKIPEN ADEN LDOSENSE EN ADEN C5 2.2 µF R5 R4 ENPB R7 R8 R9 LDOEN EN GND ENPB LBO1 LBO2 PGOOD PGND LBO1 LBO2 PGOOD TPS6110XRGE LDOEN Figure 36. TPS6110x EVM Circuit Diagram THERMAL INFORMATION Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat-generating components affect the power-dissipation limits of a given component. Three basic approaches for enhancing thermal performance are listed below. • Improving the power dissipation capability of the PCB design. • Improving the thermal coupling of the component to the PCB. • Introducing airflow in the system. The maximum junction temperature (TJ) of the TPS6110x devices is 150°C. The thermal resistance of the 20-pin TSSOP package (PW) isRΘJA = 155 K/W (QFN package, RGE, 161 K/W). Specified regulator operation is assured to a maximum ambient temperature TA of 85°C. Therefore, the maximum power dissipation is about 420 mW. More power can be dissipated if the maximum ambient temperature of the application is lower. T
T J(MAX) A P   150°C
85°C  420 mW D(MAX) R 155 kW
JA (9) 25 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPS61100PW ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TPS61100 TPS61100PWR ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TPS61100 TPS61100RGER ACTIVE VQFN RGE 24 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS 61100 TPS61107PW ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TPS61107 TPS61107RGER ACTIVE VQFN RGE 24 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS 61107 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of