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TPS62067DSGT

TPS62067DSGT

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    WSON8_EP

  • 描述:

    TPS62067 3MHZ, 2A STEP-DOWN CONV

  • 数据手册
  • 价格&库存
TPS62067DSGT 数据手册
TPS62065, TPS62067 TPS62067 SLVS833E – MARCH 2010 –TPS62065, REVISED OCTOBER 2020 SLVS833E – MARCH 2010 – REVISED OCTOBER 2020 www.ti.com TPS6206x 3-MHz, 2-A, Step-Down Converter in 2-mm × 2-mm SON Package 1 Features 3 Description • • • • • • • • • • • • • • The TPS6206x is a family of highly efficient synchronous step down DC/DC converters. They provide up to 2-A output current. 3-MHz Switching Frequency VIN Range from 2.9 V to 6 V Up to 97% Efficiency Power Save Mode / 3-MHz Fixed PWM Mode Power Good Output Output Voltage Accuracy in PWM Mode ±1.5% Output Capacitor Discharge Function Typical 18 µA Quiescent Current 100% Duty Cycle for Lowest Dropout Voltage Positioning Clock Dithering -40°C to 125°C Operating Junction Temperature Supports Maximum 1-mm Height Solutions Available in a 2 mm x 2 mm x 0.75 mm WSON 2 Applications • • • • Point of Load (POL) Notebooks, Pocket PCs Portable Media Players DSP Supply With an input voltage range of 2.9 V to 6 V, the device is a perfect fit for power conversion from a 5-V or 3.3V system supply rail. The TPS6206x operates at 3MHz fixed frequency and enters power save mode operation at light load currents to maintain high efficiency over the entire load current range. The power save mode is optimized for low output voltage ripple. For low noise applications, TPS62065 can be forced into fixed frequency PWM mode by pulling the MODE pin high. TPS62067 provides an open drain power good output. In the shutdown mode, the current consumption is reduced to less than 1 µA and an internal circuit discharges the output capacitor. TPS6206x family is optimized for operation with a tiny 1 µH inductor and a small 10-µF output capacitor to achieve smallest solution size and high regulation performance. It is available in a small 2-mm × 2-mm × 0.75-mm 8pin WSON package. Device Information PACKAGE (1) PART NUMBER TPS62065 TPS62067 (1) L 1.0 mH VIN = 2.9 V to 6 V CIN 10 mF AVIN EN AGND PGND VOUT 1.8 V 2 A 100 FB PG R2 180 kW Cff COUT 22 pF 10 mF RPG 100 kW 90 Copyright © 2016, Texas Instruments Incorporated Typical Application Schematic VIN = 3.7 V 95 SW R1 360 kW 2.00 mm × 2.00 mm For all available packages, see the orderable addendum at the end of the data sheet. VIN = 4.2 V VIN = 5 V 85 Efficiency - % PVIN WSON (8) BODY SIZE (NOM) 80 75 70 65 L = 1.2 mH (NRG4026T 1R2), COUT = 22 mF (0603 size), VOUT = 3.3 V, Mode: Auto PFM/PWM 60 55 50 0 0.25 0.5 0.75 1 1.25 1.5 IL - Load Current - A 1.75 2 Efficiency vs Load Current An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated intellectual property matters and other important disclaimers. PRODUCTION DATA. Product Folder Links: TPS62065 TPS62067 1 TPS62065, TPS62067 www.ti.com SLVS833E – MARCH 2010 – REVISED OCTOBER 2020 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Device Comparison Table...............................................3 6 Pin Configuration and Functions...................................3 7 Specifications.................................................................. 4 7.1 Absolute Maximum Ratings........................................ 4 7.2 ESD Ratings............................................................... 4 7.3 Recommended Operating Conditions.........................4 7.4 Thermal Information....................................................4 7.5 Electrical Characteristics.............................................5 7.6 Typical Characteristics................................................ 6 8 Detailed Description........................................................7 8.1 Overview..................................................................... 7 8.2 Functional Block Diagram........................................... 7 8.3 Feature Description.....................................................8 8.4 Device Functional Modes............................................9 9 Application and Implementation.................................. 12 9.1 Application Information............................................. 12 9.2 Typical Application.................................................... 12 9.3 System Example....................................................... 18 10 Power Supply Recommendations..............................19 11 Layout........................................................................... 19 11.1 Layout Guidelines................................................... 19 11.2 Layout Example...................................................... 19 12 Device and Documentation Support..........................20 12.1 Device Support....................................................... 20 12.2 Related Links.......................................................... 20 12.3 Receiving Notification of Documentation Updates..20 12.4 Support Resources................................................. 20 12.5 Trademarks............................................................. 20 12.6 Electrostatic Discharge Caution..............................20 12.7 Glossary..................................................................20 13 Mechanical, Packaging, and Orderable Information.................................................................... 20 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (November 2016) to Revision E (October 2020) Page • Updated the numbering format for tables, figures and cross-references throughout the document...................1 Changes from Revision C (September 2015) to Revision D (November 2016) Page • Changed the conditions statement for Section 7.5 ............................................................................................ 5 • Added Note 1 to the Test conditions of ISD, IIN, and ILKG in Section 7.5 ............................................................ 5 • Changed temperature values From: TA To: TJ in Figure 7-1 and Figure 7-3 ..................................................... 6 Changes from Revision B (November 2013) to Revision C (September 2015) Page • Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ............................................................................................................................................................... 1 Changes from Revision A (May 2010) to Revision B (November 2013) Page • Added Thermal Information table and deleted Dissipation Ratings table........................................................... 4 Changes from Revision * (March 2010) to Revision A () Page • Changed VIN Range from "3V to 6V" to "2.9V to 6V", throughout...................................................................... 1 • Added equation to "Output Voltage Setting" section.........................................................................................12 • Changed equation for calculating fz. ................................................................................................................ 12 • Changed equation for calculating Cff. .............................................................................................................. 12 2 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS62065 TPS62067 TPS62065, TPS62067 www.ti.com SLVS833E – MARCH 2010 – REVISED OCTOBER 2020 5 Device Comparison Table POWER GOOD (PG) MAXIMUM OUTPUT CURRENT Adjustable Selectable No 2A Adjustable Auto PWM/PFM Yes 2A OUTPUT VOLTAGE(1) TPS62065 TPS62067 (1) (2) FUNCTION MODE PART NUMBER (2) Contact TI for other fixed output voltage options For the most current package and ordering information, see Section 13 at the end of this document, or see the TI website at www.ti.com. PGND 1 SW 2 AGND 3 FB 4 PowerPAD 6 Pin Configuration and Functions 8 PVIN 7 AVIN 6 MODE 5 EN Figure 6-1. DSG Package 8-Pin WSON Top View Table 6-1. Pin Functions PIN NAME NO. I/O DESCRIPTION AGND 3 I Analog GND supply pin for the control circuit. AVIN 7 I Analog VIN power supply for the control circuit. Must be connected to PVIN and input capacitor. EN 5 I This is the enable pin of the device. Pulling this pin to low forces the device into shutdown mode. Pulling this pin to high enables the device. This pin must be terminated FB 4 I Feedback pin for the internal regulation loop. Connect the external resistor divider to this pin. In case of fixed output voltage option, connect this pin directly to the output capacitor I MODE: MODE pin = High forces the device to operate in fixed frequency PWM mode. MODE pin = Low enables the power save mode with automatic transition from PFM mode to fixed frequency PWM mode. This pin must be terminated. MODE 6 Open- PG: Power Good Open-Drain output. Connect an external pullup resistor to a rail which is Drain below or equal AVIN. PG PGND 1 PWR PowerPAD™ — — PVIN 8 PWR SW 2 O GND supply pin for the output stage. For good thermal performance, this PAD must be soldered to the land pattern on the PCB. This PAD should be used as device GND. VIN power supply pin for the output stage. This is the switch pin and is connected to the internal MOSFET switches. Connect the external inductor between this terminal and the output capacitor. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS62065 TPS62067 3 TPS62065, TPS62067 www.ti.com SLVS833E – MARCH 2010 – REVISED OCTOBER 2020 7 Specifications 7.1 Absolute Maximum Ratings Over operating free-air temperature range (unless otherwise noted) (1) Voltage(2) MIN MAX AVIN, PVIN –0.3 7 UNIT EN, MODE, PG, FB –0.3 VIN +0.3 < 7 SW –0.3 7 V Current (sink) into PG Current (source) Peak output Internally limited TJ –40 125 °C Tstg –65 150 °C Temperature (1) (2) 1 mA A Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. 7.2 ESD Ratings VALUE Human body model (HBM), per ANSI/ESDA/JEDEC V(ESD) (1) (2) Electrostatic discharge JS-001(1) UNIT ±2000 Charged-device model (CDM), per JEDEC specification JESD22C101(2) V ±1000 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions MIN AVIN , PVIN Supply voltage NOM 2.9 MAX 6 Output current capability 2000 Output voltage range for adjustable voltage 0.8 UNIT V mA VIN V L Effective inductance 0.7 1 1.6 µH COUT Effective output capacitance 4.5 10 22 µF TJ Operating junction temperature –40 125 °C 7.4 Thermal Information THERMAL METRIC(1) TPS62065 TPS62067 DSG (WSON) UNIT 8 PINS RθJA Junction-to-ambient thermal resistance 65.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 74.2 °C/W RθJB Junction-to-board thermal resistance 35.4 °C/W ψJT Junction-to-top characterization parameter 2.2 °C/W ψJB Junction-to-board characterization parameter 36 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 12.8 °C/W (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS62065 TPS62067 TPS62065, TPS62067 www.ti.com SLVS833E – MARCH 2010 – REVISED OCTOBER 2020 7.5 Electrical Characteristics TJ = -40°C to 125°C, typical values are at TA = 25°C. Unless otherwise noted, specifications apply for condition VIN = EN = 3.6 V. External components CIN = 10 μF 0603, COUT = 10 μF 0603, L = 1 μH, see the parameter measurement information. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VIN Input voltage range 2.9 IQ Operating quiescent current IOUT = 0 mA, device operating in PFM mode and device not switching ISD Shutdown current EN = GND, current into AVIN and PVIN(1) VUVLO Undervoltage lockout threshold 6 18 0.1 1 V μA Falling 1.73 1.78 1.83 Rising 1.9 1.95 1.99 μA V ENABLE, MODE VIH High level input voltage 2.9 V ≤ VIN ≤ 6 V 1 VIL Low level input voltage 2.9 V ≤ VIN ≤ 6 V 0 IIN Input bias current EN, mode tied to GND or AVIN(1) 6 V 0.4 V 0.01 1 μA POWER GOOD OPEN-DRAIN OUTPUT VTHPG Power good threshold voltage Rising feedback voltage 93% 95% 98% Falling feedback voltage 87% 90% 92% VOL Output low voltage IOUT = –1mA; must be limited by external pullup resistor (1) VH Output high voltage Voltage applied to PG pin through external pullup resistor ILKG Leakage current into PG pin V(PG) = 3.6V(1) tPGDL Internal power good delay time 0.3 V VIN V 100 nA 5 µs POWER SWITCH VIN = 3.6 V (1) 120 180 95 150 90 130 75 100 2750 3300 RDS(on) High-side MOSFET on-resistance RDS(on) Low-side MOSFET on-resistance ILIMF Forward current limit MOSFET high-side and low-side 2.9 V ≤ VIN ≤ 6 V Thermal shutdown Increasing junction temperature 150 Thermal shutdown hysteresis Decreasing junction temperature 10 TSD VIN = 5 V(1) VIN = 3.6 V(1) VIN = 5 V(1) 2300 mΩ mΩ mA °C OSCILLATOR fSW Oscillator frequency 2.9 V ≤ VIN ≤ 6 V 2.6 3 3.4 MHz OUTPUT Vref Reference voltage VFB(PWM) Feedback voltage PWM mode VFB(PFM) Feedback voltage PFM mode, voltage positioning 600 PWM operation, MODE = VIN , 2.9 V ≤ VIN ≤ 6 V, 0 mA load device in PFM mode, voltage positioning active(2) Line regulation R(Discharge) Internal discharge resistor Activated with EN = GND, 2.9 V ≤ VIN ≤ 6 V, 0.8 ≤ VOUT ≤ 3.6 V tSTART Start-up time Time from active EN to reach 95% of VOUT 0% 1.5% 1% Load regulation VFB (1) (2) –1.5% mV 75 –0.5 %/A 0 %/V 200 500 1450 Ω μs Maximum value applies for TJ = 85°C In PFM mode, the internal reference voltage is set to typ. 1.01 × Vref. See the parameter measurement information. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS62065 TPS62067 5 TPS62065, TPS62067 www.ti.com SLVS833E – MARCH 2010 – REVISED OCTOBER 2020 7.6 Typical Characteristics 25 TA = 85°C TJ = 85°C 20 0.75 Iq - Quiesent Current - mA ISHDN - Shutdown Current - mA 1 0.50 TJ = 25°C 0.25 3 3.5 4 4.5 5 VI - Input Voltage - V 5.5 TA = -40°C 10 0 2.5 6 Figure 7-1. Shutdown Current vs Input Voltage and Ambient Temperature 3 3.5 4 4.5 5 VI - Input Voltage - V 5.5 6 Figure 7-2. Quiescent Current vs Input Voltage 3.1 0.12 TJ = 85°C 3.05 0.1 TJ = 85°C TJ = 25°C TJ = 25°C 3 0.08 RDSON - W fOSC - Oscillator Frequency - MHz 15 5 TJ = -40°C 0 2.5 TA = 25°C 2.95 TJ = -40°C 0.06 2.9 0.04 2.85 0.02 2.8 2.5 3 3.5 4 4.5 5 VI - Input Voltage - V 5.5 TJ = -40°C 0 2.5 6 Figure 7-3. Oscillator Frequency vs Input Voltage 3 3.5 4 4.5 5 VI - Input Voltage - V 5.5 6 Figure 7-4. RDSON Low-Side Switch 0.2 600 0.18 500 0.16 400 TJ = 25°C 0.12 RDischarge - W RDSON - W VO = 3.3 V TJ = 85°C 0.14 TJ = -40°C 0.1 0.08 VO = 1.8 V 300 200 0.06 VO = 1.2 V 0.04 100 0.02 0 2.5 3 3.5 4 4.5 5 VI - Input Voltage - V 5.5 Figure 7-5. RDSON High-Side Switch 6 6 0 2.5 3 3.5 4 4.5 5 VI - Input Voltage - V 5.5 6 Figure 7-6. Rdischarge vs Input Voltage Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS62065 TPS62067 TPS62065, TPS62067 www.ti.com SLVS833E – MARCH 2010 – REVISED OCTOBER 2020 8 Detailed Description 8.1 Overview The TPS6206x step down converter operates with typically 3-MHz fixed frequency pulse width modulation (PWM) at moderate to heavy load currents. At light load currents the converter can automatically enter power save mode and operates then in pulse frequency modulation (PFM) mode. During PWM operation the converter use a unique fast response voltage mode controller scheme with input voltage feed-forward to achieve good line and load regulation allowing the use of small ceramic input and output capacitors. At the beginning of each clock cycle initiated by the clock signal, the high-side MOSFET switch is turned on. The current flows now from the input capacitor through the high-side MOSFET switch through the inductor to the output capacitor and load. During this phase, the current ramps up until the PWM comparator trips and the control logic will turn off the switch. The current limit comparator will also turn off the switch in case the current limit of the high-side MOSFET switch is exceeded. After a dead time preventing shoot through current, the low-side MOSFET rectifier is turned on and the inductor current ramps down. The current flows now from the inductor to the output capacitor and to the load. It returns back to the inductor through the low-side MOSFET rectifier.. The next cycle will be initiated by the clock signal again turning off the low-side MOSFET rectifier and turning on the high-side MOSFET switch. 8.2 Functional Block Diagram AVIN PVIN Current Limit Comparator Undervoltage Lockout 1.8V Thermal Shutdown Limit High Side PFM Comparator Reference 0.6V VREF FB VREF Softstart VOUT RAMP CONTROL Gate Driver Anti Shoot-Through Control Stage Error Amp. VREF SW Integrator FB Internal FB Network* MODE * MODE/ PG PWM Comp. Zero-Pole AMP. Sawtooth Generator PG Limit Low Side 3MHz Clock Current Limit Comparator FB VREF RDischarge PG Comparator* AGND EN PGND Copyright © 2016, Texas Instruments Incorporated * Function depends on device option Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS62065 TPS62067 7 TPS62065, TPS62067 www.ti.com SLVS833E – MARCH 2010 – REVISED OCTOBER 2020 8.3 Feature Description 8.3.1 Mode Selection (TPS62065) The MODE pin allows mode selection between forced PWM mode and power save mode. Connecting this pin to GND enables the power save mode with automatic transition between PWM and PFM mode. Pulling the MODE pin high forces the converter to operate in fixed frequency PWM mode even at light load currents. This allows simple filtering of the switching frequency for noise sensitive applications. In this mode, the efficiency is lower compared to the power save mode during light loads. The condition of the MODE pin can be changed during operation and allows efficient power management by adjusting the operation mode of the converter to the specific system requirements. In device options where the MODE pin is replaced with power good output, the power save mode is enabled per default. 8.3.2 Power Good Output (TPS62067) This function is available in the TPS62067. The power good output is an open-drain output and requires an external pullup resistor. The circuit is active once the device is enabled and AVIN is above the undervoltage lockout threshold V UVLO. It is driven by an internal comparator connected to the FB voltage. The PG output provides a high level once the feedback voltage exceeds typically 95% of its nominal value. The PG output is driven to low level once the feedback voltage falls below typically 90% of its nominal value. The PG output is activated with an internal delay of 5 µs. The PG open-drain output transistor is turned on immediately with EN = Low level and pulls the output low. The external pullup resistor can be connected to any voltage rail lower or equal the voltage applied to AVIN of the device. The value of the pullup resistor must be carefully selected to limit the current into the PG pin to maximum 1 mA. The external pullup resistor can be connected to VOUT or another voltage rail which does not exceed the V IN level. The current flowing through the pullup resistor impacts the current consumption of the application circuit in shutdown mode. The shutdown current of the device does not include the current through the external pullup and internal opendrain stage. The PG signal can be used for sequencing various converters or to reset a microcontroller. EN VOUT Startup 95% 90% Overload Output discharge tRamp tStart PG WithEN = low PG --> low Figure 8-1. Power Good Output Pg 8.3.3 Enable The device is enabled by setting EN pin to high. At first, the internal reference is activated and the internal analog circuits are settled. Afterwards, the soft start is activated and the output voltage is ramped up. The output voltages reaches 95% of its nominal value within t START of typically 500 µs after the device has been enabled. The EN input can be used to control power sequencing in a system with various DC/DC converters. The EN pin can be connected to the output of another converter, to drive the EN pin high and getting a sequencing of supply rails. With EN = GND, the device enters shutdown mode. In this mode, all circuits are disabled and the SW pin is connected to PGND through an internal resistor to discharge the output. 8 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS62065 TPS62067 www.ti.com TPS62065, TPS62067 SLVS833E – MARCH 2010 – REVISED OCTOBER 2020 8.3.4 Clock Dithering To reduce the noise level of switch frequency harmonics in the higher RF bands, the TPS6206x family has a built-in clock-dithering circuit. The oscillator frequency is slightly modulated with a sub clock causing a clock dither of typically 6 ns. 8.3.5 Undervoltage Lockout The undervoltage lockout circuit prevents the device from malfunctioning at low input voltages and from excessive discharge of the battery. It disables the output stage of the converter once the falling V IN trips the undervoltage lockout threshold V UVLO. The undervoltage lockout threshold V UVLO for falling V IN is typically 1.78 V. The device starts operation once the rising V IN trips undervoltage lockout threshold V UVLO again at typically 1.95 V. 8.3.6 Thermal Shutdown As soon as the junction temperature, T J, exceeds 150°C (typical) the device goes into thermal shutdown. In this mode, the high-side and low-side MOSFETs are turned off. The device continues its operation with a soft start once the junction temperature falls below the thermal shutdown hysteresis. 8.4 Device Functional Modes 8.4.1 Soft Start The TPS6206x has an internal soft start circuit that controls the ramp up of the output voltage. Once the converter is enabled and the input voltage is above the undervoltage lockout threshold V UVLO the output voltage ramps up from 5% to 95% of its nominal value within tRamp of typically 250 µs. This limits the inrush current in the converter during start-up and prevents possible input voltage drops when a battery or high impedance power source is used. During soft start, the switch current limit is reduced to 1/3 of its nominal value I LIMF until the output voltage reaches 1/3 of its nominal value. Once the output voltage trips this threshold, the device operates with its nominal current limit ILIMF. 8.4.2 Power Save Mode At TPS62065 pulling the MODE pin low enables power save mode. In TPS62067 power save mode is enabled per default. If the load current decreases, the converter enters power save mode operation automatically. During power save mode the converter skips switching and operates with reduced frequency in PFM mode with a minimum quiescent current to maintain high efficiency. The converter positions the output voltage typically +1% above the nominal output voltage. This voltage positioning feature minimizes voltage drops caused by a sudden load step. The transition from PWM mode to PFM mode occurs once the inductor current in the low-side MOSFET switch becomes zero, which indicates discontinuous conduction mode. During the power save mode the output voltage is monitored with a PFM comparator. As the output voltage falls below the PFM comparator threshold of V OUTnominal +1%, the device starts a PFM current pulse. For this the high-side MOSFET switch will turn on and the inductor current ramps up. After the on-time expires the switch will be turned off and the low-side MOSFET switch will be turned on until the inductor current becomes zero. The converter effectively delivers a current to the output capacitor and the load. If the load is below the delivered current the output voltage will rise. If the output voltage is equal or higher than the PFM comparator threshold, the device stops switching and enters a sleep mode with typically 18 µA current consumption. In case the output voltage is still below the PFM comparator threshold, further PFM current pulses will be generated until the PFM comparator threshold is reached. The converter starts switching again once the output voltage drops below the PFM comparator threshold due to the load current. The PFM mode is exited and PWM mode entered in case the output current can no longer be supported in PFM mode. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS62065 TPS62067 9 TPS62065, TPS62067 www.ti.com SLVS833E – MARCH 2010 – REVISED OCTOBER 2020 8.4.3 Dynamic Voltage Positioning This feature reduces the voltage undershoots and overshoots at load steps from light to heavy load and vice versa. It is active in power save mode and regulates the output voltage 1% higher than the nominal value. This provides more headroom for both the voltage drop at a load step, and the voltage increase at a load throw-off. Output voltage Voltage Positioning VOUT + 1% PFM Comparator threshold Light load PFM Mode VOUT (PWM) Moderate to heavy load PWM Mode Figure 8-2. Power Save Mode Operation with Automatic Mode Transition 8.4.4 100% Duty Cycle Low Dropout Operation The device starts to enter 100% duty cycle mode as the input voltage comes close to the nominal output voltage. To maintain the output voltage, the high-side MOSFET switch is turned on 100% for one or more cycles. With further decreasing V IN the high-side MOSFET switch is turned on completely. In this case the converter offers a low input-to-output voltage difference. This is particularly useful in battery-powered applications to achieve longest operation time by taking full advantage of the whole battery voltage range. The minimum input voltage to maintain regulation depends on the load current and output voltage, and can be calculated as: VINmin = VOmax + IOmax × (RDS(on)max + RL) (1) where • • • • IOmax = maximum output current RDS(on)max = maximum P-channel switch RDS(on) RL = DC resistance of the inductor VOmax = nominal output voltage plus maximum output voltage tolerance 8.4.5 Internal Current Limit and Fold-Back Current Limit for Short Circuit Protection During normal operation the high-side and low-side MOSFET switches are protected by its current limits I LIMF. Once the high-side MOSFET switch reaches its current limit, it is turned off and the low-side MOSFET switch is turned on. The high-side MOSFET switch can only turn on again, once the current in the low-side MOSFET switch decreases below its current limit I LIMF. The device is capable to provide peak inductor currents up to its internal current limitILIMF.. As soon as the switch current limits are hit and the output voltage falls below 1/3 of the nominal output voltage due to overload or short circuit condition, the foldback current limit is enabled. In this case the switch current limit is reduced to 1/3 of the nominal value ILIMF. Due to the short circuit protection is enabled during start-up, the device does not deliver more than 1/3 of its nominal current limit I LIMF until the output voltage exceeds 1/3 of the nominal output voltage. This needs to be considered when a load is connected to the output of the converter, which acts as a current sink. 10 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS62065 TPS62067 www.ti.com TPS62065, TPS62067 SLVS833E – MARCH 2010 – REVISED OCTOBER 2020 8.4.6 Output Capacitor Discharge With EN = GND, the device enters shutdown mode and all internal circuits are disabled. The SW pin is connected to PGND through an internal resistor to discharge the output capacitor. This feature ensures a startup in a discharged output capacitor once the converter is enabled again and prevents "floating" charge on the output capacitor. The output voltage ramps up monotonic starting from 0 V. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS62065 TPS62067 11 TPS62065, TPS62067 www.ti.com SLVS833E – MARCH 2010 – REVISED OCTOBER 2020 9 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The TPS62065 and TPS62067 are highly efficient synchronous step down DC/DC converters providing up to 2-A output current. 9.2 Typical Application L 1.0 mH VIN = 2.9 V to 6 V PVIN SW R1 360 kΩ AVIN EN MODE AGND PGND CIN 10 µF VOUT = 1.8 V up to 2 A FB Cff 22 pF COUT 10 µF R2 180 kΩ Copyright © 2016, Texas Instruments Incorporated Figure 9-1. TPS62065 1.8-V Adjustable Output Voltage Configuration 9.2.1 Design Requirements The device operates over an input voltage range from 2.9 V to 6 V. The output voltage is adjustable using an external feedback divider. 9.2.2 Detailed Design Procedure 9.2.2.1 Output Voltage Setting The output voltage can be calculated to: æ R ö VOUT = VREF ´ ç1 + 1 ÷ è R2 ø æV ö R1 = ç OUT - 1÷ ´ R2 V è REF ø (2) with an internal reference voltage VREF typically 0.6 V. To minimize the current through the feedback divider network, R 2 should be within the range of 120 kΩ to 360 kΩ. The sum of R1 and R 2 should not exceed approximately 1 MΩ, to keep the network robust against noise. An external feed-forward capacitor Cff is required for optimum regulation performance. Lower resistor values can be used. R1 and Cff places a zero in the loop. The right value for Cff can be calculated as: fz = C ff = 12 1 = 25 kHz 2 ´ p ´ R1 ´ C ff (3) 1 2 ´ p ´ R1 ´ 25 kHz (4) Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS62065 TPS62067 TPS62065, TPS62067 www.ti.com SLVS833E – MARCH 2010 – REVISED OCTOBER 2020 9.2.2.2 Output Filter Design (Inductor and Output Capacitor) The internal compensation network of TPS6206x is optimized for a LC output filter with a corner frequency of: fc = 1 2 ´ p ´ (1μH ´ 10μF) = 50kHz (5) The device operates with nominal inductors of 1 µH to 1.2 µH and with 10 µF to 22 µF small X5R and X7R ceramic capacitors. Refer to the lists of inductors and capacitors. The device is optimized for a 1-µH inductor and 10-µF output capacitor. 9.2.2.2.1 Inductor Selection The inductor value has a direct effect on the ripple current. The selected inductor must be rated for its DC resistance and saturation current. The inductor ripple current (ΔI L) decreases with higher inductance and increases with higher VIN or VOUT. Equation 6 calculates the maximum inductor current in PWM mode under static load conditions. The saturation current of the inductor should be rated higher than the maximum inductor current as calculated with Equation 7. This is recommended because during heavy load transient the inductor current rises above the calculated value. Vout Vin L´ƒ 1DI L = Vout ´ IL max = Iout max + (6) DIL 2 (7) where • • • • f = Switching frequency (3 MHz typical) L = Inductor value ΔIL = Peak-to-peak inductor ripple current ILmax = Maximum inductor current A more conservative approach is to select the inductor current rating just for the switch current limit I LIMF of the converter. The total losses of the coil have a strong impact on the efficiency of the DC/DC conversion and consist of both the losses in the DC resistance R(DC) and the following frequency-dependent components: • • • • The losses in the core material (magnetic hysteresis loss, especially at high switching frequencies) Additional losses in the conductor from the skin effect (current displacement at high frequencies) Magnetic field losses of the neighboring windings (proximity effect) Radiation losses Table 9-1. List of Inductors DIMENSIONS (mm3) INDUCTANCE (μH) INDUCTOR TYPE SUPPLIER 3.2 × 2.5 × 1 maximum 1 LQM32PN (MLCC) Murata 3.7 × 4 × 1.8 maximum 1 LQH44 (wire wound) Murata 4 × 4 × 2.6 maximum 1.2 NRG4026T (wire wound) Taiyo Yuden 3.5 × 3.7 × 1.8 maximum 1.2 DE3518 (wire wound) TOKO 9.2.2.2.2 Output Capacitor Selection The advanced fast-response voltage mode control scheme of the TPS6206x allows the use of tiny ceramic capacitors. TI recommends ceramic capacitors with low ESR values that have the lowest output voltage ripple. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS62065 TPS62067 13 TPS62065, TPS62067 www.ti.com SLVS833E – MARCH 2010 – REVISED OCTOBER 2020 The output capacitor requires either an X7R or X5R dielectric. Y5V and Z5U dielectric capacitors, aside from their wide variation in capacitance over temperature, become resistive at high frequencies and may not be used. For most applications a nominal 10-µF or 22-µF capacitor is suitable. At small ceramic capacitors, the DC-bias effect decreases the effective capacitance. Therefore a 22-µF capacitor can be used for output voltages higher than 2 V, see list of capacitors. In case additional ceramic capacitors in the supplied system are connected to the output of the DC/DC converter, the output capacitor C OUT must be decreased in order not to exceed the recommended effective capacitance range. In this case a loop stability analysis must be performed as described later. At nominal load current, the device operates in PWM mode and the RMS ripple current is calculated as: Vout Vin 1 ´ L´ƒ 2´ 3 1IRMSCout = Vout ´ (8) 9.2.2.2.3 Input Capacitor Selection Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is required for best input voltage filtering and minimizing the interference with other circuits caused by high input voltage spikes. For most applications, TI recommends a 10-µF ceramic capacitor. The input capacitor can be increased without any limit for better input voltage filtering. Take care when using only small ceramic input capacitors. When a ceramic capacitor is used at the input and the power is being supplied through long wires, such as from a wall adapter, a load step at the output or VIN step on the input can induce ringing at the VIN pin. This ringing can couple to the output and be mistaken as loop instability or could even damage the part by exceeding the maximum ratings. Table 9-2. List of Capacitors TYPE SIZE (mm3) SUPPLIER 10μF GRM188R60J106M 0603: 1.6 x 0.8 x 0.8 Murata 22μF GRM188R60G226M 0603: 1.6 x 0.8 x 0.8 Murata 22µF CL10A226MQ8NRNC 0603: 1.6 x 0.8 x 0.8 Samsung 10µF CL10A106MQ8NRNC 0603: 1.6 x 0.8 x 0.8 Samsung CAPACITANCE 9.2.2.3 Checking Loop Stability The first step of circuit and stability evaluation is to look from a steady-state perspective at the following signal • • • Switching node, SW Inductor current, IL Output ripple voltage, VOUT(AC) These are the basic signals that must be measured when evaluating a switching converter. When the switching waveform shows large duty cycle jitter or the output voltage or inductor current shows oscillations, the regulation loop may be unstable. This is often a result of board layout and/or wrong L-C output filter combinations. As a next step in the evaluation of the regulation loop, the load transient response is tested. The time between the application of the load transient and the turnon of the P-channel MOSFET, the output capacitor must supply all of the current required by the load. V OUT immediately shifts by an amount equal to Δ I(LOAD) x ESR, where ESR is the effective series resistance of COUT. ΔI(LOAD) begins to charge or discharge COUT generating a feedback error signal used by the regulator to return VOUT to its steady-state value. The results are most easily interpreted when the device operates in PWM mode at medium to high load currents. During this recovery time, V OUT can be monitored for settling time, overshoot, or ringing; that helps evaluate stability of the converter. Without any ringing, the loop has usually more than 45° of phase margin. 14 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS62065 TPS62067 TPS62065, TPS62067 www.ti.com SLVS833E – MARCH 2010 – REVISED OCTOBER 2020 9.2.3 Application Curves 100 100 95 95 90 VIN = 4.2 V 80 VIN = 3 V 75 VIN = 3.3 V VIN = 3.6 V 70 65 55 50 0 VIN = 3.3 V 75 VIN = 3.6 V 70 0.25 0.5 0.75 1 1.25 1.5 IL - Load Current - A 1.75 100 L = 1.2 mH (NRG4026T 1R2), COUT = 10 mF (0603 size), VOUT = 1.8 V, Mode: Auto PFM/PWM 60 55 50 0 2 Figure 9-2. VOUT = 1.2 V, Auto PFM/PWM Mode, Linear Scale 0.25 0.5 0.75 1 1.25 1.5 IL - Load Current - A 1.75 2 Figure 9-3. VOUT = 1.8 V, Auto PFM/PWM Mode, Linear Scale 100 VIN = 3.7 V Auto PFM/PWM Mode 95 90 90 VIN = 4.2 V 80 VIN = 5 V 85 70 Efficiency - % Efficiency - % VIN = 3 V 80 65 L = 1.2 mH (NRG4026T 1R2), COUT = 10 mF (0603 size), VOUT = 1.2 V, Mode: Auto PFM/PWM 60 80 75 70 VIN = 3.3 V VIN = 3.6 V VIN = 4.2 V VIN = 5 V Forced PWM Mode 60 VIN = 3.3 V VIN = 3.6 V VIN = 4.2 V VIN = 5 V 50 40 30 65 L = 1.2 mH (NRG4026T 1R2), COUT = 22 mF (0603 size), VOUT = 3.3 V, Mode: Auto PFM/PWM 60 55 0 0.25 0.5 0.75 1 1.25 1.5 IL - Load Current - A 1.75 20 0 0.001 2 1.872 1.872 1.854 Voltage Positioning PFM Mode 1.854 VO - Output Voltage DC - V 1.890 1.836 1.818 1.800 VIN = 3.6 V VIN = 4.2 V 1.782 1.764 PWM Mode VIN = 5 V L = 1 mH, COUT = 10 mF, VOUT = 1.8 V, Mode: Auto PFM/PWM 1.746 1.728 1.710 0.001 0.01 0.1 IL - Load Current - A 1 Figure 9-6. Auto PFM/PWM Mode 0.01 0.1 IL - Load Current - A 1 10 Figure 9-5. Auto PFM/PWM Mode vs. Forced PWM Mode, Logarithmic Scale 1.890 VIN = 3.3 V L = 1.2 mH (NRG4026T 1R2), COUT = 10 mF (0603 size), VOUT = 1.8 V 10 Figure 9-4. VOUT = 3.3 V, Auto PFM/PWM Mode, Linear Scale VO - Output Voltage DC - V VIN = 5 V 85 Efficiency - % Efficiency - % 85 50 VIN = 4.2 V 90 VIN = 5 V L = 1 mH, COUT = 10 mF, VOUT = 1.8 V, Mode: Forced PWM 1.836 1.818 1.800 VIN = 3.3 V 1.782 VIN = 3.6 V VIN = 4.2 V 1.764 VIN = 5 V 1.746 1.728 10 1.710 0.001 0.01 0.1 IL - Load Current - A 1 10 Figure 9-7. Forced PWM Mode Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS62065 TPS62067 15 TPS62065, TPS62067 www.ti.com SLVS833E – MARCH 2010 – REVISED OCTOBER 2020 VOUT 50mV/Div VOUT 50mV/Div VIN = 3.6 V VOUT = 1.8 V IOUT = 20 mA MODE = GND L = 1.2 mH COUT = 10 mF SW 2V/Div SW 2V/Div ICOIL 500mA/Div MODE = GND VIN = 3.6 V L = 1.2 mH VOUT = 1.8 V IOUT = 500 mA COUT = 10 mF ICOIL 200mA/Div Time Base - 100ns/Div Time Base - 4ms/Div Figure 9-8. Typical Operation (PWM Mode) Figure 9-9. Typical Operation (PFM Mode) VOUT100 mV/Div VOUT100 mV/Div SW 2V/Div SW 2V/Div ICOIL1A/Div ICOIL1A/Div VIN = 3.6 V, VOUT = 1.2 V, IOUT = 0.2 A to 1 A MODE = VIN ILOAD500 mA/Div VIN = 3.6 V, VOUT = 1.2 V, IOUT = 20 mA to 250 mA ILOAD500 mA/Div Time Base - 10 µs/Div Time Base - 10 µs/Div Figure 9-10. Load Transient Response PWM Mode 0.2 A to 1 A Figure 9-11. Load Transient PFM Mode 20 mA to 250 mA VIN = 3.6 V to 4.2 V, VOUT = 1.8 V, IOUT = 500 mA L = 1.2 mH, 200 mV/Div 500 mV/Div 2A/Div VIN = 3.6 V, VOUT = 1.8 V, 1A/Div 50 mV/Div L = 1.2 mH COUT = 10 mF IOUT 200 mA to 1500 mA Time Base - 100 ms/Div Time Base - 100ms/Div Figure 9-12. Load Transient Response 200 mA to 1500 mA 16 Figure 9-13. Line Transient Response PWM Mode Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS62065 TPS62067 TPS62065, TPS62067 www.ti.com SLVS833E – MARCH 2010 – REVISED OCTOBER 2020 2 V/Div 500 mV/Div 1 V/Div 2 A/Div 500 mA/Div VIN = 3.6 V to 4.2 V, VOUT = 1.8 V, IOUT = 50 mA, 50 mV/Div L = 1.2 mH, COUT = 10 mF 500 mA/Div VIN = 3.6 V, L = 1.2 mH, VOUT = 1.8 V, COUT = 10 mF Load = 2R2 Time Base - 100 ms/Div Time Base - 100 ms/Div Figure 9-14. Line Transient PFM Mode Figure 9-15. Startup Into Load – VOUT 1.8 V EN 1 V/Div VIN = 3.6 V, VOUT = 1.8 V, COUT = 10 mF, No Load 2 V/Div SW 2 V/Div 2 V/Div VOUT 1 V/Div 1 A/Div 2 V/Div VIN = 4.2 V, VOUT = 3.3 V, Load = 2R2 PG Pullup resistor 10 kW Time Base - 2ms/Div Time Base - 100 ms/Div Figure 9-17. Output Discharge Figure 9-16. Start-up TPS62067 Into 2.2-Ω Load With Power Good VIN = 4.2 V, VOUT = 3.3 V, Load = no load PG Pullup resistor 10 kW 2 V/Div 2 V/Div 5 V/Div Time Base - 1 ms/Div Figure 9-18. Shutdown TPS62067 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS62065 TPS62067 17 TPS62065, TPS62067 www.ti.com SLVS833E – MARCH 2010 – REVISED OCTOBER 2020 9.3 System Example The TPS62067 provides an open-drain power good output, refer to Section 8.3.2. 9.3.1 TPS62067 Adjustable 1.8-V Output L 1.0 mH VIN = 2.9 V to 6 V PVIN CIN 10 mF AVIN EN AGND PGND VOUT 1.8 V 2 A SW R1 360 kW FB PG R2 180 kW Cff COUT 22 pF 10 mF RPG 100 kW Copyright © 2016, Texas Instruments Incorporated Figure 9-19. TPS62067 Adjustable 1.8-V Output 18 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS62065 TPS62067 TPS62065, TPS62067 www.ti.com SLVS833E – MARCH 2010 – REVISED OCTOBER 2020 10 Power Supply Recommendations The power supply to the TPS6206x must have a current rating according to the supply voltage, output voltage, and output current of the TPS6206x. 11 Layout 11.1 Layout Guidelines Take care in board layout to get the specified performance. If the layout is not carefully done, the regulator could show poor line and/or load regulation, stability issues as well as EMI and thermal problems. It is critical to provide a low inductance, impedance ground path. Therefore, use wide and short traces for the main current paths. The input capacitor should be placed as close as possible to the IC pins as well as the inductor and output capacitor. Connect the AGND and PGND pins of the device to the PowerPAD™ land of the PCB and use this pad as a star point. Use a common power PGND node and a different node for the signal AGND to minimize the effects of ground noise. The FB divider network should be connected right to the output capacitor and the FB line must be routed away from noisy components and traces (for example, SW line). Due to the small package of this converter and the overall small solution size the thermal performance of the PCB layout is important. To get a good thermal performance, TI recommends a four or more Layer PCB design. The PowerPAD™ of the IC must be soldered on the power pad area on the PCB to get a proper thermal connection. For good thermal performance the PowerPAD™ on the PCB needs to be connected to an inner GND plane with sufficient via connections. Refer to the documentation of the evaluation kit. Mode/PG Enable 11.2 Layout Example VIN GND CIN COUT R2 R1 CFF GND L VOUT Figure 11-1. PCB Layout Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS62065 TPS62067 19 TPS62065, TPS62067 www.ti.com SLVS833E – MARCH 2010 – REVISED OCTOBER 2020 12 Device and Documentation Support 12.1 Device Support 12.1.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 12.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 12-1. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY TPS62065 Click here Click here Click here Click here Click here TPS62067 Click here Click here Click here Click here Click here 12.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.4 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 12.5 Trademarks PowerPAD™ and TI E2E™ are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 12.6 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.7 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 20 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS62065 TPS62067 PACKAGE OPTION ADDENDUM www.ti.com 29-Apr-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPS62065DSGR ACTIVE WSON DSG 8 3000 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR -40 to 125 OFA TPS62065DSGT ACTIVE WSON DSG 8 250 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR -40 to 125 OFA TPS62067DSGR ACTIVE WSON DSG 8 3000 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR -40 to 125 ODH TPS62067DSGT ACTIVE WSON DSG 8 250 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR -40 to 125 ODH (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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