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TPS62065-Q1, TPS62067-Q1
SLVSCM3A – JANUARY 2015 – REVISED MAY 2020
TPS6206x-Q1 3-MHz 2-A Step-Down Converter in 2 × 2 SON Package
1 Features
3 Description
•
The TPS62065-Q1 and TPS62067-Q1 device is a
highly-efficient synchronous step-down DC-DC
converter. The device provides up to 2-A output
current.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
New product available: TPS628502-Q1, 6-V StepDown Converter in SOT583 Package
AEC-Q100 qualified with the following results:
– Device temperature grade 1: –40°C to 125°C
operating junction temperature range
– Device HBM ESD classification level 2
– Device CDM ESD classification level C4B
Functional Safety-Capable
– Documentation available to aid functional
safety system design
3-MHz Switching frequency
VIN Range from 2.9 V to 6 V
Up to 97% efficiency
Power save mode and 3-MHz fixed PWM mode
Power good output
Output voltage accuracy in PWM mode ±1.5%
Output capacitor discharge function
Typical 18-µA quiescent current
100% Duty cycle for lowest dropout
Voltage Positioninp
Clock dithering
Available in a 2 × 2 × 0.75-mm WSON
The new product, TPS628502-Q1, offers reduced
BOM cost and size, higher efficiency and other
features.
Device Information(1)
PART NUMBER
2 Applications
•
•
With an input voltage range of 2.9 V to 6 V the device
is a perfect fit for power conversion from a 5-V or
3.3-V system supply rail. The TPS62065-Q1 and
TPS62067-Q1 device operates at 3-MHz fixed
frequency and enters power-save mode operation at
light load currents to maintain high efficiency over the
entire load current range. The power save mode is
optimized for low output-voltage ripple. For low noise
applications, the TPS62065-Q1 device can be forced
into fixed frequency PWM mode by pulling the MODE
pin high. The TPS62067-Q1 provides an open drain
power good output. In the shutdown mode, the
current consumption is reduced to 5 µA and an
internal circuit discharges the output capacitor. The
TPS62065-Q1 and TPS62067-Q1 device is optimized
for operation with a tiny 1-µH inductor and a small 10µF output capacitor to achieve smallest solution size
and high regulation performance.
TPS62065-Q1
Advanced driver assistance systems
Automotive infotainment & cluster
CIN
10 µF
PVIN
AVIN
EN
R1
360 kΩ
FB
R2
180 kΩ
Cff
COUT
22 pF 10 µF
2.00 mm × 2.00 mm
Efficiency vs Load Current
VOUT
1.8 V 2 A
SW
BODY SIZE
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
100
95
RPG
100 kΩ
90
85
PG
Efficiency (%)
AGND
PGND
L
1 µH
WSON (8)
TPS62067-Q1
Typical Application Circuit
VIN = 2.9 V to 6 V
PACKAGE
80
75
70
65
60
L = 1.2 µH (NRG4026T 1R2),
COUT = 22 µF (0603 size),
VOUT = 3.3 V,
Mode: Auto PFM/PWM
55
50
0
0.25
0.5
0.75
1
1.25
Load Current (A)
VIN = 3.7 V
VIN = 4.2 V
VIN = 5 V
1.5
1.75
2
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS62065-Q1, TPS62067-Q1
SLVSCM3A – JANUARY 2015 – REVISED MAY 2020
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
4
4
4
4
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 8
Detailed Description .............................................. 9
9.1 Overview ................................................................... 9
9.2 Functional Block Diagram ......................................... 9
9.3 Feature Description................................................. 10
9.4 Device Functional Modes........................................ 11
10 Application and Implementation........................ 13
10.1 Application Information.......................................... 13
10.2 Typical Application ................................................ 13
11 Power Supply Recommendations ..................... 20
12 Layout................................................................... 21
12.1 Layout Guidelines ................................................. 21
12.2 Layout Example .................................................... 21
13 Device and Documentation Support ................. 22
13.1
13.2
13.3
13.4
13.5
Device Support......................................................
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
22
22
22
22
22
14 Mechanical, Packaging, and Orderable
Information ........................................................... 22
4 Revision History
Changes from Original (January 2015) to Revision A
Page
•
Added Functional safety capable bullet.................................................................................................................................. 1
•
Updated power-good description.......................................................................................................................................... 10
•
Updated the output discharge function description. ............................................................................................................. 10
•
Added PFM/PWM mode checking block description............................................................................................................ 12
•
Updated the recommended list of the inductors................................................................................................................... 14
•
Corrected the output current value on Figure 20 ................................................................................................................. 17
2
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SLVSCM3A – JANUARY 2015 – REVISED MAY 2020
5 Device Comparison Table
PART NUMBER
MODE/PG FUNCTION
TPS62065Q1
MODE = selectable; Power Good = no
TPS62067Q1
Automatic PWM/PFM transition; Power Good = yes
6 Pin Configuration and Functions
PGND
1
SW
2
AGND
3
FB
4
Thermal Pad
DSG Package
8-Pin WSON With Exposed Thermal Pad
Top View
8
PVIN
7
AVIN
6
MODE/PG
5
EN
Pin Functions
PIN
TYPE
DESCRIPTION
NO.
NAME
1
PGND
—
2
SW
OUT
3
AGND
—
Analog GND supply pin for the control circuit
4
FB
IN
Feedback pin for the internal regulation loop. Connect the external resistor divider to this pin.
In case of the fixed output voltage option, connect this pin directly to the output capacitor.
5
EN
IN
This is the enable pin of the device. Pulling this pin to low forces the device into shutdown
mode. Pulling this pin to high enables the device. This pin must be terminated.
IN
MODE: MODE pin = high forces the device to operate in fixed frequency PWM mode. MODE
pin = low enables the power save mode with automatic transition from PFM mode to fixed
frequency PWM mode. This pin must be terminated. (TPS62065-Q1)
6
MODE/PG
Open Drain
7
AVIN
IN
8
PVIN
PWR
—
Thermal Pad
—
GND supply pin for the output stage
This is the switch pin and is connected to the internal MOSFET switches. Connect the
external inductor between this terminal and the output capacitor.
PG: Power Good open-drain output. Connect an external pullup resistor to a rail which is
below or equal AVIN. (TPS62067-Q1)
Analog VIN power supply for the control circuit must be connected to PVIN and input
capacitor.
VIN power supply pin for the output stage
For good thermal performance, this pad must be soldered to the land pattern on the PCB.
This pad should be used as device GND.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted) (1)
Voltage
(2)
MIN
MAX
AVIN, PVIN
–0.3
7
EN, MODE/PG, FB
–0.3
VIN + 0.3 < 7
SW
–0.3
7
Current (sink)
into PG
Current (source)
Peak output
UNIT
V
1
mA
Internally limited
A
Junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–65
150
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
7.2 ESD Ratings
VALUE
Human body model (HBM), per AEC Q100-002
V(ESD)
(1)
Electrostatic discharge
Charged device model (CDM), per AEC
Q100-011
(1)
UNIT
±2500
Corner pins (1, 4, 5, and 8)
±750
Other pins
±500
V
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
MIN
AVIN ,
PVIN
Supply voltage
NOM
2.9
6
Output current capability
Output voltage range for adjustable voltage
0.8
L
Effective Inductance Range
0.7
COUT
Effective Output Capacitance Range
4.5
TJ
Operating junction temperature
–40
MAX
UNIT
V
2000
mA
VIN
V
1
1.6
µH
10
22
µF
125
°C
7.4 Thermal Information
DSG (WSON)
8 PINS
THERMAL METRIC (1)
RθJA
Junction-to-ambient thermal resistance
64.78
RθJC(top)
Junction-to-case (top) thermal resistance
80.60
RθJB
Junction-to-board thermal resistance
34.63
ψJT
Junction-to-top characterization parameter
1.65
ψJB
Junction-to-board characterization parameter
35.02
RθJC(bot)
Junction-to-case (bottom) thermal resistance
6.61
(1)
4
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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SLVSCM3A – JANUARY 2015 – REVISED MAY 2020
7.5 Electrical Characteristics
Over operating junction temperature range (TJ = –40°C to 125°C), typical values are at TJ = 25°C. Unless otherwise noted,
specifications apply for condition VIN = EN = 3.6 V. External components CIN = 10 μF 0603, COUT = 10 μF 0603, L = 1 μH.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
VIN
Input voltage range
2.9
IQ
Operating quiescent current
IOUT = 0 mA, device operating in PFM mode
and not device not switching
ISD
Shutdown current
EN = GND, current into AVIN and PVIN combined
VUVLO
Undervoltage lockout threshold
6
18
0.1
5
V
μA
Falling
1.73
1.78
1.83
Rising
1.9
1.95
1.99
μA
V
ENABLE, MODE
VIH
High level input voltage
2.9 V ≤ VIN ≤ 6 V
1
6
VIL
Low level input voltage
2.9 V ≤ VIN ≤ 6 V
0
0.4
V
IIN
Input bias current
EN, Mode tied to GND or AVIN
0.01
1
μA
V
POWER GOOD OPEN DRAIN OUTPUT
VTHPG
Power good threshold voltage
Rising feedback voltage
93%
95%
98%
Falling feedback voltage
87%
90%
92%
VOL
Output low voltage
IOUT = –1 mA; must be limited by external pullup
resistor (1)
ILKG
Leakage current into PG pin
V(PG) = 3.6 V
tPGDL
Internal power good delay time
0.3
100
5
V
nA
µs
POWER SWITCH
VIN = 3.6 V
(1)
120
180
95
150
90
130
75
100
2750
3300
RDS(on)
High-side MOSFET on-resistance
RDS(on)
Low-side MOSFET on-resistance
ILIMF
Forward current limit MOSFET
high-side and low-side
2.9 V ≤ VIN ≤ 6 V
Thermal shutdown
Increasing junction temperature
150
Thermal shutdown hysteresis
Decreasing junction temperature
10
TSD
VIN = 5 V
(1)
VIN = 3.6 V (1)
VIN = 5 V
(1)
2300
mΩ
mΩ
mA
°C
OSCILLATOR
fSW
2.9 V ≤ VIN ≤ 6 V
Oscillator frequency
2.6
3
3.4
MHz
OUTPUT
Vref
Reference voltage
VFB(PWM)
VFB(PFM)
600
Feedback voltage PWM Mode
Feedback voltage PFM mode,
Voltage Positioning
PWM operation, MODE = VIN ,
2.9 V ≤ VIN ≤ 6 V, 0-mA load
device in PFM mode, voltage positioning active
–1.5%
1%
Line regulation
R(Discharge)
Internal discharge resistor
Activated with EN = GND, 2.9 V ≤ VIN ≤ 6 V, 0.8 ≤
VOUT ≤ 3.6 V
tSTART
Start-up time
Time from active EN to reach 95% of VOUT
(1)
(2)
1.5%
(2)
Load regulation
VFB
0%
mV
75
–0.5
%/A
0
%/V
200
1450
500
Ω
μs
Maximum value applies for TJ = 85°C
In PFM mode, the internal reference voltage is set to typ. 1.01 × Vref. See the parameter measurement information.
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7.6 Typical Characteristics
Table 1. Table of Graphs
FIGURE
6
Shutdown Current
Input Voltage and Ambient Temperature
Figure 1
Quiescent Current
Input Voltage
Figure 2
Oscillator Frequency
Input Voltage
Figure 3
Static Drain-Source On-State
Resistance
Input Voltage, Low-Side Switch
Figure 4
Input Voltage, High-Side Switch
Figure 5
RDISCHARGE
Input Voltage vs. VOUT
Figure 6
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1
25
TJ = –40°C
TJ = 25°C
TJ = 85°C
20
Quiescent Current (µA)
Shutdown Current (µA)
0.75
0.50
15
10
0.25
5
0
2.5
3
3.5
4
4.5
Input Voltage (V)
5
5.5
0
2.5
6
3.1
0.12
3.05
0.1
3
0.08
2.9
3.5
4
4.5
Input Voltage (V)
5
5.5
6
0.06
0.04
2.85
2.8
2.5
3
Figure 2. Quiescent Current vs Input Voltage
RDSON (Ω)
Oscillator Frequency (MHz)
Figure 1. Shutdown Current vs Input Voltage and Ambient
Temperature
2.95
TJ = –40°C
TJ = 25°C
TJ = 85°C
TJ = –40°C
TJ = 25°C
TJ = 85°C
3
3.5
4
4.5
Input Voltage (V)
5
5.5
TJ = –40°C
TJ = 25°C
TJ = 85°C
0.02
0
2.5
6
3
3.5
4
4.5
Input Voltage (V)
5
5.5
6
Low-Side Switch
Figure 3. Oscillator Frequency vs Input Voltage
Figure 4. Static Drain-Source On-State Resistance vs Input
Voltage
600
0.2
VO = 1.2 V
VO = 1.8 V
VO = 3.3 V
0.18
500
0.16
400
Rdischarge (Ω)
RDSON (Ω)
0.14
0.12
0.1
0.08
200
0.06
0.04
100
TJ = –40°C
TJ = 25°C
TJ = 85°C
0.02
0
2.5
300
3
3.5
4
4.5
Input Voltage (V)
5
5.5
6
0
2.5
3
3.5
4
4.5
Input Voltage (V)
5
5.5
6
High-Side Switch
Figure 5. Static Drain-Source On-State Resistance vs Input
Voltage
Figure 6. RDISCHARGE vs Input Voltage
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8 Parameter Measurement Information
PVIN
SW
AVIN
R1
Cff
EN
CIN
10 µF
VOUT
up to 2.0 A
L
1 µH / 1.2 µH
VIN = 2.9 V to 6 V
MODE/PG
AGND
FB
COUT
10 µF
R2
PGND
L: LQH44PN1R0NP0, L = 1 µH, Murata, NRG4026T1R2, L = 1.2 µH, Taiyo Yuden
CIN/COUT: GRM188R60J106U, Murata 0603 size
8
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9 Detailed Description
9.1 Overview
The TPS62065-Q1 and TPS62067-Q1 step-down converter operates with 3-MHz (typical) fixed-frequency pulsewidth modulation (PWM) at moderate to heavy load currents. At light load currents, the converter can
automatically enter power save mode and then operate in pulse-frequency mode (PFM).
During PWM operation, the converter uses a unique fast-response voltage-mode controller scheme with inputvoltage feedforward to achieve good line and load regulation, which allows the use of small ceramic input and
output capacitors. At the beginning of each clock cycle initiated by the clock signal, the high-side MOSFET switch
is turned on. The current flows from the input capacitor through the high-side MOSFET switch through the
inductor to the output capacitor and load. During this phase, the current ramps up until the PWM comparator trips
and the control logic turns off the switch. The current-limit comparator also turns off the switch in case the
current-limit of the high-side MOSFET switch is exceeded. After a dead time preventing shoot-through current,
the low-side MOSFET rectifier is turned on and the inductor current ramps down. The current now flows from the
inductor to the output capacitor and to the load. The current returns back to the inductor through the low-side
MOSFET rectifier.
The next cycle is initiated by the clock signal again turning off the low-side MOSFET rectifier and turning on the
high-side MOSFET switch.
9.2 Functional Block Diagram
AVIN
PVIN
Current
Limit Comparator
Undervoltage
Lockout 1.8V
Thermal
Shutdown
Limit
High Side
PFM Comparator
Reference
0.6V VREF
FB
VREF
Softstart
VOUT RAMP
CONTROL
Gate Driver
Anti
Shoot-Through
Control
Stage
Error Amp.
VREF
SW
Integrator
FB
Zero-Pole
Amp.
Internal
FB
Network(1)
PWM
Comp.
Limit
Low Side
MODE(1)
Sawtooth
Generator
3MHz
Clock
Current
Limit Comparator
PG
MODE/
FB
PG
VREF
RDischarge
PG Comparator(1)
AGND
(1)
EN
PGND
Function depends on device option.
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9.3 Feature Description
9.3.1 Mode Selection and Forced PWM Mode (TPS62065-Q1)
The MODE pin allows mode selection between forced PWM mode and power save mode.
Connecting this pin to GND enables the power save mode with an automatic transition between PWM and PFM
mode. Pulling the MODE pin high forces the converter to operate in fixed frequency PWM mode, even at light
load currents, which allows simple filtering of the switching frequency for noise-sensitive applications. In this
mode, the efficiency is lower compared to when the device is in power save mode during light loads.
The condition of the MODE pin can be changed during operation and allows efficient power management by
adjusting the operation mode of the converter to the specific system requirements.
For the TPS62067-Q1, where the MODE pin is replaced with the PG pin, the power save mode is enabled per
default.
9.3.2 Power Good (PG, TPS62067-Q1)
The Power Good (PG) pin indicates whether the output voltage has reached its regulation voltage. The PG pin
can be used for sequencing of other system rails. The PG pin is an open-drain output that requires a pullup
resistor to any voltage up to any voltage rail lower or equal the voltage applied to AVIN pin of the device. A 100kΩ pullup resistor is recommended, and this value can be adjusted as described in the Choosing an Appropriate
Pulllup/Pulldown Resistor for Open Drain Outputs Application Report.
If the power-good output is not used, it is recommended to tie to GND or leave open. The PG pin can sink a
maximum of 1 mA. Table 2 shows the typical logic states of the PG pin.
Table 2. PG Pin Functional Table
DEVICE CONDITIONS
PG STATUS
HIGH IMPEDANCE
EN = High, VFB ≥ 0.57 V
Enable
LOW
√
EN = High, VFB ≤ 0.54 V
√
Shutdown
EN = Low
√
Thermal Shutdown
TJ > TJSD
UVLO
VIN < VUVLO
√
undefined
9.3.3 Enable
Setting the EN pin high enables the device. At first, the internal reference is activated and the internal analog
circuits are settled. Afterwards, the soft start is activated and the output voltage is ramped up. The output voltage
reaches 95% of the nominal value within tSTART which is 500 µs (typical) after the device has been enabled. The
EN input can be used to control power sequencing in a system with various DC-DC converters. The EN pin can
connect to the output of another converter to drive the EN pin high and get a sequencing of supply rails.
9.3.4 Shutdown and Output Discharge
When EN is pulled low, the device enters shutdown mode. In this mode, all circuits are disabled and the SW pin
is connected to PGND through an internal resistor to discharge the output. This feature ensures a start-up in a
discharged output capacitor once the converter is enabled again and prevents a floating charge on the output
capacitor. The input voltage must remain higher than 1 V (TYP) to keep the output discharge function.
9.3.5 Soft Start
The TPS62065-Q1 and TPS62067-Q1 devices has an internal soft-start circuit that controls the ramp up of the
output voltage. When the converter is enabled and the input voltage is above the UVLO threshold, VUVLO, the
output voltage ramps up from 5% to 95% of the nominal value with a tRamp value of 250 µs (typical). The ramp
time limits the inrush current in the converter during start-up and prevents possible input voltage drops when a
battery or high impedance power source is used.
10
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During soft start, the switch current-limit is reduced to 1/3 of the nominal value, ILIMF, until the output voltage
reaches 1/3 of the nominal value. When the output voltage trips this threshold, the device operates with the
nominal current limit, ILIMF.
9.3.6 Undervoltage Lockout (UVLO)
The UVLO circuit prevents the device from malfunctioning at low input voltages and from excessive discharge of
the battery. It disables the output stage of the converter once the falling VIN trips the UVLO threshold, VUVLO.
The UVLO threshold, VUVLO, for falling VIN is typically 1.78 V. The device starts operation once the rising VIN trips
VUVLO again at typically 1.95 V.
9.3.7 Internal Current Limit and Foldback Current Limit For Short-Circuit Protection
During normal operation, the high-side and low-side MOSFET switches are protected by the current limit ILIMF.
When the high-side MOSFET switch reaches the current limit, it turns off and the low-side MOSFET switch turns
on. The high-side MOSFET switch can only turn on again when the current in the low-side MOSFET switch
decreases below ILIMF. The device is capable of providing peak-inductor currents up to the internal current limit,
ILIMF..
As soon as the switch current limits are met and the output voltage falls below 1/3 of the nominal output voltage
because of overload or short circuit condition, the foldback current limit is enabled. In this case, the switch
current-limit is reduced to 1/3 of the nominal value ILIMF.
Because the short-circuit protection is enabled during start-up, the device does not deliver more than 1/3 of the
nominal current limit, ILIMF, until the output voltage exceeds 1/3 of the nominal output voltage. This protection
must be considered when a load is connected to the output of the converter, which acts as a current sink.
9.3.8 Clock Dithering
To reduce the noise level of switch-frequency harmonics in the higher RF bands, the TPS62065-Q1 and
TPS62067-Q1 devices has a built-in clock-dithering circuit. The oscillator frequency is slightly modulated with a
sub clock, causing a clock dither of 6 ns (typical).
9.3.9 Thermal Shutdown
As soon as the junction temperature, TJ, exceeds 150°C (typical), the device enters thermal shutdown. In this
mode, the high-side and low-side MOSFETs are turned off. The device continues operation with a soft start once
the junction temperature falls below the thermal shutdown hysteresis.
9.4 Device Functional Modes
9.4.1 Power Save Mode
The TPS62065-Q1 pulling the MODE pin low enables power save mode. For the TPS62067-Q1, power-save
mode is enabled per default. If the load current decreases, the converter enters power save mode operation
automatically. During power save mode, the converter skips switching and operates with reduced frequency in
PFM mode with a minimum quiescent current to maintain high efficiency. The converter positions the output
voltage 1% (typical) above the nominal output voltage. This voltage positioning feature minimizes voltage drops
caused by a sudden load step.
The transition from PWM mode to PFM mode occurs when the inductor current in the low-side MOSFET switch
becomes zero, which indicates discontinuous conduction mode.
During power save mode, the output voltage is monitored with a PFM comparator. As the output voltage falls
below the PFM comparator threshold of VOUTnominal +1%, the device starts a PFM current pulse. For this, the
high-side MOSFET switch turns on and the inductor current ramps up. After the on-time expires, the switch is
turned off and the low-side MOSFET switch is turned on until the inductor current becomes zero. In case the
output voltage is still below the PFM comparator threshold, further PFM current pulses are generated until the
PFM comparator reaches its threshold. The converter starts switching again once the output voltage drops below
the PFM comparator threshold due to the load current.
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Device Functional Modes (continued)
If power save mode is enabled (TPS62065-Q1, MODE = Low), the device regularly checks to see if PFM mode
needs to be entered. The checking occurs at about a 100-kHz rate and can show up as a small ripple on the
output. Enabled forced PWM mode (MODE = High) disables the checking circuit. The TPS62067-Q1 always
checks for PFM mode.
9.4.1.1 Dynamic Voltage Positioning
This feature reduces the voltage undershoots or overshoots at load steps from light to heavy load and vice versa.
It is active in power save mode and regulates the output voltage 1% higher than the nominal value. This provides
more headroom for both the voltage drop at a load step, and the voltage increase at a load throw-off.
Output voltage
Voltage Positioning
VOUT +1%
PFM Comparator
threshold
Light load
PFM Mode
VOUT (PWM)
Moderate to heavy load
PWM Mode
Figure 7. Power Save Mode Operation with Automatic Mode Transition
9.4.1.2 100% Duty-Cycle Low-Dropout Operation
The device starts to enter 100% duty cycle mode as the input voltage comes close to the nominal output voltage.
To maintain the output voltage, the high-side MOSFET switch is turned on 100% for one or more cycles.
To further decrease VIN, the high-side MOSFET switch is turned on completely. In this case, the converter offers
a low input-to-output voltage difference. This is particularly useful in battery-powered applications to achieve
longest operation time by taking full advantage of the whole battery voltage range.
The minimum input voltage to maintain regulation depends on the load current and output voltage, and can be
calculated as:
VINmin = VOmax + IOmax × (RDS(on)max + RL)
where
•
•
•
•
12
IOmax = maximum output current
RDS(on)max = maximum P-channel switch RDS(on)
RL = DC resistance of the inductor
VOmax = nominal output voltage plus maximum output voltage tolerance
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The TPS62065-Q1 and TPS62067-Q1 are highly efficient synchronous 2-A step down DC-DC converters.
10.2 Typical Application
L
1 µH
VIN = 2.9 V to 6 V
PVIN
SW
R1
360 kΩ
AVIN
EN
MODE
AGND
PGND
CIN
10 µF
VOUT = 1.8 V
up to 2 A
FB
Cff
22 pF
COUT
10 µF
R2
180 kΩ
Figure 8. TPS62065-Q1 Adjustable 1.8-V Output-Voltage Configuration
L
1 µH
VIN = 2.9 V to 6 V
PVIN
SW
R1
360 kΩ
AVIN
EN
CIN
10 µF
FB
AGND
PGND
VOUT
1.8 V 2 A
PG
Cff
COUT
22 pF 10 µF
RPG
100 kΩ
R2
180 kΩ
Figure 9. TPS62067-Q1 Adjustable 1.8-V Output-Voltage Configuration
10.2.1 Design Requirements
The device operates over an input voltage range from 2.9 V to 6 V. The output voltage is adjustable using an
external feedback divider.
10.2.2 Detailed Design Procedure
10.2.2.1 Output Voltage Setting
The output voltage can be calculated to:
æ R ö
VOUT = VREF ´ ç1 + 1 ÷
è R2 ø
æV
ö
R1 = ç OUT - 1÷ ´ R2
è VREF
ø
(2)
with an internal reference voltage VREF typically 0.6 V.
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Typical Application (continued)
To minimize the current through the feedback divider network, R2 must be within the range of 120 kΩ to 360 kΩ.
The sum of R1 and R2 must not exceed approximately 1 MΩ in order to keep the network robust against noise.
An external feedforward capacitor, Cff, is required for optimum regulation performance. Lower resistor values can
be used. R1 and Cff place a zero in the loop. The right value for Cff can be calculated as:
1
fz =
= 25 kHz
2 ´ p ´ R1 ´ Cff
(3)
C ff =
1
2 ´ p ´ R1 ´ 25 kHz
(4)
10.2.2.2 Output Filter Design (Inductor And Output Capacitor)
The internal compensation network of TPS62065-Q1 and TPS62067-Q1 is optimized for a LC output filter with a
corner frequency of:
fC =
1
2´p´
( 1 µH ´ 10 µF )
= 50 kHz
(5)
The part operates with nominal inductors of 1 µH to 1.2 µH and with 10-µF to 22-µF small X5R and X7R ceramic
capacitors. Refer to the lists of inductors and capacitors. The part is optimized for a 1-µH inductor and 10-µF
output capacitor.
10.2.2.2.1 Inductor Selection
The inductor value has a direct effect on the ripple current. The selected inductor has to be rated for its DC
resistance and saturation current. The inductor ripple current (ΔIL) decreases with higher inductance and
increases with higher VI or VO.
Equation 6 calculates the maximum inductor current in PWM mode under static load conditions. The saturation
current of the inductor must be rated higher than the maximum inductor current as calculated with Equation 7.
This is recommended because during heavy load transient, the inductor current rises above the calculated value.
V
1 - OUT
VIN
DIL = VOUT ´
L´f
where
•
•
•
ΔIL = peak-to-peak inductor ripple current
L = inductor value
f = switching frequency (3-MHz typical)
IL max = IOUT max
(6)
DI
+ L
2
where
•
ILmax = maximum inductor current
(7)
A more conservative approach is to select the inductor current rating just for the switch current limit ILIMF of the
converter.
The total losses of the coil have a strong impact on the efficiency of the DC/DC conversion and consist of both
the losses in the DC resistance R(DC) and the following frequency-dependent components:
• The losses in the core material (magnetic hysteresis loss, especially at high switching frequencies)
• Additional losses in the conductor from the skin effect (current displacement at high frequencies)
• Magnetic field losses of the neighboring windings (proximity effect)
Table 3. List of Inductors
14
INDUCTOR TYPE
INDUCTANCE (μH)
CURRENT (A)
DIMENSIONS (mm)
MANUFACTURER
XEL4020-102ME
1.0
13.25
4x4x2
Coilcraft
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Typical Application (continued)
Table 3. List of Inductors (continued)
INDUCTOR TYPE
INDUCTANCE (μH)
CURRENT (A)
DIMENSIONS (mm)
MANUFACTURER
DFE252012PD-1R0M
1.0
3.8
2.5 x 2.0 x 1.2
Murata
10.2.2.2.2 Output Capacitor Selection
The advanced fast-response voltage mode control scheme of the TPS62065-Q1 and TPS62067-Q1 allows the
use of tiny ceramic capacitors. Ceramic capacitors with low ESR values have the lowest output voltage ripple
and are recommended. The output capacitor requires either an X7R or X5R dielectric. Y5V and Z5U dielectric
capacitors, aside from their wide variation in capacitance over temperature, become resistive at high frequencies
and may not be used. For most applications, a nominal 10-µF or 22-µF capacitor is suitable. At small ceramic
capacitors, the DC-bias effect decreases the effective capacitance. Therefore, a 22-µF capacitor can be used for
output voltages higher than 2 V, see the list of capacitors.
In case additional ceramic capacitors in the supplied system are connected to the output of the DC/DC converter,
the output capacitor COUT must be decreased to not exceed the recommended effective capacitance range. In
this case, a loop stability analysis must be performed as described later.
At nominal load current, the device operates in PWM mode and the RMS ripple current is calculated as:
V
1 - OUT
VIN
1
IRMSCout = VOUT ´
´
L´f
2´ 3
(8)
10.2.2.2.3 Input Capacitor Selection
Since the buck converter has a pulsating input current, a low-ESR input capacitor is required for the best input
voltage filtering and minimizing the interference with other circuits caused by high input voltage spikes. For most
applications, a 10-µF ceramic capacitor is recommended. The input capacitor can be increased without any limit
for better input voltage filtering.
Take care when using only small ceramic input capacitors. When a ceramic capacitor is used at the input and the
power is being supplied through long wires, such as from a wall adapter, a load step at the output or VIN step on
the input can induce ringing at the VIN pin. This ringing can couple to the output and be mistaken as loop
instability or could even damage the part by exceeding the maximum ratings.
Table 4. List of Capacitors
CAPACITANCE
TYPE
SIZE [ mm3]
SUPPLIER
10 μF
GRM188R60J106M
0603: 1,6 × 0,8 × 0,8
Murata
22 μF
GRM188R60G226M
0603: 1,6 × 0,8 × 0,8
Murata
22 µF
CL10A226MQ8NRNC
0603: 1,6 × 0,8 × 0,8
Samsung
10 µF
CL10A106MQ8NRNC
0603: 1,6 × 0,8 × 0,8
Samsung
10.2.2.3 Checking Loop Stability
The first step of circuit and stability evaluation is to look from a steady-state perspective at the following signal:
• Switching node, SW
• Inductor current, IL
• Output ripple voltage, VOUT(AC)
These are the basic signals that need to be measured when evaluating a switching converter. When the
switching waveform shows large duty cycle jitter or the output voltage or inductor current shows oscillations, the
regulation loop can be unstable. This is often a result of board layout, wrong L-C output filter combinations, or
both. As a next step in the evaluation of the regulation loop, test the load transient response. The results are
most easily interpreted when the device operates in PWM mode at medium to high load currents.
During this recovery time, VOUT can be monitored for settling time, overshoot, or ringing; that helps evaluate
stability of the converter. Without any ringing, the loop has usually more than 45° of phase margin.
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10.2.3 Application Curves
Table 5. Table of Graphs
FIGURE
η
Efficiency
Output Voltage Accuracy
Typical Operation
Load Transient
Line Transient
16
Load Current, VOUT = 1.2 V, Auto PFM and PWM Mode, Linear Scale
Figure 10
Load Current, VOUT = 1.8 V, Auto PFM and PWM Mode, Linear Scale
Figure 11
Load Current, VOUT = 3.3 V, PFM and PWM Mode, Linear Scale
Figure 12
Load Current, VOUT = 1.8 V, Auto PFM and PWM Mode vs. Forced PWM
Mode, Logarithmic Scale
Figure 13
Load Current, VOUT = 1.8 V, Auto PFM and PWM Mode
Figure 14
Load Current, VOUT = 1.8 V, Forced PWM Mode
Figure 15
PWM Mode, VIN = 3.6 V, VOUT = 1.8 V, 500 mA, L = 1.2 μH, COUT = 10
μF
Figure 16
PFM Mode, VIN = 3.6 V, VOUT = 1.8 V, 20 mA, L = 1.2 μH, COUT = 10 μF
Figure 17
PWM Mode, VIN = 3.6 V, VOUT = 1.2 V, 0.2 mA to 1 A
Figure 18
PFM Mode, VIN = 3.6 V, VOUT = 1.2 V, 20 mA to 250 mA
Figure 19
VIN = 3.6 V, VOUT = 1.8 V, 200 mA to 1500 mA
Figure 20
PWM Mode, VIN = 3.6 V to 4.2 V, VOUT = 1.8 V, 500 mA
Figure 21
PFM Mode, VIN = 3.6 V to 4.2 V, VOUT = 1.8 V, 500 mA
Figure 22
Startup into Load
VIN = 3.6 V, VOUT = 1.8 V, Load = 2.2 Ω
Figure 23
Startup TPS62067-Q1
Into 2.2-Ω Load with Power Good
Figure 24
Output Discharge
VIN = 3.6 V, VOUT = 1.8 V, No Load
Figure 25
Shutdown TPS62067-Q1
VIN = 4.2 V, VOUT = 3.3 V, No Load, PG Pullup Resistor 10 kΩ
Figure 26
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95
90
90
85
85
Efficiency (%)
100
95
Efficiency (%)
100
80
75
70
65
55
50
0
0.25
0.5
0.75
1
1.25
Load Current (A)
VOUT = 1.2 V
L = 1.2 µH (NRG4026T 1R2)
1.5
1.75
70
55
50
0
2
Linear Scale
COUT = 10 µF (0603 size)
80
85
70
Efficiency (%)
90
90
Efficiency (%)
100
75
70
20
VIN = 3.7 V
VIN = 4.2 V
VIN = 5 V
0.5
0.75
1
1.25
Load Current (A)
VOUT = 3.3 V
L = 1.2 µH (NRG4026T 1R2)
1.5
1.75
0
0.001
2
Figure 12. Efficiency vs Load Current
Auto PFM and PWM MODE
1.872
1.854 Voltage Positioning PFM Mode
1.854
1.836
1.836
Output Voltage DC (V)
1.890
PWM Mode
1.800
1.782
1.764
VIN = 3.3 V
VIN = 3.6 V
VIN = 4.2 V
VIN = 5 V
1.728
1.710
0.001
L = 1 µH
0.01
0.1
Load Current (A)
1
VOUT = 1.8 V
Forced
PWM Mode
VIN = 3.3 V
VIN = 3.6 V
VIN = 4.2 V
VIN = 5 V
0.01
0.1
Load Current (A)
1.818
1.800
1.782
1.764
VIN = 3.3 V
VIN = 3.6 V
VIN = 4.2 V
VIN = 5 V
1.728
COUT = 10 µF
Figure 14. Output Voltage Accuracy vs Load Current
Auto PFM and PWM MODE
10
Logarithmic Scale
L = 1.2 µH (NRG4026T 1R2)
1.746
10
1
Figure 13. Efficiency vs Load Current
Auto PFM and PWM Mode vs. Forced PWM Mode
1.872
1.746
Auto PFM/
PWM Mode
VOUT = 1.8 V
COUT = 10 µF (0603 size)
1.890
1.818
2
Linear Scale
COUT = 10 µF (0603 size)
10
Linear Scale
COUT = 22 µF (0603 size)
1.75
40
30
0.25
1.5
50
60
0
0.75
1
1.25
Load Current (A)
60
65
50
0.5
Figure 11. Efficiency vs Load Current
PFM and PWM MODE
95
80
0.25
VOUT = 1.8 V
L = 1.2 µH (NRG4026T 1R2)
100
55
VIN = 3 V
VIN = 3.3 V
VIN = 3.6 V
VIN = 4.2 V
VIN = 5 V
60
Figure 10. Efficiency vs Load Current
Auto PFM and PWM MODE
Output Voltage DC (V)
75
65
VIN = 3 V
VIN = 3.3 V
VIN = 3.6 V
VIN = 4.2 V
VIN = 5 V
60
80
1.710
0.001
L = 1 µH
0.01
0.1
Load Current (A)
VOUT = 1.8 V
1
10
COUT = 10 µF
Figure 15. Output Voltage Accuracy vs Load Current
Forced PWM MODE
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VOUT 50 mV/Div
VOUT 50 mV/Div
SW 2 V/Div
SW 2 V/Div
ICOIL 500 mA/Div
ICOIL 200 mA/Div
Time Base - 4 µs/Div
Time Base - 100 ns/Div
VIN = 3.6 V
COUT = 10 µF
VOUT = 1.8 V
L = 1.2 µH
MODE = GND
IOUT = 500 mA
Figure 16. Typical Operation (PWM Mode)
VIN = 3.6 V
COUT = 10 µF
VOUT = 1.8 V
L = 1.2 µH
Figure 17. Typical Operation (PFM Mode)
VOUT 100 mV/Div
VOUT 100 mV/Div
SW 2 V/Div
SW 2 V/Div
ICOIL1 A/Div
ICOIL1 A/Div
ILOAD 500 mA/Div
ILOAD 500 mA/Div
Time Base - 10 µs/Div
VIN = 3.6 V
VOUT = 1.2 V
MODE = GND
IOUT = 20 mA
Time Base - 10 µs/Div
IOUT = 0.2 to 1 A
VIN = 3.6 V
VOUT = 1.8 V
Figure 18. Load Transient Response, MODE = VIN
PWM Mode 0.2 A to 1 A
VOUT
200 mV/Div
IOUT = 20 to 750 mA
Figure 19. Load Transient
PFM Mode 20 mA to 750 mA
VIN
500 mV/Div
ILOAD
2 A/Div
VOUT
50 mV/Div
IINDUCTOR
1 A/Div
Time Base - 100 µs/Div
Time Base - 100 µs/Div
VIN = 3.6 V
COUT = 10 µF
VOUT = 1.8 V
L = 1.2 µH
Figure 20. Load Transient Response
200 mA To 1500 mA
18
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VIN = 3.6 to 4.2 V
COUT = 10 µF
VOUT = 1.8 V
L = 1.2 µH
IOUT = 500 mA
Figure 21. Line Transient Response PWM Mode
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EN
2 V/Div
VIN
500 mV/Div
VOUT
1 V/Div
2 A/Div
ICOIL
500 mA/Div
VOUT
50 mV/Div
ILOAD
500 mA/Div
Time Base - 100 µs/Div
Time Base - 100 µs/Div
VIN = 3.6 to 4.2 V
COUT = 10 µF
VOUT = 1.8 V
L = 1.2 µH
IOUT = 50 mA
VIN = 3.6 V
COUT = 10 µF
Figure 22. Line Transient PFM Mode
VOUT = 1.8 V
L = 1.2 µH
Load = 2R2
Figure 23. Startup Into Load
EN
1 V/Div
EN
2 V/Div
SW
2 V/Div
VOUT
2 V/Div
VOUT
1 V/Div
ICOIL
1 A/Div
PG
2 V/Div
Time Base - 2 ms/Div
Time Base - 100 µs/Div
VIN = 4.2 V
VOUT = 3.3 V
PG Pullup resistor 10 kΩ
Load = 2R2
VIN = 3.6 V
COUT = 1.8 µF
VOUT = 1.8 V
No load
Figure 25. Output Discharge
Figure 24. Startup TPS62067-Q1 into 2.2-Ω Load With
Power Good
EN
2 V/Div
VOUT
2 V/Div
PG
5 V/Div
Time Base - 1 ms/Div
VIN = 4.2 V
VOUT = 3.3 V
PG pullup resistor, 10 kΩ
No load
Figure 26. Shutdown TPS62067-Q1
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11 Power Supply Recommendations
The power supply to the TPS62065-Q1 and TPS62067-Q1 must have a current rating according to the supply
voltage, output voltage, and output current of the TPS62065-Q1 and TPS62067-Q1.
20
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12 Layout
12.1 Layout Guidelines
As for all switching power supplies, the layout is an important step in the design. The input capacitor needs to be
placed as close as possible to the IC pins.
It is critical to provide a low inductance, impedance ground, and supply path. Therefore, use wide and short
traces for the main current paths. Connect the AGND and PGND pins of the device to the thermal pad land of
the PCB and use this pad as a star point. Use a common power PGND node and a different node for the signal
AGND to minimize the effects of ground noise. The FB divider network must be connected right to the output
capacitor and the FB line must be routed away from noisy components and traces (for example, SW line).
Due to the small package of this converter and the overall small solution size, the thermal performance of the
PCB layout is important. To get a good thermal performance, a four or more layer PCB design is recommended.
The PowerPAD of the IC must be soldered on the thermal pad area on the PCB to get a proper thermal
connection. For good thermal performance, the exposed pad on the PCB must be connected to an inner GND
plane with sufficient via connections. Refer to the documentation of the evaluation kit.
Mode/PG
Enable
12.2 Layout Example
VIN
GND
CIN
COUT
R2
R1
CFF
GND
L
VOUT
Figure 27. PCB Layout
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13 Device and Documentation Support
13.1 Device Support
13.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
13.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 6. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS62065-Q1
Click here
Click here
Click here
Click here
Click here
TPS62067-Q1
Click here
Click here
Click here
Click here
Click here
13.3 Trademarks
All trademarks are the property of their respective owners.
13.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
22
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS62065QDSGRQ1
ACTIVE
WSON
DSG
8
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
SJF
TPS62067QDSGRQ1
ACTIVE
WSON
DSG
8
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
SIP
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
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RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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