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TPS62170-Q1, TPS62171-Q1, TPS62172-Q1
SLVSCK7E – DECEMBER 2014 – REVISED MAY 2020
TPS6217x-Q1 3-V to17-V 0.5-A Step-Down Converters with DCS-Control™
1 Features
3 Description
•
•
•
The TPS6217x-Q1 family is an easy to use
synchronous step-down DC-DC converter optimized
for applications with high power density. A high
switching frequency of typically 2.25 MHz allows the
use of small inductors and provides fast transient
response as well as high output voltage accuracy by
utilization of the DCS-Control topology.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
DCS-Control™ topology
Qualified for automotive applications
AEC-Q100 qualified with the following results:
– Device temperature grade: –40°C to 125°C
operating junction temperature range
– Device HBM ESD classification level H2
– Device CDM ESD classification level C4B
Functional Safety-Capable
– Documentation available to aid functional
safety system design
Input voltage range: 3 V to 17 V
Up to 500-mA output current
Adjustable output voltage from 0.9 V to 6 V
Fixed output voltage versions
Seamless power save mode transition
Typically 17-µA quiescent current
Power-good output
100% Duty cycle mode
Short circuit protection
Overtemperature protection
Pin-to-pin compatible with TPS62160-Q1
Available in a 2 × 2 mm, WSON-8 package
Create a custom design using the TPS62170-Q1
with the WEBENCH® power designer
2 Applications
•
•
•
•
ADAS camera
Powertrain systems
Body electronics and lighting
Automotive infotainment and cluster
VIN
SW
EN
VOS
TPS62170-Q1
AGND
PG
PGND
FB
In Power Save Mode, the devices draw quiescent
current of about 17 μA from VIN. Power Save Mode,
entered automatically and seamlessly if load is small,
maintains high efficiency over the entire load range.
In Shutdown Mode, the device is turned off and
shutdown current consumption is less than 2 μA.
The device, available in adjustable and fixed output
voltage versions, is packaged in an 8-pin WSON
package measuring 2 × 2 mm (DSG).
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TPS62170-Q1
WSON (8)
2.00 mm × 2.00 mm
TPS62171-Q1
WSON (8)
2.00 mm × 2.00 mm
TPS62172-Q1
WSON (8)
2.00 mm × 2.00 mm
Efficiency versus Output Current
3.3V / 0.5A
2.2µH
C1
10uF
Power sequencing is also possible by configuring the
Enable and open-drain Power Good pins.
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Schematic
VIN
With their wide operating input voltage range of 3 V
to 17 V, the devices are ideally suited for systems
powered from either a Li-Ion or other battery as well
as from 12-V intermediate power rails. It supports up
to 0.5-A continuous output current at output voltages
between 0.9 V and 6 V (with 100% duty cycle mode).
100k
R1
470k
R2
150k
C2
22uF
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS62170-Q1, TPS62171-Q1, TPS62172-Q1
SLVSCK7E – DECEMBER 2014 – REVISED MAY 2020
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Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
4
5
7.1
7.2
7.3
7.4
7.5
7.6
5
5
5
5
6
7
Detailed Description .............................................. 8
8.1
8.2
8.3
8.4
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Overview ...................................................................
Functional Block Diagram .........................................
Feature Description...................................................
Device Functional Modes..........................................
8
8
9
9
Application and Implementation ........................ 12
9.1 Application Information............................................ 12
9.2 Typical TPS62170-Q1 Application ......................... 12
9.3 System Examples ................................................... 20
10 Power Supply Recommendations ..................... 22
11 Layout................................................................... 23
11.1 Layout Guidelines ................................................. 23
11.2 Layout Example .................................................... 23
11.3 Thermal Considerations ........................................ 23
12 Device and Documentation Support ................. 25
12.1
12.2
12.3
12.4
12.5
12.6
12.7
12.8
Device Support ....................................................
Documentation Support .......................................
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Receiving Notification of Documentation Updates
Support Resources ...............................................
Glossary ................................................................
25
25
26
26
26
26
26
26
13 Mechanical, Packaging, and Orderable
Information ........................................................... 26
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (February 2017) to Revision E
•
Page
Added functional safety bullet in the Features ...................................................................................................................... 1
Changes from Revision C (November 2016) to Revision D
Page
•
Added WEBENCH® information ............................................................................................................................................. 1
•
Changed TJ spec MAX value From 125°C To 150°C in the Absolute Maximum Ratings table............................................. 5
Changes from Revision B (October 2016) to Revision C
Page
•
Added Pin to Pin compatible feature ..................................................................................................................................... 1
•
Changed Thermal Information table ....................................................................................................................................... 5
•
Added C1, C2, R1, R2, descriptors to Figure 5.................................................................................................................... 12
•
Added C1, C2 to Table 1 ..................................................................................................................................................... 12
Changes from Revision A (September 2016) to Revision B
•
Page
Added the Device Comparison Table..................................................................................................................................... 4
Changes from Original (December 2014) to Revision A
Page
•
Changed "POE Over Coax POL Supply " To: "Power Over Coax POL Supply " in the Application list ................................ 1
•
Added TPS62171-Q1 device to data sheet............................................................................................................................ 1
•
Changed Unit from mA to V for Pin voltage at FB, PG, and VOS in the Absolute Maximum Ratings table. ........................ 5
•
Changed Unit from °C to mA in the Absolute Maximum Ratings table for Power Good sink current. .................................. 5
•
Changed Unit from kV to °C in the Absolute Maximum Ratings table for the Operating junction temperature, TJ .............. 5
2
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SLVSCK7E – DECEMBER 2014 – REVISED MAY 2020
•
Added legal NOTE at Application and Implementation ....................................................................................................... 12
•
Added cross references to Third-Party Products disclaimer in Table 1 ............................................................................... 12
Copyright © 2014–2020, Texas Instruments Incorporated
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SLVSCK7E – DECEMBER 2014 – REVISED MAY 2020
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5 Device Comparison Table
(1)
PART NUMBER (1)
OUTPUT VOLTAGE
TPS62170-Q1
Adjustable
TPS62171-Q1
1.8 V
TPS62172-Q1
3.3 V
For detailed ordering information, please check the Mechanical, Packaging, and Orderable Information
section at the end of this data sheet.
6 Pin Configuration and Functions
8-Pin WSON
DSG Package
(Top View)
PGND
1
VIN
2
EN
3
AGND
4
Exposed
Thermal
Pad
8
PG
7
SW
6
VOS
5
FB
Pin Functions
PIN
NAME
(1)
NUMBER
I/O
DESCRIPTION
PGND
1
VIN
2
I
Supply voltage
EN
3
I
Enable input (High = enabled, Low = disabled)
AGND
4
FB
5
I
Voltage feedback of adjustable version. Connect resistive voltage divider to this pin. It is recommended
to connect FB to AGND on fixed output voltage versions for improved thermal performance.
VOS
6
I
Output voltage sense pin and connection for the control loop circuitry
SW
7
O
Switch node, which is connected to the internal MOSFET switches. Connect inductor between SW and
output capacitor.
PG
8
O
Exposed
Thermal Pad
(1)
4
Power ground
Analog ground
Output power good (High = VOUT ready, Low = VOUT below nominal regulation); open drain (requires
pullup resistor; goes high impedance, when device is switched off)
Must be connected to AGND. Must be soldered to achieve appropriate power dissipation and
mechanical reliability.
For more information about connecting pins, see the Detailed Description and Application and Implementation sections.
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SLVSCK7E – DECEMBER 2014 – REVISED MAY 2020
7 Specifications
7.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted)
(1)
MIN
MAX
VIN
–0.3
20
EN
–0.3
VIN+0.3
SW
-0.3
VIN+0.3
V
FB, PG, VOS
–0.3
7
V
10
mA
Operating junction temperature range, TJ
–40
150
°C
Storage temperature range, Tstg
–65
150
°C
Pin voltage (2)
Power Good sink current
(1)
(2)
PG
UNIT
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to network ground terminal.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human body model (HBM), per AEC Q100-002
(1)
UNIT
±2000
Charged device model (CDM), per AEC Q100-011
V
±500
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
MIN
VIN
Supply voltage
VOUT
TJ
TYP
MAX
UNIT
3
17
V
Output voltage range
0.9
6
V
Operating junction temperature
–40
125
°C
7.4 Thermal Information
TPS6217x-Q1
THERMAL METRIC (1)
DSG (8 PINS)
UNIT
RθJA
Junction-to-ambient thermal resistance
65.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
66.4
°C/W
RθJB
Junction-to-board thermal resistance
35.5
°C/W
ψJT
Junction-to-top characterization parameter
1.7
°C/W
ψJB
Junction-to-board characterization parameter
35.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
8.4
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2014–2020, Texas Instruments Incorporated
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7.5 Electrical Characteristics
over junction temperature range (TJ = –40°C to +125°C), typical values at VIN = 12 V and TJ = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
VIN
Input voltage range (1)
17
V
IQ
Operating quiescent current
EN = High, IOUT = 0 mA, Device not switching
17
30
µA
ISD
Shutdown current (2)
EN = Low
1.8
25
µA
VUVLO
Undervoltage lockout threshold
2.7
2.82
3
Falling input voltage
2.6
Hysteresis
180
Thermal shutdown temperature
TSD
160
Thermal shutdown hysteresis
V
mV
°C
20
CONTROL (EN, PG)
VEN_H
High-level input threshold voltage (EN)
0.9
VEN_L
Low-level input threshold voltage (EN)
ILKG_EN
Input leakage current (EN)
VTH_PG
Power Good threshold voltage
VOL_PG
Power Good output low
IPG = –2 mA
0.07
0.3
V
ILKG_PG
Input leakage current (PG)
VPG = 1.8 V
1
400
nA
VIN ≥ 6 V
300
600
VIN = 3 V
430
VIN ≥ 6 V
120
VIN = 3 V
165
EN = VIN or GND
V
0.3
V
0.01
1
µA
Rising (%VOUT)
92%
95%
98%
Falling (%VOUT)
87%
90%
93%
POWER SWITCH
High-side MOSFET ON-resistance
RDS(ON)
Low-side MOSFET ON-resistance
High-side MOSFET forward current limit (3)
ILIMF
VIN = 12 V, TA = 25°C
0.85
1.05
200
1.35
mΩ
mΩ
A
OUTPUT
VREF
Internal reference voltage
0.8
ILKG_FB
Pin leakage current (FB)
TPS62170-Q1, VFB = 1.2 V
Output voltage range
TPS62170-Q1, VIN ≥ VOUT
PWM Mode operation, VIN ≥ VOUT + 1 V
Feedback voltage accuracy (4)
VOUT
(1)
(2)
(3)
(4)
(5)
(6)
6
5
Power Save Mode operation, COUT = 22 µF (5)
V
400
nA
0.9
6.0
V
–3%
3%
–3.5%
4%
DC output voltage load regulation
(6)
VIN = 12 V, VOUT = 3.3 V, PWM Mode operation
0.05
%/A
DC output voltage line regulation
(6)
3 V ≤ VIN ≤ 17 V, VOUT = 3.3 V, IOUT = 0.5 A,
PWM Mode operation
0.02
%/V
The device is still functional down to Under Voltage Lockout (see parameter VUVLO).
Current into VIN pin
This is the static current limit. It can be temporarily higher in applications due to internal propagation delay (see Current Limit and Short
Circuit Protection).
For fixed voltage versions, the (internal) resistive feedback divider is included.
The accuracy in Power Save Mode can be improved by increasing the COUT value, reducing the output voltage ripple.
Line and load regulation are depending on external component selection and layout (see Figure 14 and Figure 15).
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SLVSCK7E – DECEMBER 2014 – REVISED MAY 2020
7.6 Typical Characteristics
At VIN = 12 V, VOUT = 3.3 V and TJ = 25°C (unless otherwise noted)
Figure 1. Quiescent Current
Figure 2. Shutdown Current
Figure 3. High-Side Static Drain-Source-Resistance (RDSon)
Figure 4. Low-Side Static Drain-Source-Resistance (RDSon)
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8 Detailed Description
8.1 Overview
The TPS6217x-Q1 synchronous switched mode power converters are based on DCS-Control (Direct Control with
Seamless transition into power save mode), an advanced regulation topology, that combines the advantages of
hysteretic, voltage mode, and current mode control including an AC loop directly associated to the output
voltage. This control loop takes information about output voltage changes and feeds it directly to a fast
comparator stage. It sets the switching frequency, which is constant for steady state operating conditions, and
provides immediate response to dynamic load changes. To get accurate DC load regulation, a voltage feedback
loop is used. The internally compensated regulation network achieves fast and stable operation with small
external components and low ESR capacitors.
The DCS-Control™ topology supports PWM (Pulse Width Modulation) mode for medium and heavy load
conditions and a Power Save Mode at light loads. During PWM, it operates at its nominal switching frequency in
continuous conduction mode. This frequency is typically about 2.25 MHz with a controlled frequency variation
depending on the input voltage. If the load current decreases, the converter enters Power Save Mode to sustain
high efficiency down to very light loads. In Power Save Mode, the switching frequency decreases linearly with the
load current. Since DCS-Control supports both operation modes within one single building block, the transition
from PWM to Power Save Mode is seamless without affecting the output voltage.
8.2 Functional Block Diagram
PG
Soft
start
Thermal
Shtdwn
UVLO
VIN
PG control
HS lim
comp
EN*
power
control
control logic
gate
drive
SW
comp
LS lim
VOS
direct control
&
compensation
ramp
_
FB
comparator
+
timer tON
error
amplifier
DCS - ControlTM
AGND
PGND
Copyright © 2016, Texas Instruments Incorporated
*This pin is connected to a pull down resistor internally (see the Feature Description section).
8
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SLVSCK7E – DECEMBER 2014 – REVISED MAY 2020
8.3 Feature Description
8.3.1 Enable / Shutdown (EN)
When Enable (EN) is set High, the device starts operation.
Shutdown is forced if EN is pulled Low with a shutdown current of typically 1.8 µA. During shutdown, the internal
power MOSFETs as well as the entire control circuitry are turned off. The internal resistive divider pulls down the
output voltage smoothly. If the EN pin goes Low, an internal pulldown resistor of about 400 kΩ is connected and
keeps it Low in case of floating pin. To avoid ON/OFF oscillations, a minimum slew rate of about 50 mV/s is
recommended for the EN signal.
Connecting the EN pin to an appropriate output signal of another power rail provides sequencing of multiple
power rails.
8.3.2 Soft Start
The internal soft start circuitry controls the output voltage slope during start-up. This avoids excessive inrush
current and ensures a controlled output voltage rise time. It also prevents unwanted voltage drops from highimpedance power sources or batteries. When EN is set to start device operation, the device starts switching after
a delay of about 50 µs and VOUT rises with a slope of about 25 mV/µs. See Figure 26 and Figure 27 for typical
start-up operation.
The TPS6217x-Q1 can start into a pre-biased output. During monotonic pre-biased start-up, the low-side
MOSFET is not allowed to turn on until the internal ramp of the device sets an output voltage above the pre-bias
voltage.
8.3.3 Power Good (PG)
The TPS6217x-Q1 has a built-in power good (PG) function to indicate whether the output voltage has reached its
appropriate level or not. The PG signal can be used for start-up sequencing of multiple rails. The PG pin is an
open-drain output that requires a pullup resistor (to any voltage below 7 V). It can sink 2 mA of current and
maintain its specified logic low level. It is high impedance when the device is turned off due to EN, UVLO, or
thermal shutdown.
8.3.4 Undervoltage Lockout (UVLO)
If the input voltage drops, the undervoltage lockout prevents misoperation of the device by switching off both the
power FETs. The undervoltage lockout threshold is set typically to 2.7 V. The device is fully operational for
voltages above the UVLO threshold and turns off if the input voltage trips the threshold. The converter starts
operation again once the input voltage exceeds the threshold by a hysteresis of typically 180 mV.
8.3.5 Thermal Shutdown
The junction temperature (TJ) of the device is monitored by an internal temperature sensor. If TJ exceeds 160°C
(typ), the device goes into thermal shut down. Both the high-side and low-side power FETs are turned off and PG
goes high impedance. When TJ decreases below the hysteresis amount, the converter resumes normal
operation, beginning with soft start. To avoid unstable conditions, a hysteresis of typically 20°C is implemented
on the thermal shut down temperature.
8.4 Device Functional Modes
8.4.1 Pulse Width Modulation (PWM) Operation
The TPS62170-Q1 operates with pulse width modulation in continuous conduction mode (CCM) with a nominal
switching frequency of about 2.25 MHz. The frequency variation in PWM is controlled and depends on VIN, VOUT,
and the inductance. The device operates in PWM mode as long the output current is higher than half the ripple
current of the inductor. To maintain high efficiency at light loads, the device enters Power Save Mode at the
boundary to discontinuous conduction mode (DCM). This happens if the output current becomes smaller than
half the ripple current of the inductor.
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Device Functional Modes (continued)
8.4.2 Power Save Mode Operation
The built-in Power Save Mode of the TPS6217x-Q1 is entered seamlessly, if the load current decreases. This
secures a high efficiency in light load operation. The device remains in Power Save Mode as long as the inductor
current is discontinuous.
In Power Save Mode, the switching frequency decreases linearly with the load current maintaining high
efficiency. The transition in and out of Power Save Mode happens within the entire regulation scheme and is
seamless in both directions.
The TPS6217x-Q1 includes a fixed on-time circuitry. This on-time, in steady-state operation, can be estimated
as:
V
t ON = OUT × 420ns
VIN
(1)
For very small output voltages, the on-time increases beyond the result of Equation 1 to stay above an absolute
minimum on-time, tON(min), which is around 80 ns to limit switching losses. The peak inductor current in PSM can
be approximated by:
(V - VOUT )
I LPSM ( peak ) = IN
× t ON
(2)
L
When VIN decreases to typically 15% above VOUT, the TPS62170-Q1 does not enter Power Save Mode,
regardless of the load current. The device maintains output regulation in PWM mode.
8.4.3 100% Duty-Cycle Operation
The duty cycle of the buck converter is given by D = Vout / Vin and increases as the input voltage comes close
to the output voltage. In this case, the device starts 100% duty cycle operation turning on the high-side switch
100% of the time. The high-side switch stays turned on as long as the output voltage is below the internal
setpoint. This allows the conversion of small input to output voltage differences (for example, for longest
operation time of battery-powered applications). In 100% duty cycle mode, the low-side FET is switched off.
The minimum input voltage to maintain output voltage regulation, depending on the load current and the output
voltage level, can be calculated as:
VIN (min) = VOUT (min) + I OUT (RDS ( on ) + RL )
where
•
•
•
IOUT is the output current
RDS(on) is the RDS(on) of the high-side FET
RL is the DC resistance of the inductor used
(3)
8.4.4 Current Limit and Short Circuit Protection
The TPS6217x-Q1 devices are protected against heavy load and short circuit events. At heavy loads, the current
limit determines the maximum output current. If the current limit is reached, the high-side FET is turned off.
Avoiding shoot through current, the low-side FET is then switched on to allow the inductor current to decrease.
The high-side FET turns on again, only if the current in the low-side FET has decreased below the low side
current limit threshold.
The output current of the device is limited by the current limit (see the Electrical Characteristics). Due to internal
propagation delay, the actual current can exceed the static current limit during that time. The dynamic current
limit can be calculated as follows:
V
I peak ( typ ) = I LIMF + L × t PD
L
where
•
•
•
•
10
ILIMF is the static current limit, specified in the electrical characteristic table
L is the inductor value
VL is the voltage across the inductor
tPD is the internal propagation delay
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Device Functional Modes (continued)
The dynamic high side switch peak current can be calculated as follows:
(V - VOUT )
I peak ( typ ) = I LIMF _ HS + IN
× 30ns
L
(5)
Care on the current limit has to be taken if the input voltage is high and very small inductances are used.
8.4.5 Operation Above TJ = 125°C
The operating junction temperature of the device is specified up to 125°C. In power supply circuits, the self
heating effect causes the junction temperature, TJ, to be even higher than the ambient temperature TA.
Depending on TA and the load current, the maximum operating temperature TJ can be exceeded. However, the
electrical characteristics are specified up to a TJ of 125°C only. The device operates as long as thermal
shutdown threshold is not triggered.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The following information is intended to be a guideline through the individual power supply design process.
9.2 Typical TPS62170-Q1 Application
VIN
3.3V / 0.5A
2.2µH
C1
10uF
VIN
SW
EN
VOS
TPS62170-Q1
AGND
PG
PGND
FB
100k
R1
470k
C2
22uF
R2
150k
Figure 5. 3.3-V/0.5-A Power Supply
9.2.1 Design Requirements
The step-down converter design can be adapted to different output voltage and load current needs by choosing
external components appropriate. The following design procedure is adequate for whole VIN, VOUT, and load
current range of the TPS62170-Q1. Using Table 2, the design procedure needs minimum effort.
Table 1. List of Components
REFERENCE
(1)
MANUFACTURER (1)
DESCRIPTION
IC
17-V, 0.5-A step-down converter, WSON
L1
2.2-µH, 1.4-A, 3 x 2.8 x 1.2 mm
TPS62170QDSG, Texas Instruments
C1
10-µF, 25-V, ceramic
Standard
C2
22-µF, 6.3-V, ceramic
Standard
R1
Depending on Vout
R2
Depending on Vout
R3
100-kΩ, chip, 0603, 1/16-W, 1%
VLF3012ST-2R2M1R4, TDK
Standard
See Third-Party Products disclaimer.
9.2.2 Detailed Design Procedure
9.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS62170-Q1 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
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•
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Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
9.2.2.2 Programming the Output Voltage
While the output voltage of the TPS62170-Q1 is adjustable, the TPS62171-Q1 and TPS62172-Q1 are
programmed to a fixed output voltage. For fixed output versions, the FB pin is pulled down internally and can be
left floating. It is recommended to connect it to AGND to improve thermal resistance. The adjustable version can
be programmed for output voltages from 0.9 V to 6 V by using a resistive divider from VOUT to FB to AGND. The
voltage at the FB pin is regulated to 800 mV. The value of the output voltage is set by the selection of the
resistive divider from Equation 6. It is recommended to choose resistor values which allow a cross current of at
least 2 µA, meaning the value of R2 must not exceed 400 kΩ. Lower resistor values are recommended for the
highest accuracy and most robust design. For applications requiring lowest current consumption, the use of fixed
output voltage versions is recommended.
ö
æV
R1 = R 2 ç OUT - 1÷
ø
è 0.8V
(6)
In case the FB pin gets opened, the device clamps the output voltage at the VOS pin to about 7.4 V.
9.2.2.3 External Component Selection
The external components have to fulfill the needs of the application, but also the stability criteria of the devices
control loop. The TPS62170-Q1 is optimized to work within a range of external components. The LC output filters
inductance and capacitance have to be considered together, creating a double pole, responsible for the corner
frequency of the converter (see the Output Filter and Loop Stability section). Table 2 can be used to simplify the
output filter component selection.
Table 2. Recommended LC Output Filter Combinations (1)
4.7 µF
10 µF
22 µF
47 µF
100 µF
200 µF
2.2 µH
√
√ (2)
√
√
√
3.3 µH
√
√
√
√
400 µF
1 µH
4.7 µH
(1)
(2)
The values in the table are nominal values. Variations of typically ±20% due to tolerance, saturation, and DC bias are assumed.
This LC combination is the standard value and recommended for most applications.
More detailed information on further LC combinations can be found in the Optimizing the TPS62130/40/50/60
Output Filter Application Report.
9.2.2.3.1 Inductor Selection
The inductor selection is affected by several effects like inductor ripple current, output ripple voltage, PWM-toPSM transition point, and efficiency. In addition, the inductor selected has to be rated for appropriate saturation
current and DC resistance (DCR). Equation 7 and Equation 8 calculate the maximum inductor current under
static load conditions.
DI L(max)
I L(max) = I OUT (max) +
(7)
2
V
æ
ö
ç 1 - OUT ÷
ç V IN (max) ÷
DI L(max) = VOUT × ç
L
×f ÷
ç (min) SW ÷
ç
÷
è
ø
where
•
•
•
•
IL(max) is the maximum inductor current
ΔIL is the peak-to-peak inductor ripple current
L(min) is the minimum effective inductor value
fSW is the actual PWM switching frequency
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Calculating the maximum inductor current using the actual operating conditions gives the minimum saturation
current of the inductor needed. A margin of about 20% is recommended to add. A larger inductor value is also
useful to get lower ripple current, but increases the transient response time and size as well. The following
inductors have been used with the TPS62170-Q1 and are recommended for use:
Table 3. List of Inductors
(1)
(2)
TYPE
INDUCTANCE [µH]
CURRENT [A] (1)
DIMENSIONS [L x B x H] mm
MANUFACTURER (2)
VLF3012ST-2R2M1R4
2.2 µH, ±20%
1.9 A
3.0 x 2.8 x 1.2
TDK
VLF302512MT-2R2M
2.2 µH, ±20%
1.9 A
3.0 x 2.5 x 1.2
TDK
VLS252012-2R2
2.2 µH, ±20%
1.3 A
2.5 x 2.0 x 1.2
TDK
XFL3012-222MEC
2.2 µH, ±20%
1.9 A
3.0 x 3.0 x 1.2
Coilcraft
XFL3012-332MEC
3.3 µH, ±20%
1.6 A
3.0 x 3.0 x 1.2
Coilcraft
XPL2010-222MLC
2.2 µH, ±20%
1.3 A
1.9 x 2.0 x 1.0
Coilcraft
XPL2010-332MLC
3.3 µH, ±20%
1.1 A
1.9 x 2.0 x 1.0
Coilcraft
LPS3015-332ML
3.3 µH, ±20%
1.4 A
3.0 x 3.0 x 1.4
Coilcraft
PFL2512-222ME
2.2 µH, ±20%
1.0 A
2.8 x 2.3 x 1.2
Coilcraft
PFL2512-333ME
3.3 µH, ±20%
0.78 A
2.8 x 2.3 x 1.2
Coilcraft
744028003
3.3 µH, ±30%
1.0 A
2.8 x 2.8 x 1.1
Wuerth
PSI25201B-2R2MS
2.2 µH, ±20%
1.3 A
2.0 x 2.5 x 1.2
Cyntec
NR3015T-2R2M
2.2 µH, ±20%
1.5 A
3.0 x 3.0 x 1.5
Taiyo Yuden
BRC2012T2R2MD
2.2 µH, ±20%
1.0 A
2.0 x 1.25 x 1.4
Taiyo Yuden
BRC2012T3R3MD
3.3 µH, ±20%
0.87 A
2.0 x 1.25 x 1.4
Taiyo Yuden
IRMS at 40°C rise or ISAT at 30% drop.
See Third-Party Products disclaimer.
The TPS6217x-Q1 can be run with an inductor as low as 2.2 µH. However, for applications running with low
input voltages, 3.3 µH is recommended to allow the full output current. The inductor value also determines the
load current at which Power Save Mode is entered:
1
I load ( PSM ) = DI L
(9)
2
Using Equation 8, this current level can be adjusted by changing the inductor value.
9.2.2.3.2 Capacitor Selection
9.2.2.3.2.1 Output Capacitor
The recommended value for the output capacitor is 22 µF. The architecture of the TPS6217x-Q1 allows the use
of tiny ceramic output capacitors with low equivalent series resistance (ESR). These capacitors provide low
output voltage ripple and are recommended. To keep its low resistance up to high frequencies and to get narrow
capacitance variation with temperature, it's recommended to use X7R or X5R dielectric. Using a higher value can
have some advantages like smaller voltage ripple and a tighter DC output accuracy in Power Save Mode (see
the Optimizing the TPS62130/40/50/60 Output Filter Application Report).
NOTE
In Power Save Mode, the output voltage ripple depends on the output capacitance, its
ESR and the peak inductor current. Using ceramic capacitors provides small ESR and low
ripple.
9.2.2.3.2.2 Input Capacitor
For most applications, 10 µF is sufficient and is recommended, though a larger value reduces input current ripple
further. The input capacitor buffers the input voltage for transient events and also decouples the converter from
the supply. A low ESR multilayer ceramic capacitor is recommended for best filtering and should be placed
between VIN and GND as close as possible to those pins.
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NOTE
DC Bias effect: High capacitance ceramic capacitors have a DC Bias effect, which will
have a strong influence on the final effective capacitance. Therefore, the right capacitor
value has to be chosen carefully. Package size and voltage rating in combination with
dielectric material are responsible for differences between the rated capacitor value and
the effective capacitance.
9.2.2.4 Output Filter and Loop Stability
The devices of the TPS6217x-Q1 family are internally compensated to be stable with L-C filter combinations
corresponding to a corner frequency to be calculated with Equation 10:
1
f LC =
2p L × C
(10)
Proven nominal values for inductance and ceramic capacitance are given in Table 2 and are recommended for
use. Different values can work, but care has to be taken on the loop stability which might be affected. More
information including a detailed L-C stability matrix can be found in the Optimizing the TPS62130/40/50/60
Output Filter Application Report.
The TPS6217x-Q1 devices, both fixed and adjustable versions, include an internal 25-pF feedforward capacitor,
connected between the VOS and FB pins. This capacitor impacts the frequency behavior and sets a pole and
zero in the control loop with the resistors of the feedback divider, per Equation 11 and Equation 12:
1
f zero =
2p × R1 × 25 pF
(11)
f pole =
1
2p × 25 pF
æ 1
1
× çç
+
è R1 R 2
ö
÷÷
ø
(12)
Though the TPS6217x-Q1 devices are stable without the pole and zero being in a particular location, adjusting
their location to the specific needs of the application can provide better performance in Power Save mode and
improved transient response. An external feedforward capacitor can also be added. A more detailed discussion
on the optimization for stability versus transient response can be found in the Optimizing Transient Response of
Internally Compensated DC-DC Converters Application Report and Feedforward Capacitor to Improve Stability
and Bandwidth of TPS621/821-Family Application Report.
If using ceramic capacitors, the DC bias effect has to be considered. The DC bias effect results in a drop in
effective capacitance as the voltage across the capacitor increases (see the DC Bias effect note in the Input
Capacitor section).
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9.2.3 Application Curves
100.0
100.0
90.0
90.0
80.0
80.0
70.0
VIN=17V
60.0
Efficiency (%)
Efficiency (%)
At VIN = 12 V, VOUT = 3.3 V, and TJ = 25°C (unless otherwise noted)
VIN=12V
50.0
40.0
30.0
70.0
40.0
20.0
10.0
10.0
0.01
Output Current (A)
0.1
0.0
1
7
8
9
10
11
12
13
14
Input Voltage (V)
G001
Vout = 6 V
90.0
80.0
80.0
70.0
60.0
Efficiency (%)
Efficiency (%)
100.0
90.0
VIN=17V
VIN=12V
VIN=5V
VIN=17V
40.0
20.0
10.0
10.0
0.1
VIN=5V
50.0
20.0
0.01
Output Current (A)
VIN=12V
0.0
0.0001
1
0.001
0.1
1
G001
Vout = 3.3 V
Figure 8. Efficiency versus Output Current
Figure 9. Efficiency versus Input Voltage
100.0
100.0
VIN=5V
90.0
80.0
80.0
70.0
70.0
60.0
VIN=17V
50.0
40.0
VIN=12V
60.0
20.0
20.0
10.0
10.0
0.01
Output Current (A)
0.1
Vout = 1.8 V
Figure 10. Efficiency versus Output Current
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1
G001
IOUT=10mA
IOUT=100mA
40.0
30.0
0.001
IOUT=1mA
50.0
30.0
0.0
0.0001
IOUT=500mA
90.0
Efficiency (%)
Efficiency (%)
0.01
Output Current (A)
G001
Vout = 3.3 V
16
G001
60.0
30.0
0.001
17
70.0
30.0
0.0
0.0001
16
Figure 7. Efficiency versus Input Voltage
100.0
40.0
15
Vout = 6 V
Figure 6. Efficiency versus Output Current
50.0
IOUT=500mA
50.0
20.0
0.001
IOUT=100mA
IOUT=10mA
30.0
VIN=6V
0.0
0.0001
IOUT=1mA
60.0
0.0
3
4
5
6
7
8 9 10 11 12 13 14 15 16 17
Input Voltage (V)
G001
Vout = 1.8 V
Figure 11. Efficiency versus Input Voltage
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At VIN = 12 V, VOUT = 3.3 V, and TJ = 25°C (unless otherwise noted)
100.0
100.0
90.0
90.0
VIN=5V
70.0
60.0
50.0
VIN=17V
40.0
VIN=12V
30.0
50.0
IOUT=1mA
40.0
30.0
20.0
10.0
0.01
Output Current (A)
0.1
0.0
1
3
4
5
6
7
G001
Vout = 0.9 V
Figure 13. Efficiency versus Input Voltage
3.35
Output Voltage (V)
Output Voltage (V)
3.35
3.30
VIN=5V
VIN=12V
VIN=17V
3.25
3.20
0.0001
0.001
0.01
Output Current (A)
0.1
IOUT=1mA
IOUT=10mA
IOUT=100mA
IOUT=500mA
3.30
3.25
3.20
1
4
7
10
13
Input Voltage (V)
G001
Figure 14. Output Voltage Accuracy (Load Regulation)
4
4
3.5
3.5
3
2.5
2
1.5
1
0.5
16
G001
Figure 15. Output Voltage Accuracy (Line Regulation)
Switching Frequency (MHz)
Switching Frequency (MHz)
8 9 10 11 12 13 14 15 16 17
Input Voltage (V)
G001
Vout = 0.9 V
Figure 12. Efficiency versus Output Current
0
IOUT=500mA
60.0
10.0
0.001
IOUT=100mA
70.0
20.0
0.0
0.0001
IOUT=10mA
80.0
Efficiency (%)
Efficiency (%)
80.0
3
2.5
2
IOUT=0.5A
1.5
1
0.5
0
0.1
0.2
0.3
Output Current (A)
0.4
0.5
G000
Figure 16. Switching Frequency versus Output Current
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0
4
6
8
10
12
Input Voltage (V)
14
16
18
G000
Figure 17. Switching Frequency versus Input Voltage
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At VIN = 12 V, VOUT = 3.3 V, and TJ = 25°C (unless otherwise noted)
1.5
0.04
1.2
VIN=17V
Output Current (A)
Output Voltage Ripple (V)
0.05
0.03
0.02
VIN=12V
0.01
−40°C
1
25°C
0.8
0.5
85°C
0.2
VIN=5V
0
0
0.1
0.2
0.3
Output Current (A)
0.4
0.5
G000
4
5
6
7
8
9 10 11 12 13 14 15 16 17
Input Voltage (V)
G000
Figure 18. Output Voltage Ripple
Figure 19. Maximum Output Current
Figure 20. PWM / PSM Mode Transition
Figure 21. PWM to PSM Mode Transition
200 mA to 500 mA
Figure 22. Load Transient Response in PWM Mode
18
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100 mA to 500 mA
Figure 23. Load Transient Response from Power Save
Mode
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At VIN = 12 V, VOUT = 3.3 V, and TJ = 25°C (unless otherwise noted)
200 mA to 500 mA
Figure 24. Load Transient Response in PWM Mode, Rising
Edge
Iout = 100 mA
Figure 26. Start-up to VOUT = 3.3 V
Iout = 66 mA
Figure 28. Typical Operation in Power Save Mode
Copyright © 2014–2020, Texas Instruments Incorporated
200 mA to 500 mA
Figure 25. Load Transient Response in PWM Mode, Falling
Edge
Iout = 500 mA
Figure 27. Start-up to VOUT = 3.3 V
Iout = 500 mA
Figure 29. Typical Operation in PWM Mode
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9.3 System Examples
9.3.1 Inverting Power Supply
The TPS62170-Q1 can be used as inverting power supply by rearranging external circuitry as shown in
Figure 30. Since the former GND node now represents a voltage level below system ground, the voltage
difference between VIN and VOUT has to be limited for operation to the maximum supply voltage of 17 V (see
Equation 13).
VIN + VOUT £ VIN max
(13)
10uF
2.2µH
VIN
SW
EN
10uF
VOS
680k
100k
TPS62170-Q1
22uF
GND
PG
PGND
FB
130k
-5V
Figure 30. –5-V Inverting Power Supply
The transfer function of the inverting power supply configuration differs from the buck mode transfer function,
incorporating a Right Half Plane Zero additionally. The loop stability has to be adapted and an output
capacitance of at least 22 µF is recommended. A detailed design example is given in the Using the TPS6215x in
an Inverting Buck-Boost Topology Application Report.
9.3.2 Various Output Voltages
The TPS62170-Q1 can be set for different output voltages between 0.9 V and 6 V. Some examples are shown
below.
(5 .. 17)V
5V / 0.5A
2.2µH
10uF
VIN
SW
EN
VOS
TPS62170-Q1
AGND
PG
PGND
FB
100k
680k
22uF
130k
Figure 31. 5-V/0.5-A Power Supply
(3.3 .. 17)V
3.3V / 0.5A
2.2µH
10uF
VIN
SW
EN
VOS
TPS62170-Q1
AGND
PG
PGND
FB
100k
470k
22uF
150k
Figure 32. 3.3-V/0.5-A Power Supply
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System Examples (continued)
(3 .. 17)V
10uF
2.5V / 0.5A
2.2µH
VIN
SW
EN
VOS
TPS62170-Q1
AGND
PG
PGND
FB
100k
390k
22uF
180k
Figure 33. 2.5-V/0.5-A Power Supply
(3 .. 17)V
10uF
1.8V / 0.5A
2.2µH
VIN
SW
EN
VOS
TPS62170-Q1
AGND
PG
PGND
FB
100k
200k
22uF
160k
Figure 34. 1.8-V/0.5-A Power Supply
(3 .. 17)V
10uF
1.5V / 0.5A
2.2µH
VIN
SW
EN
VOS
TPS62170-Q1
AGND
PG
PGND
FB
100k
130k
22uF
150k
Figure 35. 1.5-V/0.5-A Power Supply
(3 .. 17)V
10uF
1.2V / 0.5A
2.2µH
VIN
SW
EN
VOS
TPS62170-Q1
AGND
PG
PGND
FB
100k
75k
22uF
150k
Figure 36. 1.2-V/0.5-A Power Supply
(3 .. 17)V
10uF
1V / 0.5A
2.2µH
VIN
SW
EN
VOS
TPS62170-Q1
AGND
PG
PGND
FB
100k
51k
22uF
200k
Figure 37. 1-V/0.5-A Power Supply
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10 Power Supply Recommendations
The TPS6217x-Q1 are designed to operate from a 3-V to 17-V input voltage supply. The output current of the
input power supply needs to be rated according to the output voltage and the output current of the power rail
application.
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11 Layout
11.1 Layout Guidelines
A proper layout is critical for the operation of a switched mode power supply, even more at high switching
frequencies. Therefore, the PCB layout of the TPS6217x-Q1 demands careful attention to ensure operation and
to get the performance specified. A poor layout can lead to issues like poor regulation (both line and load),
stability and accuracy weaknesses, increased EMI radiation, and noise sensitivity. Considering the following
topics ensures best electrical and optimized thermal performance:
1. The input capacitor must be placed as close as possible to the VIN and PGND pin of the IC. This provides
low resistive and inductive path for the high di/dt input current.
2. The VOS pin must be connect in the shortest way to VOUT at the output capacitor, avoiding noise coupling.
3. The feedback resistors, R1 and R2 must be connected close to the FB and AGND pins, avoiding noise
coupling.
4. The output capacitor mst be placed such that its ground is as close as possible to the PGND pins of the IC,
avoiding additional voltage drop in traces.
5. The inductor must be placed close to the SW pin and connect directly to the output capacitor, minimizing the
loop area between the SW pin, inductor, output capacitor, and PGND pin.
More detailed information can be found in the TPS62160EVM-627 and TPS62170EVM-627 Evaluation Modules
User's Guide.
The Exposed Thermal Pad must be soldered to the circuit board for mechanical reliability and to achieve
appropriate power dissipation. Although the Exposed Thermal Pad can be connected to a floating circuit board
trace, the device will have better thermal performance if it is connected to a larger ground plane. The Exposed
Thermal Pad is electrically connected to AGND.
11.2 Layout Example
GND
VOUT
C2
L1
PG
PGND
C1
VIN
SW
EN
VOS
AGND
FB
AGND
VIN
R2
R1
Figure 38. Layout Example
11.3 Thermal Considerations
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the powerdissipation limits of a given component.
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Thermal Considerations (continued)
The following are three basic approaches for enhancing thermal performance:
• Improving the power dissipation capability of the PCB design
• Improving the thermal coupling of the component to the PCB by soldering the Exposed Thermal Pad
• Introducing airflow in the system
For more details on how to use the thermal parameters, see the Thermal Characteristics of Linear and Logic
Packages Using JEDEC PCB Designs Application Report and Semiconductor and IC Package Thermal Metrics
Application Report.
The TPS6217x-Q1 are designed for a maximum operating junction temperature (TJ) of 125°C. Therefore, the
maximum output power is limited by the power losses that can be dissipated over the actual thermal resistance,
given by the package and the surrounding PCB structures. Since the thermal resistance of the package is fixed,
increasing the size of the surrounding copper area and improving the thermal connection to the IC can reduce
the thermal resistance. To get an improved thermal behavior, it is recommended to use top layer metal to
connect the device with wide and thick metal lines. Internal ground layers can connect to vias directly under the
IC for improved thermal performance.
If short circuit or overload conditions are present, the device is protected by limiting internal power dissipation.
24
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Product Folder Links: TPS62170-Q1 TPS62171-Q1 TPS62172-Q1
TPS62170-Q1, TPS62171-Q1, TPS62172-Q1
www.ti.com
SLVSCK7E – DECEMBER 2014 – REVISED MAY 2020
12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
12.1.1.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS62170-Q1 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
12.1.2 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Documentation Support
12.2.1 Related Documentation
• Optimizing the TPS62130/40/50/60/70 Output Filter Application Report
• Optimizing Transient Response of Internally Compensated dc-dc Converters With Feedforward Capacitor
Application Report\
• Using a Feedforward Capacitor to Improve Stability and Bandwidth of TPS62130/40/50/60/70 Application
Report
• Using the TPS6215x in an Inverting Buck-Boost Topology Application Report
• TPS62160EVM-627 and TPS62170EVM-627 Evaluation Modules User's Guide
• Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs Application Report
• Semiconductor and IC Package Thermal Metrics Application Report
Copyright © 2014–2020, Texas Instruments Incorporated
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12.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 4. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS62170-Q1
Click here
Click here
Click here
Click here
Click here
TPS62171-Q1
Click here
Click here
Click here
Click here
Click here
TPS62172-Q1
Click here
Click here
Click here
Click here
Click here
12.4 Trademarks
DCS-Control, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.7 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
26
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Product Folder Links: TPS62170-Q1 TPS62171-Q1 TPS62172-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS62170QDSGRQ1
ACTIVE
WSON
DSG
8
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
QUEQ
TPS62170QDSGTQ1
ACTIVE
WSON
DSG
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
QUEQ
TPS62171QDSGRQ1
ACTIVE
WSON
DSG
8
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
QUFQ
TPS62171QDSGTQ1
ACTIVE
WSON
DSG
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
QUFQ
TPS62172QDSGRQ1
ACTIVE
WSON
DSG
8
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
QUGQ
TPS62172QDSGTQ1
ACTIVE
WSON
DSG
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
QUGQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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