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TPS63050RMWT

TPS63050RMWT

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    VQFN12

  • 描述:

    IC REG BCK BST ADJ 500MA 12VQFN

  • 数据手册
  • 价格&库存
TPS63050RMWT 数据手册
Order Now Product Folder Technical Documents Support & Community Tools & Software TPS63050, TPS63051 SLVSAM8D – JULY 2013 – REVISED AUGUST 2019 TPS6305x Single Inductor Buck-Boost With 1-A Switches and Adjustable Soft Start 1 Features 3 Description • The TPS6305x family of devices is a high efficiency, low quiescent-current buck-boost converter, suitable for applications where the input voltage is higher or lower than the output. Real buck or boost with seamless transition between buck and boost mode 2.5 V to 5.5 V Input voltage range 0.5-A Continuous output current: VIN ≥ 2.5 V, VOUT = 3.3 V Adjustable and fixed output voltage version Efficiency > 90% in boost mode and > 95% in buck mode 2.5-MHz Typical switching frequency Adjustable average input current limit Adjustable soft-start time Device quiescent current < 60 μA Automatic power save mode or forced PWM mode Load disconnect during shutdown Overtemperature protection Small 1.6mm x 1.2mm, 12-pin WCSP and 2.5mm x 2.5mm 12-pin HotRod™ QFN package Create a custom design using the: – TPS63050 With the WEBENCH® Power Designer – TPS63051 With the WEBENCH® Power Designer 1 • • • • • • • • • • • • • 2 Applications • • • • • Cellular and smart phones Tablets PC PC and smart phone accessories Battery powered applications Smart grid/smart meter Continuous output current can go as high as 500 mA in boost mode and as high as 1 A in buck mode. The maximum average current in the switches is limited to a typical value of 1 A. The TPS6305x family of devices regulate the output voltage over the complete input voltage range by automatically switching between buck or boost mode depending on the input voltage, ensuring seamless transition between modes. The buck-boost converter is based on a fixedfrequency, pulse-width-modulation (PWM) controller using synchronous rectification to obtain the highest efficiency. At low load currents, the converter enters Power Save Mode to maintain high efficiency over the complete load current range. The PFM/PWM pin allows the user to select between automatic-PFM/PWM mode operation and forcedPWM operation. During PWM mode a fixed-frequency of typically 2.5 MHz is used. The output voltage is programmable using an external resistor divider, or is fixed internally on the chip. The converter can be disabled to minimize battery drain. During shutdown, the load is disconnected from the battery. The device is packaged in a 12-pin DSBGA and in a 12-pin HotRod package. Device Information(1) PART NUMBER TPS63050 TPS63051 PACKAGE BODY SIZE (NOM) DSBGA (12) 1.56 mm x 1.16 mm VQFN (12) 2.50 mm × 2.50 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Simplified Schematic (WCSP) Efficiency vs Output Current L1 1.5 µH TPS63051 VIN C1 L2 VIN VOUT EN FB ILIM0 PG PFM/ PWM ILIM1 GND SS 3.3 V / 500mA R2 1MΩ 10µF VIH or VIL VIH or VIL C3 C2 C3 10µF 10µF VOUT Efficiency (%) L1 2.5 V to 5.5 V 1nF VIN = 2.8V, V OUT = 3.3V VIN = 3.6V, V OUT = 3.3V TPS63051 Output Current (mA) 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS63050, TPS63051 SLVSAM8D – JULY 2013 – REVISED AUGUST 2019 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Comparison Table..................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 4 4 5 7.1 7.2 7.3 7.4 7.5 7.6 7.7 5 5 5 5 6 7 8 Absolute Maximum Ratings ...................................... ESD Ratings ............................................................ Recommended Operating Conditions....................... Thermal Information ................................................. Electrical Characteristics........................................... Switching Characteristics .......................................... Typical Characteristics .............................................. Detailed Description .............................................. 9 8.1 8.2 8.3 8.4 Overview ................................................................... 9 Functional Block Diagrams ....................................... 9 Feature Description................................................. 11 Device Functional Modes........................................ 12 9 Application and Implementation ........................ 15 9.1 Application Information............................................ 15 9.2 Typical Application ................................................. 15 10 Power Supply Recommendations ..................... 23 11 Layout................................................................... 23 11.1 11.2 11.3 11.4 Layout Guidelines ................................................. Layout Example (WCSP) ...................................... Layout Example (HotRod)..................................... Thermal Considerations ........................................ 23 23 23 24 12 Device and Documentation Support ................. 24 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 Custom Design With WEBENCH® Tools ............. Device Support .................................................... Related Links ........................................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 24 24 24 25 25 25 25 25 13 Mechanical, Packaging, and Orderable Information ........................................................... 25 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (July 2015) to Revision D Page • Added Webench links to the data sheet................................................................................................................................. 1 • Changed the Pin Configurations............................................................................................................................................. 4 • Changed the quiescent current VIN max value From: 60 µA To: 65 µA in the Electrical Characteristics ............................. 6 • Added Note: Conditions: TJ = –40°C to 85°C To the quiescent current and shutdown current in the Electrical Characteristics ........................................................................................................................................................................ 6 Changes from Revision B (April 2015) to Revision C Page • Added new package option to Features................................................................................................................................. 1 • Added VQFN package to Device Information table .............................................................................................................. 1 • Added HotRod Pin Configuration and Functions ................................................................................................................... 4 • Added Parameter Measurement Circuit for HotRod package option ................................................................................... 15 Changes from Revision A (February 2014) to Revision B Page • Changed Description section ................................................................................................................................................. 1 • Changed graphic image ........................................................................................................................................................ 1 • Changed Ordering Information table To:Device Comparison Table ..................................................................................... 4 • Changed "Handling Ratings" table to "ESD Rating" table and moved Tstg spec to the Absolute Maximum Ratings table.... 5 • Moved some Typical Characteristics graphs to the Application Curves section ................................................................... 8 2 Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated Product Folder Links: TPS63050 TPS63051 TPS63050, TPS63051 www.ti.com SLVSAM8D – JULY 2013 – REVISED AUGUST 2019 Changes from Original (July 2013) to Revision A Page • Added Device Information and ESD Rating tables, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ..................................... 1 • Added TPS63050 device specifications and description throughout data sheet .................................................................. 1 • Changed Figure 34, PCB Layout ........................................................................................................................................ 23 • Changed Figure 35, PCB Layout ........................................................................................................................................ 23 Copyright © 2013–2019, Texas Instruments Incorporated Product Folder Links: TPS63050 TPS63051 Submit Documentation Feedback 3 TPS63050, TPS63051 SLVSAM8D – JULY 2013 – REVISED AUGUST 2019 www.ti.com 5 Device Comparison Table PART NUMBER (1) (1) VOUT TPS63050 Adjustable TPS63051 3.3 V For all available packages, see the orderable addendum at the end of the datasheet 6 Pin Configuration and Functions YFF Package 12-Pin DSBGA Top View L1 VIN EN L1 ILIM0 GND 2 9 GND L2 3 8 PG VOUT 4 7 SS ILIM1 L2 PFM/PWM PG FB C D VOUT 6 ILIM0 10 FB SS PFM/PWM GND 1 5 B EN 3 11 2 VIN 1 12 A RMW Package 12-Pin HotRod Top View No t to scale No t to scale Pin Functions PIN NAME I/O DESCRIPTION WCSP HotRod EN A3 11 I Enable input. (1 enabled, 0 disabled). It must not be left floating FB D2 5 I Voltage feedback of adjustable versions, must be connected to VOUT on fixed output voltage versions1 GND B1 2,9 ILIM0 B2 10 ILIM1 B3 See L1 A1 1 Connection for Inductor L2 C1 3 Connection for Inductor PFM/PWM C2 6 I 0 for PFM mode 1 for forced PWM mode. It must not be left floating PG C3 8 O Power good open drain output SS D3 7 I Adjustable Soft-Start. If left floating default soft-start time is set VIN A2 12 I Supply voltage for power stage and control stage VOUT D1 4 O Buck-boost converter output (1) 4 Ground for Power stage and Control stage I (1) I Programmable inrush current limit input works together with lLIM1. See table on page 1. It must not be left floating Programmable inrush current limit input works together with lLIM0. See Efficiency vs Output Current on page 1. Do not leave floating Only available with DSBGA package, for VQFN package ILIM1 is internally connected to voltage level > VIH Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated Product Folder Links: TPS63050 TPS63051 TPS63050, TPS63051 www.ti.com SLVSAM8D – JULY 2013 – REVISED AUGUST 2019 7 Specifications 7.1 Absolute Maximum Ratings over junction temperature range (unless otherwise noted) (1) MIN MAX VIN, L1, EN, VOUT, FB, VINA, PFM/PWM –0.3 7 L2 (3) –0.3 7 L2 (4) –0.3 9.5 Operating junction temperature, TJ –40 150 °C Operating ambient temperature, TA –40 85 °C Storage temperature, Tstg –65 150 °C Voltage (2) (1) (2) (3) (4) UNIT V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground pin. DC voltage rating. AC voltage rating. 7.2 ESD Ratings VALUE Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 V(ESD) (1) (2) Electrostatic discharge (1) UNIT ±1500 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) V ±700 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions (1) See VIN Input voltage IOUT Output current (2) MIN NOM MAX 2.5 5.5 V 0.5 A 2.2 µH L Inductance COUT Output capacitance (3) TA Operating ambient temperature –40 85 °C TJ Operating virtual junction temperature –40 125 °C (1) (2) (3) 1 1.5 UNIT 10 µF Refer to the Application Information section for further information Effective inductance value at operating condition. The nominal value given matches a typical inductor to be chosen to meet the inductance required. Due to the DC bias effect of ceramic capacitors, the effective capacitance is lower then the nominal value when a voltage is applied. This is why the capacitance is specified to allow the selection of the nominal capacitor required with the DC bias effect for this type of capacitor. The nominal value given matches a typical capacitor to be chosen to meet the minimum capacitance required. 7.4 Thermal Information TPS6305x THERMAL METRIC (1) WCSP RMW UNIT 12 PINS 12 PINS RθJA Junction-to-ambient thermal resistance 89.9 37.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 0.7 30.4 °C/W RθJB Junction-to-board thermal resistance 43.9 8.0 °C/W ψJT Junction-to-top characterization parameter 2.9 0.4 °C/W ψJB Junction-to-board characterization parameter 43.7 7.8 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance n/a 2.5 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Copyright © 2013–2019, Texas Instruments Incorporated Product Folder Links: TPS63050 TPS63051 Submit Documentation Feedback 5 TPS63050, TPS63051 SLVSAM8D – JULY 2013 – REVISED AUGUST 2019 www.ti.com 7.5 Electrical Characteristics VIN = 3.6 V, TJ = –40°C to 125°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VIN Input voltage range VIN_Min Minimum input voltage to turn on in full load IOUT = 500 mA 2.7 V IOUT Output current (1) ILIM0 = VIH, ILIM1 = VIH, 500 mA IQ 2.5 VIN IOUT = 0 mA, EN = VIN = 3.6 V, VOUT = 3.3 V VOUT IOUT = 0 mA, EN = VIN = 3.6 V, VOUT = 3.3 V (2) Quiescent current (2) Isd Shutdown current UVLOTH Undervoltage lockout threshold UVLOhys Undervoltage lockout hysteresis TSD Thermal shutdown TSD(hys) Thermal shutdown hysteresis 43 V 65 μA 10 EN = 0 V VIN falling 5.5 1.6 Temperature rising 0.1 1 1.7 1.8 μA V 200 mV 140 °C 20 °C LOGIC SIGNALS EN, ILIM0, ILIM1 VIH High level input voltage VIN = 2.5 V to 5.5 V VIL Low level voltage Input Voltage VIN = 2.5 V to 5.5 V Input leakage current PFM / PWM, EN, ILIM0, ILIM1 = GND or VIN Ilkg 1.2 V 0.01 0.3 V 0.1 μA POWER GOOD VOL Low level voltage Isink = 100 μA 0.3 V IPG PG sinking current V = 0.3 V 0.1 mA Ilkg Input leakage current VPG = 3.6 V 0.1 μA 5.5 V 0.01 OUTPUT VOUT Output voltage range 2.5 VFB TPS63050 feedback regulation voltage VFB TPS63050 feedback voltage accuracy PWM mode VFB TPS63050 feedback voltage accuracy (3) PFM mode –1% VOUT TPS63051 output voltage accuracy PWM mode 3.27 PFM mode 3.27 (3) 0.8 –1.1% V 1.1% 3% 3.3 3.34 3.3 3.39 V VOUT TPS63051 output voltage accuracy IPWM->PFM Minimum output current to enter PFM mode VIN = 3 V; VOUT = 3.3 V IFB TPS63050 feedback input bias current VFB = 0.8 V Input high-side FET on-resistance ISW = 500 mA 145 mΩ Output high-side FET on-resistance ISW = 500 mA 95 mΩ Input low-side FET on-resistance ISW = 500 mA 170 mΩ Output low-side FET on-resistance ISW = 500 mA 115 mΩ RDS(on) IIN_MAX (1) (2) (3) 6 Input current-limit boost mode 150 10 V mA 100 nA ILIM0 = VIH, ILIM1 = VIH,VIN = 2.7 V to 3 V, VOUT = 3 V 480 1240 mA ILIM0 = VIH, ILIM1 = VIH,VIN = 2.7 V to 3.3 V, VOUT = 3.3 V, 550 1400 mA ILIM0 = VIH, ILIM1 = VIH,VIN = 2.7 V to 4.5 V, VOUT = 4.5 V, 630 1950 mA For minimum and maximum output current in a specific working point see Figure 1 and Figure 2; and Equation 1 through Equation 4. Conditions: TJ = –40°C to 85°C Conditions: f = 2.5 MHz, L = 1.5 µH, COUT = 10 µF Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated Product Folder Links: TPS63050 TPS63051 TPS63050, TPS63051 www.ti.com SLVSAM8D – JULY 2013 – REVISED AUGUST 2019 Electrical Characteristics (continued) VIN = 3.6 V, TJ = –40°C to 125°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER ISS_IN Programmable inrush current limit (4) ISS Soft-start current TPS63051 ISS Soft-start current TPS63050 (4) TEST CONDITIONS MIN TYP MAX ILIM0 = VIL, ILIM1 = VIL, VIN = 3 V,VOUT = 3.3 V, (Available for DBGA only) 0.4×IIN_MAX ILIM0 = VIH, ILIM1 = VIL, VIN = 3 V,VOUT = 3.3 V, (Available for DBGA only) 0.5×IIN_MAX ILIM0 = VIL, ILIM1 = VIH, VIN = 3 V,VOUT = 3.3 V 0.65×IIN_MAX ILIM0 = VIH, ILIM1 = VIH, VIN = 3 V,VOUT = 3.3 V IIN_MAX UNIT mA 1 μA 3.2 μA Line regulation VIN = 2.5 V to 5.5 V, IOUT = 500 mA, PWM mode 0.963 mV/V Load regulation VIN = 3.6 V, IOUT = 0 mA to 500 mA, PWM mode 4 mV/A For variation of this parameter with Input voltage see Figure 3. 7.6 Switching Characteristics VIN = 3.6 V, TJ = –40°C to 125°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OUTPUT fs tSS td (1) Switching frequency 2.5 Softstart time Start up delay VOUT = EN = low to high, SS = floating, Buck mode VIN = 3.6 V, VOUT = 3.3 V, IOUT = 500 mA (1) 280 VOUT = EN = low to high, SS = floating, Boost mode VIN = 2.5 V, VOUT = 3.3 V, IOUT = 500 mA (1) 600 Time from when EN = high to when device starts switching 100 MHz µs µs For variation of this parameter with Input voltage see Figure 3. Copyright © 2013–2019, Texas Instruments Incorporated Product Folder Links: TPS63050 TPS63051 Submit Documentation Feedback 7 TPS63050, TPS63051 SLVSAM8D – JULY 2013 – REVISED AUGUST 2019 www.ti.com TPS63051 TPS63051 TA = -40 °C TA = 25 °C TA = 85 °C TA = -40 °C TA = 25 °C TA = 85 °C Minimum Average Input Current (A) Maximum Average Input Current (A) 7.7 Typical Characteristics Input Voltage (V) Input Voltage (V) VOUT = 3.3 V VOUT = 3.3 V Figure 1. Maximum Average Input Current vs Input Voltage Figure 2. Minimum Average Input Current vs Input Voltage Soft Start programmable Average Input Current (A) TPS63051 ILM0 = VIL, ILM1 = VIL ILM0 = VIH, ILM1 = VIL ILM0 = VIL, ILM1 = VIH Input Voltage (V) Figure 3. Programmable Average Input Current vs Input Voltage (1) (1) 8 All options only available with the DSBGA package. For VQFN package ILIM1 is internally connected to voltage level > VIH Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated Product Folder Links: TPS63050 TPS63051 TPS63050, TPS63051 www.ti.com SLVSAM8D – JULY 2013 – REVISED AUGUST 2019 8 Detailed Description 8.1 Overview The TPS6305x devices use 4 internal N-channel MOSFETs to maintain synchronous power conversion at all possible operating conditions. This enables the device to keep high efficiency over the complete input voltage and output power range. To regulate the output voltage at all possible input voltage conditions, the device automatically switches from buck operation to boost operation and back as required by the configuration. It always uses one active switch, one rectifying switch, one switch held on, and one switch held off. Therefore, it operates as a buck converter when the input voltage is higher than the output voltage, and as a boost converter when the input voltage is lower than the output voltage. There is no mode of operation in which all 4 switches are switching at the same time. Keeping one switch on and one switch off eliminates their switching losses. The RMS current through the switches and the inductor is kept at a minimum, to minimize switching and conduction losses. Controlling the switches this way allows the converter to always keep higher efficiency. The device provides a seamless transition from buck to boost or from boost to buck operation. 8.2 Functional Block Diagrams L1 L2 VIN VOUT Current Sensor VIN VOUT GND Gate Control _ Modulator SS ILIM1 ILIM0 PG PFM/PWM + Oscillator Device Control EN GND _ FB + + - Temperature Control GND VREF GND GND Figure 4. TPS63050 Block Diagram Copyright © 2013–2019, Texas Instruments Incorporated Product Folder Links: TPS63050 TPS63051 Submit Documentation Feedback 9 TPS63050, TPS63051 SLVSAM8D – JULY 2013 – REVISED AUGUST 2019 www.ti.com Functional Block Diagrams (continued) L1 L2 VIN VOUT Current Sensor VIN VOUT GND GND Gate Control FB _ Modulator SS ILIM1 ILIM0 PG PFM/PWM _ + + Oscillator + - Device Control EN VREF Temperature Control GND GND GND Figure 5. TPS63051 Block Diagram 10 Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated Product Folder Links: TPS63050 TPS63051 TPS63050, TPS63051 www.ti.com SLVSAM8D – JULY 2013 – REVISED AUGUST 2019 8.3 Feature Description 8.3.1 Power Good The TPS6305x devices have a PG output. The power good goes high impedance once the output is above 95% of the nominal voltage, and is driven low once the output voltage falls below typically 90% of the nominal voltage. The PG pin is an open drain output and is specified to sink up to 0.1 mA. The power good output requires a pullup resistor connecting to any voltage rail less than 5.5 V. The power good is valid as long as the converter is enabled and VIN is present. The power good goes low when the device is in undervoltage lockout, in thermal shutdown or in current limit. If EN is pulled low and one of the pins ILIM0 or ILIM1 is high, then the PG pin is low. If both pins, ILIM0 and ILIM1 are low, the PG is open drain. In this case the PG pin, follows its pullup voltage. If this is not desired, one of the two pins ILIM0 or ILIM1, must be set high. Table 1 lists the PG pin functionality. Table 1. Power Good Settings EN ILIM1 ILIM0 PG 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 Open Drain 8.3.2 Overvoltage Protection Overvoltage protection is implemented to limit the maximum output voltage. In case of overvoltage condition, the voltage amplifier regulates the output voltage to typically 6.7 V. 8.3.3 Undervoltage Lockout (UVLO) To avoid mis-operation of the device at low input voltages, an undervoltage lockout is included. UVLO shuts down the device at input voltages lower than typically 1.7 V with a 200-mV hysteresis. 8.3.4 Thermal Shutdown The device goes into thermal shutdown once the junction temperature exceeds typically 140°C with a 20°C hysteresis. 8.3.5 Soft Start To minimize inrush current and output voltage overshoot during start up, the device has a soft start. At turn on, the input current raises monotonically until the output voltage reaches regulation. The TPS6305x devices charge the soft start capacitor, at the SS pin, with a constant current of typically 1 µA. The input current follows the current used to charge the capacitor at the SS pin. The soft start operation is completed once the voltage at the SS pin has reached typically 1.3 V. Figure 3 shows the value of the soft start capacitor in respect to the soft-start time. The soft-start time is the time from when the EN pin is asserted to when the output voltage has reached 90% of its nominal value. There is typically a 100-µs delay time from EN pin assertion to the start of the switching activity. The soft-start time depends on the load current, the input voltage, and the output capacitor. The soft-start time in boost mode is longer then the time in buck mode and it also depends on the load current, input voltage and output capacitor. The soft-start time in Figure 3 is referred to typical application with 10-µF effective output capacitance. The inductor current is able to increase and always assure a soft start unless a real short circuit is applied at the output. 8.3.6 Short Circuit Protection The TPS6305x devices provide short circuit protection. When the output voltage does not increase above 1.2 V, a short circuit is detected and the output current is limited to 1.5 A. Copyright © 2013–2019, Texas Instruments Incorporated Product Folder Links: TPS63050 TPS63051 Submit Documentation Feedback 11 TPS63050, TPS63051 SLVSAM8D – JULY 2013 – REVISED AUGUST 2019 www.ti.com 8.4 Device Functional Modes 8.4.1 Control Loop Description 0.8V Ramp and Clock Generator Figure 6. Average Current Mode Control The controller circuit of the device is based on an average current mode topology. The average inductor current is regulated by a fast current regulator loop which is controlled by a voltage control loop. Figure 6 shows the control loop. The noninverting input of the transconductance amplifier, gmv, is assumed to be constant. The output of gmv defines the average inductor current. The inductor current is reconstructed by measuring the current through the high side buck MOSFET. This current corresponds exactly to the inductor current in boost mode. In buck mode the current is measured during the on time of the same MOSFET. During the off time, the current is reconstructed internally starting from the peak value at the end of the on time cycle. The average current and the feedback from the error amplifier gmv forms the correction signal gmc. This correction signal is compared to the buck and the boost sawtooth ramp giving the PWM signal. Depending on which of the two ramps the gmc output crosses either the Buck or the Boost stage is initiated. When the input voltage is close to the output voltage, one buck cycle is always followed by a boost cycle. In this condition, no more than three cycles in a row of the same mode are allowed. This control method in the buck-boost region ensures a robust control and the highest efficiency. 12 Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated Product Folder Links: TPS63050 TPS63051 TPS63050, TPS63051 www.ti.com SLVSAM8D – JULY 2013 – REVISED AUGUST 2019 Device Functional Modes (continued) 8.4.2 Power Save Mode Operation Heavy Load transient step PFM mode at light load current Comparator High 30mV ripple Vo+1.3%*Vo Comparator low Vo PWM mode Absolute Voltage drop with positioning Figure 7. Power Save Mode Operation Depending on the load current, the device works in PWM mode at load currents of approximately 350 mA or higher to provide the best efficiency over the complete load range. At lighter loads, the device switches automatically into Power Save Mode to reduce power consumption and extend battery life. The PFM/PWM pin is used to select between the two different operation modes. To enable Power Save Mode, the PFM/PWM pin must be set low. During Power Save Mode, the part operates with a reduced switching frequency and lowest supply current to maintain high efficiency. The output voltage is monitored with a comparator at every clock cycle by the thresholds comp low and comp high. When the device enters Power Save Mode, the converter stops operating and the output voltage drops. The slope of the output voltage depends on the load and the output capacitance. When the output voltage reaches the comp low threshold, at the next clock cycle the device ramps up the output voltage again, by starting operation. Operation can last for one or several pulses until the comp high threshold is reached. At the next clock cycle, if the load is still lower than 150 mA, the device switches off again and the same operation is repeated. If at the next clock cycle the load is above 150 mA, the device automatically switches to PWM mode. To keep high efficiency in PFM mode, there is only one comparator active to keep the output voltage regulated. The AC ripple in this condition is increased, compared to the PWM mode. The amplitude of this voltage ripple in the worst case scenario is 50 mV peak to peak, (typically 30 mV peak-to-peak), with 10 µF of effective output capacitance. To avoid a critical voltage drop when switching from 0 A to full load, the output voltage in PFM mode is typically 1.5% above the nominal value in PWM mode. This is called Dynamic Voltage Positioning and allows the converter to operate with a small output capacitor and still have a low absolute voltage drop during heavy load transients. Power Save Mode is disabled by setting the PFM/PWM pin high. 8.4.3 Adjustable Current Limit The TPS6305x devices have an internal user programmable current limit that monitors the input current during start-up. This prevents high inrush current protecting the device and the application. During start-up the input current does not exceed the current limit that is set by ILIM0 pin and ILIM1 pin. Depending on the logic level applied at these two pins, switching between four different current limit-levels is possible. The variation of those values over input voltage and temperature is shown in Figure 1 through Figure 2. Adjusting the soft-start time further using the soft-start capacitor is possible. ILIM0 and ILIM1 set the current limit as listed in Table 2. Copyright © 2013–2019, Texas Instruments Incorporated Product Folder Links: TPS63050 TPS63051 Submit Documentation Feedback 13 TPS63050, TPS63051 SLVSAM8D – JULY 2013 – REVISED AUGUST 2019 www.ti.com Device Functional Modes (continued) Table 2. Adjustable Current Limit ILIM1 ILIM0 CURRENT LIMIT SET (WCSP) CURRENT LIMIT SET (HotRod) Low Low 0.4 × IIN_MAX Not Available Low High 0.5 × IIN_MAX Not Available High Low 0.65 × IIN_MAX 0.65 × IIN_MAX High High IIN_MAX IIN_MAX The ILIM0, ILIM1 pins can be changed during operation. Given the curves provided in Figure 1 through Figure 2, calculating the output current in the different condition in boost mode is possible using Equation 1 and Equation 2 and in buck mode using Equation 3 and Equation 4. V -V IN OUT V OUT Duty Cycle Boost D= Output Current Boost IOUT = 0 x IIN (1-D) (1) where • • η = Estimated converter efficiency (use the number from the efficiency curves or 0.9 as an assumption) IIN = Minimum average input current (Figure 2 to Figure 2) Duty Cycle Buck V D = OUT V IN Output Current Buck IOUT = ( 0 x IIN ) / D (2) (3) where • For η, use the number from the efficiency curves or 0.9 as an assumption. (4) 8.4.4 Device Enable The device starts operation when the EN pin is set high. The device enters shutdown mode when the EN pin is set low. In shutdown mode, the regulator stops switching, all internal control circuitry is switched off, and the load is disconnected from the input. 14 Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated Product Folder Links: TPS63050 TPS63051 TPS63050, TPS63051 www.ti.com SLVSAM8D – JULY 2013 – REVISED AUGUST 2019 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers must validate and test their design implementation to confirm system functionality. 9.1 Application Information The TPS6305x is a high efficiency, low quiescent current buck-boost converter suitable for applications where the input voltage is higher or lower than the output voltage. Continuous output current can go as high as 500 mA in boost mode and as high as 1 A in buck mode. The maximum average current in the switches is limited to a typical value of 1 A. The efficiency measurements 9.2 Typical Application L1 1.5 µH TPS63051 VIN L2 L1 2.5 V to 5.5 V C1 VIN VOUT EN FB 3.3 V / 500mA R2 1MΩ 10µF VIH or VIL ILIM0 PG PFM/ PWM ILIM1 GND SS VOUT C2 C3 10µF 10µF VIH or VIL C4 1nF Figure 8. Parameter Measurement Circuit (WCSP) L1 1.5 µH TPS63050 L2 L1 2.5 V to 5.5 V VIN VIN R1 EN C1 560kΩ 10µF VIH or VIL 3.3 V / 500mA VOUT ILIM0 FB PFM/ PWM PG GND SS R2 180kΩ R3 C5 10pF C2 C3 10µF 10µF VOUT 1MΩ C4 1nF Figure 9. Parameter Measurement Circuit (HotRod) 9.2.1 Design Requirements The design guidelines provide a component selection to operate the device within the recommended operating conditions. Copyright © 2013–2019, Texas Instruments Incorporated Product Folder Links: TPS63050 TPS63051 Submit Documentation Feedback 15 TPS63050, TPS63051 SLVSAM8D – JULY 2013 – REVISED AUGUST 2019 www.ti.com Typical Application (continued) 9.2.2 Detailed Design Procedure 9.2.2.1 Custom Design With WEBENCH® Tools Click here to create a custom design using the TPS63050 device with the WEBENCH® Power Designer. Click here to create a custom design using the TPS63051 device with the WEBENCH® Power Designer. 1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements. 2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. Compare the generated design with other possible solutions from Texas Instruments. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability. In most cases, these actions are available: • Run electrical simulations to see important waveforms and circuit performance • Run thermal simulations to understand board thermal performance • Export customized schematic and layout into popular CAD formats • Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH. The first step is the selection of the output filter components, listed in Table 3. To simplify this process, Table 4 outlines possible inductor and capacitor value combinations. Table 3. Components for Application Characteristic Curves REFERENCE DESCRIPTION MANUFACTURER TPS6305x Texas Instruments L1 1.5 µH, 2.1 A, 108 mΩ 1269AS-H-1R5M, TOKO C1, C2, C3 10 μF, 6.3 V, 0603, X5R ceramic GRM188R60J106ME84D, Murata C4 CSS C5 10pF, only needed for the HotRod package version to filter ground noise when using external resistor divider R1 Depending on the output voltage of TPS6305x, 0 Ω with TPS63051 R2 Depending on the output voltage of TPS6305x, not used withTPS63051 R3 1 MΩ 9.2.2.2 Output Filter Design Table 4. Matrix of Output Capacitor and Inductor Combinations NOMINAL INDUCTOR VALUE [µH] (1) NOMINAL OUTPUT CAPACITOR VALUE [µF] (2) 10 20 + + (3) 1 1.5 2.2 (1) (2) (3) 16 44 66 100 + + + + + + + + + Inductor tolerance and current de-rating is anticipated. The effective inductance can vary by 20% and –30%. Capacitance tolerance and bias voltage de-rating is anticipated. The effective capacitance can vary by 20% and –50%. Typical application. Other check mark indicates recommended filter combinations Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated Product Folder Links: TPS63050 TPS63051 TPS63050, TPS63051 www.ti.com SLVSAM8D – JULY 2013 – REVISED AUGUST 2019 9.2.2.3 Inductor Selection The inductor selection is affected by several parameter like inductor ripple current, output voltage ripple, transition point into power save mode, and efficiency. See Table 5 for typical inductors. Table 5. List of Recommended Inductors INDUCTOR VALUE (1) COMPONENT SUPPLIER (1) SIZE (L × W × H mm) Isat / DCR 2.1 A / 68 mΩ 1 µH TOKO 1286AS-H-1R0M 2 × 1.6 × 1.2 1.5 µH TOKO, 1286AS-H-1R5M 2 × 1.6 × 1.2 2.5 A / 95 mΩ 1.5 µH TOKO, 1269AS-H-1R5M 2.5 × 2 × 1 2.1 A / 90 mΩ 2.2 µH TOKO 1286AS-H-2R2M 2 × 1.6 × 1.2 2 A / 160 mΩ See the Third Party Product Disclaimer section. For high efficiencies, the inductor must have a low dc resistance to minimize conduction losses. Especially at high-switching frequencies, the core material has a high impact on efficiency. When using small chip inductors, the efficiency is reduced mainly due to higher inductor core losses. This needs to be considered when selecting the appropriate inductor. The inductor value determines the inductor ripple current. The larger the inductor value, the smaller the inductor ripple current and the lower the conduction losses of the converter. Conversely, larger inductor values cause a slower load transient response. To avoid saturation of the inductor, the peak current for the inductor in steady state operation is calculated using Equation 6. Only the equation which defines the switch current in boost mode is shown, because this provides the highest value of current and represents the critical current value for selecting inductor. Duty Cycle Boost D= V -V IN OUT V OUT where • D = Duty Cycle in Boost mode (5) Iout Vin ´ D = + η ´ (1 - D) 2 ´ f ´ L IPEAK where • η = Estimated converter efficiency (use the number from the efficiency curves or 0.80 as an assumption) f = Converter switching frequency (typical 2.5MHz) L = Inductor value (6) NOTE The calculation must be done for the minimum input voltage that is possible to have in boost mode. Calculating the maximum inductor current using the actual operating conditions gives the minimum saturation current of the inductor needed. It's recommended to choose an inductor with a saturation current 20% higher than the value calculated using Equation 6. Possible inductors are listed in Table 5. 9.2.2.4 Capacitor selection 9.2.2.4.1 Input Capacitor At least a 10-μF input capacitor is recommended to improve line transient behavior of the regulator and EMI behavior of the total power supply circuit. An X5R or X7R ceramic capacitor placed as close as possible to the VIN and GND pins of the IC is recommended. This capacitance can be increased without limit. 9.2.2.4.2 Output Capacitor Use of small ceramic capacitors placed as close as possible to the VOUT and PGND pins of the IC, is recommended for the output capacitor. The recommended nominal output capacitance value is 10 µF with a variance as outlined in Table 4. There is also no upper limit for the output capacitance value. Larger capacitors causes lower output voltage ripple as well as lower output voltage drop during load transients. Copyright © 2013–2019, Texas Instruments Incorporated Product Folder Links: TPS63050 TPS63051 Submit Documentation Feedback 17 TPS63050, TPS63051 SLVSAM8D – JULY 2013 – REVISED AUGUST 2019 www.ti.com 9.2.2.5 Setting the Output Voltage When the adjustable output voltage version TPS63050 is used, the output voltage is set by the external resistor divider. The resistor divider must be connected between VOUT, FB and GND. When the output voltage is regulated properly, the typical value of the voltage at the FB pin is 800 mV. The current through the resistive divider must be 100 times greater than the current into the FB pin. The typical current into the FB pin is 0.1 μA, and the voltage across the resistor between FB and GND, R2, is typically 800 mV. Based on these two values, the recommended value for R2 must be lower than 200 kΩ, in order to set the divider current at 3 μA or higher. It is recommended to keep the value for this resistor in the range of 200 kΩ. The value of the resistor connected between VOUT and FB, R1, depending on the needed output voltage (VOUT), can be calculated using Equation 7: æV ö R1 = R2 × ç OUT - 1÷ è VFB ø (7) When using the HotRod package version of the TPS63050, it is recommended to add capacitor C5, as shown in Figure 9. The capacitor on the feedback node is required to help filtering ground noise and matching the efficiency result shown in the Application Curves paragraph. 18 Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated Product Folder Links: TPS63050 TPS63051 TPS63050, TPS63051 www.ti.com SLVSAM8D – JULY 2013 – REVISED AUGUST 2019 Efficiency (%) Efficiency (%) 9.2.3 Application Curves VIN = 2.8V, V OUT = 3.3V VIN = 3.6V, V OUT = 3.3V VIN = 2.8V, V OUT = 3.3V VIN = 3.6V, V OUT = 3.3V TPS63051 TPS63051 Output Current (mA) PFM/PWM = Low Output Current (mA) VOUT = 3.3 V PFM/PWM = High Figure 11. Efficiency vs Output Current Efficiency (%) Efficiency (%) Figure 10. Efficiency vs Output Current VOUT = 3.3 V VIN = 2.5V, V OUT = 2.5V VIN = 4.8V, V OUT = 2.5V VIN = 2.5V, V OUT = 2.5V VIN = 4.8V, V OUT = 2.5V VIN = 2.5V, V OUT = 4.5V VIN = 4.8V, V OUT = 4.5V VIN = 2.5V, V OUT = 4.5V VIN = 4.8V, V OUT = 4.5V TPS63050 TPS63050 Output Current (mA) PFM/PWM = Low Output Current (mA) VOUT = 2.5 V, 4.5 V PFM/PWM = High Figure 12. Efficiency vs Output Current VOUT = 2.5 V, 4.5 V Efficiency (%) Efficiency (%) Figure 13. Efficiency vs Output Current IOUT = 10mA IOUT = 500mA IOUT = 620mA IOUT = 10mA IOUT = 500mA IOUT = 620mA TPS63051 TPS63051 Input Voltage (V) Input Voltage (V) PFM/PWM = Low VOUT= 3.3 V Figure 14. Efficiency vs Input Voltage PFM/PWM = High VOUT= 3.3 V Figure 15. Efficiency vs Input Voltage Copyright © 2013–2019, Texas Instruments Incorporated Product Folder Links: TPS63050 TPS63051 Submit Documentation Feedback 19 TPS63050, TPS63051 www.ti.com Efficiency (%) Efficiency (%) SLVSAM8D – JULY 2013 – REVISED AUGUST 2019 IOUT = 10mA IOUT = 500mA IOUT = 620mA IOUT = 10mA IOUT = 500mA IOUT = 620mA TPS63050 TPS63050 Input Voltage (V) Input Voltage (V) PFM/PWM = Low VOUT = 2.5 V PFM/PWM = High Figure 17. Efficiency vs Input Voltage Efficiency (%) Efficiency (%) Figure 16. Efficiency vs Input Voltage IOUT = 10mA IOUT = 500mA IOUT = 620mA IOUT = 10mA IOUT = 500mA IOUT = 620mA TPS63050 TPS63050 Input Voltage (V) Input Voltage (V) PFM/PWM = Low VOUT = 4.5 V PFM/PWM =High VOUT= 4.5 V Figure 19. Efficiency vs Input Voltage Power Save enabled Power Save disabled Power Save enabled Power Save disabled Output Voltage (V) Output Voltage (V) Figure 18. Efficiency vs Input Voltage TPS63051 TPS63050 Output Current (A) Output Current (A) VIN = 2.5 V VIN = 3.3 V Figure 20. Output Voltage vs Output Current 20 VOUT = 2.5 V Submit Documentation Feedback Figure 21. Output Voltage vs Output Current Copyright © 2013–2019, Texas Instruments Incorporated Product Folder Links: TPS63050 TPS63051 TPS63050, TPS63051 www.ti.com SLVSAM8D – JULY 2013 – REVISED AUGUST 2019 Power Save enabled Power Save disabled Output Voltage (V) L2 L1 VOUT_Ripple 50mV/div TPS63050 Output Current (A) TPS63051 Time 2µs/div VIN = 4.5 V VIN = 3.3 V Figure 22. Output Voltage vs Output Current IOUT = 145 mA Figure 23. Output Voltage ripple in Buck-Boost mode and PFM to PWM transition L2 L2 L1 L1 VOUT_Ripple 50mV/div Time 2µs/div TPS63051 VIN = 2.8 V IOUT = 16 mA Figure 24. Output Voltage Ripple in Boost Mode and PFM to PWM Transition VOUT_Ripple 50mV/div TPS63051 Time 2µs/div VIN = 4.2 V IOUT = 16 mA Figure 25. Output Voltage Ripple in Buck Mode and PFM to PWM Transition L2 2V/div L2 2V/div L1 2V/div L1 2V/div VOUT 20mV/div VOUT 20mV/div Iinductor 500mA/div Time 400ns/div VIN = 2.5 V Iinductor 500mA/div TPS63051 IOUT = 300 mA Figure 26. Switching Waveform in Boost Mode and PWM Time 400ns/div VIN = 4.5 V TPS63051 IOUT = 300 mA Figure 27. Switching Waveform in Buck Mode and PWM Copyright © 2013–2019, Texas Instruments Incorporated Product Folder Links: TPS63050 TPS63051 Submit Documentation Feedback 21 TPS63050, TPS63051 SLVSAM8D – JULY 2013 – REVISED AUGUST 2019 www.ti.com L2 2V/div Output Current 200 mA/div, DC Output Voltage 50 mV/div, AC L1 2V/div VOUT 20mV/div Iinductor 500mA/div TPS63051 Time 400ns/div VIN = 3.4 V IOUT = 300 mA Figure 28. Switching Waveform in Buck-Boost Mode and PWM Time 1 ms/div VIN = 2.8 V TPS63051 Load change from 0 mA to 300 mA Figure 29. Load Transient Response Output Current 200 mA/div, DC Input Voltage 200 mV/div, Offset 3V Output Voltage 50 mV/div, AC Output Voltage 20 mV/div TPS63051 Time 1 ms/div VIN = 3.6 V Load change from 0 mA to 300 mA Figure 30. Load Transient Response Time 1 ms/div Enable 5 V/div, DC Output Voltage 2V/div, DC Output Voltage 2V/div, DC Inductor Current 500 mA/div, DC VOUT = 3.3 V Inductor Current 500 mA/div, DC TPS63051 VIN = 2.5 V IOUT = 0 mA Figure 32. Start Up After Enable 22 Submit Documentation Feedback IOUT = 500 mA Figure 31. Line Transient Response Enable 5 V/div, DC Time 400 ms/div TPS63051 VOUT = 3.3 V TPS63051 Time 400 ms/div VOUT = 3.3 V VIN = 4.2 V IOUT = 0 mA Figure 33. Start Up After Enable Copyright © 2013–2019, Texas Instruments Incorporated Product Folder Links: TPS63050 TPS63051 TPS63050, TPS63051 www.ti.com SLVSAM8D – JULY 2013 – REVISED AUGUST 2019 10 Power Supply Recommendations The TPS6305x device family has no special requirements for its input power supply. The input power supply output current needs to be rated according to the supply voltage, output voltage and output current of the TPS6305x devices. 11 Layout 11.1 Layout Guidelines The PCB layout is an important step to maintain the high performance of the TPS6305x devices. • Place input and output capacitors as close as possible to the IC. Traces need to be kept short. Routing wide and direct traces to the input and output capacitor results in low-trace resistance and low parasitic inductance. • Use a common-power GND. • The sense trace connected to FB is signal trace. Keep these traces away from L1 and L2 nodes. • For the HotRod package option it is important to add a capacitor between FB node and ground to filter ground noise and to match efficiency results documented in these datasheet. 11.2 Layout Example (WCSP) C4 R1 R2 VIN C2 C1 VOUT C3 GND L1 Figure 34. TPS6305x Layout (WCSP) 11.3 Layout Example (HotRod) AGND PAC302 PAR201 PAC802 C4 R2 R1 PAU107 COR1 VOUT VINCOU1 PAU104 PAC401 C3 PAC101 PAC202 C1 GND C2 COC2 PAL101 PAL102 PAC402 COC4GND L1 Figure 35. TPS6305x Layout (HotRod) Copyright © 2013–2019, Texas Instruments Incorporated Product Folder Links: TPS63050 TPS63051 Submit Documentation Feedback 23 TPS63050, TPS63051 SLVSAM8D – JULY 2013 – REVISED AUGUST 2019 www.ti.com 11.4 Thermal Considerations Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat-generating components affect the powerdissipation limits of a given component. Two basic approaches for enhancing thermal performance are listed below: • Improving the power dissipation capability of the PCB design • Introducing airflow in the system For more details on how to use the thermal parameters, see the application notes: Thermal Characteristics (SZZA017), and Semiconductor and IC Package Thermal Metrics (SPRA953) 12 Device and Documentation Support 12.1 Custom Design With WEBENCH® Tools Click here to create a custom design using the TPS63050 device with the WEBENCH® Power Designer. Click here to create a custom design using the TPS63051 device with the WEBENCH® Power Designer. 1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements. 2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. Compare the generated design with other possible solutions from Texas Instruments. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability. In most cases, these actions are available: • Run electrical simulations to see important waveforms and circuit performance • Run thermal simulations to understand board thermal performance • Export customized schematic and layout into popular CAD formats • Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH. 12.2 Device Support 12.2.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 12.3 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 6. Related Links 24 PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY TPS63050 Click here Click here Click here Click here Click here TPS63051 Click here Click here Click here Click here Click here Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated Product Folder Links: TPS63050 TPS63051 TPS63050, TPS63051 www.ti.com SLVSAM8D – JULY 2013 – REVISED AUGUST 2019 12.4 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.5 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.6 Trademarks E2E is a trademark of Texas Instruments. WEBENCH is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.7 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.8 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2013–2019, Texas Instruments Incorporated Product Folder Links: TPS63050 TPS63051 Submit Documentation Feedback 25 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPS63050RMWR ACTIVE VQFN-HR RMW 12 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 F630 TPS63050RMWT ACTIVE VQFN-HR RMW 12 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 F630 TPS63050YFFR ACTIVE DSBGA YFF 12 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 63050 TPS63050YFFT ACTIVE DSBGA YFF 12 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 63050 TPS63051RMWR ACTIVE VQFN-HR RMW 12 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 F631 TPS63051RMWT ACTIVE VQFN-HR RMW 12 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 F631 TPS63051YFFR ACTIVE DSBGA YFF 12 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 63051 TPS63051YFFT ACTIVE DSBGA YFF 12 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 63051 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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